6b8923a623
Fix bad predecode of a0/a1 in mvsa01/mva01s.
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Fix bad pop load offset when extra sp adjust is nonzero.
2023-03-20 01:03:49 +00:00
e966e832d2
First attempt at Zcmp
2023-03-20 00:19:23 +00:00
59edb2fc5f
Fix predecode of quadrant-00 compressed instruction rs1,
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to get correct rs1 for new Zbc byte/halfword load/store
2023-03-16 19:10:43 +00:00
97bf2d06f6
Hold off first instruction fetch until pwrup_ack is first seen high
2022-11-05 14:58:47 +00:00
d3667769d2
Arrange for address buses to be 0 when processor is held in reset
2022-10-08 16:50:58 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
b994674c5a
Cleanup to avoid negative array index (legal but causes whinging)
2022-08-20 18:13:45 +01:00
3b7cd9bc96
Cleanup some unused signals
2022-08-20 16:44:39 +01:00
96e55a5446
Replace localparams with defines in rv_opcodes.vh, to avoid slightly dubious localparam to casez Z-propagation
2022-08-20 16:22:04 +01:00
6e80492723
Typo
2022-07-04 12:09:21 +01:00
36cee73d1f
Fix acmd FSM not selecting the correct hart signal for its state transitions, and make flush take precedence over debug injection in frontend. (Changes from aborted abstract access memory implementation, see abstract-access-memory branch)
2022-07-02 22:46:20 +01:00
fb15894731
Hopefully fix case where we jump to the address immediately after a
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halfword-sized word-aligned predicted-taken branch, and an
address-phase hold causes the jump target to go to the fetch address
counter, causing a spurious BTB match on the branch.
2022-06-26 15:28:08 +01:00
33cec49952
Fix bad predbranch tracking on a jump to a predicted-taken non-taken
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branch which is halfword-sized and halfword-aligned, causing CIR
and PC to diverge.
2022-06-26 15:26:04 +01:00
5193dfe477
Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,
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and enable it only on the bus compliance model checks. Trying to make
the solver's life easier in instruction_fetch_match.
2022-06-25 20:08:40 +01:00
31efd07042
Fix incorrect tracking of predictedness of fetch data phase. Fixes performance regression in RV32IMC CoreMark (now runs faster, as it should.)
2022-06-25 11:32:56 +01:00
979e80be99
Attempt to fix fetch mismatch caused by jumping halfway into a 32-bit
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instruction that precedes a taken branch.
The bookkeeping in the frontend has been tightened up so that the entire
branch instruction, and nothing but the branch instruction, is marked as a
taken branch. This required some extra state, e.g. remembering the size of
the taken branch instruction, but saved an incrementer on the BTB source
address value.
2022-06-24 19:58:21 +01:00
d9389fb23e
Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
2022-06-16 01:42:28 +01:00
f8aad6d2f3
Fix some bugs, too tired to list them, look at the diff
2022-06-15 04:05:31 +01:00
0766ec6f8a
First pass at adding branch prediction
2022-06-15 02:05:46 +01:00
3703b1fc4c
Allow use of cir_flush_behind in frontend_match formal tb
2022-06-13 20:36:15 +01:00
e68d8a6cd6
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
2022-06-13 01:23:32 +01:00
26d54d0023
Re-rewrite frontend to track the halfword-validity of in-flight transfers, and clean up the old cir_lock mechanism to be a modified flush
2022-06-12 21:01:39 +01:00
e3da922f8b
Revert previous frontend changes. Seemed promising but is a dead end for area.
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The original frontend design can probably be tweaked to support predictions.
2022-06-12 16:25:42 +01:00
940b7e4009
Actually still need 7 halfwords for full throughput in the case of sequential word-sized halfword-aligned instructions
2022-06-12 16:21:56 +01:00
8458dff083
Fix bus errors not being applied in frontend
2022-06-12 05:28:21 +01:00
23b4dbe7f3
Redesign fetch queue: 2x32 + 3x16 -> 6x16.
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Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
2022-06-12 02:44:08 +01:00
d5a202e4a5
Add standalone frontend formal tb
2022-06-11 20:14:24 +01:00
3b5879da66
Small code cleanup in frontend. The address phase alignment state no longer needs to be tracked, since we just generate word accesses always, for simplicity.
2022-06-11 14:27:59 +01:00
de9b51b787
Remove default zeroing of fetch address when no fetch is asserted -- this puts LUTs on a critical path and arguably causes more toggling than asserting the sequentially next address by default.
2022-06-11 14:26:40 +01:00
ea2b8888a4
Update copyright years
2022-06-09 00:12:01 +01:00
c93228d13e
Integrate PMP, and fix a couple of PMP bugs
2022-05-24 19:57:45 +01:00
4878a752d6
Plumb privilege state through to the bus ports
2022-05-24 18:24:34 +01:00
35651f52a7
Stronger property for correct predecode
2022-04-05 08:18:00 +01:00
20cf408632
Add fine (as well as coarse) register predecode, so that predecoded regnum can be used in bypass zeroing.
2022-04-04 20:16:19 +01:00
357efac66e
Don't decode unnecessary bits in register predecode logic
2022-04-04 18:22:09 +01:00
3c61fae9ef
Remove the halfword fetch thing, was only really useful on RISCBoy
2022-04-02 10:54:16 +01:00
887c93dbf0
Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
2022-03-02 18:35:16 +00:00
8fbffbe133
Assign full width of fifo_valid in non-reset clause (cosmetic fix)
2022-02-24 12:00:27 +00:00
b0d28447ab
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
116e34df49
Fix commented out frontend properties which relied on non-constant past reset values
2021-12-07 20:24:29 +00:00
ed6b6a3660
Cleanup order of declaration/use of a couple of wires
2021-11-25 15:16:59 +00:00
e05e9a4109
Add default_nettype none at top of every file, and default_nettype wire at bottom
2021-11-23 22:10:39 +00:00
d03a82a826
Add instruction fetch faults
2021-09-04 02:57:39 +01:00
5cc483898d
Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
2021-07-10 21:02:18 +01:00
63d661af63
Start hacking in debug support to the core -- seems to work as well as before adding debug!
2021-07-10 18:53:48 +01:00
af684c4e82
Some cleanup; correctly decode 16-bit EBREAK
2021-06-03 20:03:43 +01:00
65075df0e5
More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
2021-05-29 18:00:43 +01:00
1b252d4bda
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
2021-05-23 11:59:46 +01:00
cc6f590f2e
Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still
2021-05-22 10:16:02 +01:00
692abbad8b
Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
2021-05-22 07:55:13 +01:00
Luke Wren
Luke Wren