a536e3baa7
rvcpp sim: add A extension and M-mode traps
...
(now passes a lot of the Hazard3 tests)
2023-04-01 08:21:43 +01:00
5aee830ac0
Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH
...
(clean up fallout from Zc implementation -- ensure Readme instructions will get you to hello world)
2023-03-31 01:53:28 +01:00
56586def8d
List Zcb/Zcmp in docs, and rebuild PDF
2023-03-22 03:04:16 +00:00
95faab6f2c
Add zcmp_irq_kill test
2023-03-22 02:44:03 +00:00
f702fe5352
Add test covering all pop instructions
2023-03-20 18:26:29 +00:00
d2adc6aad7
Add tests for mva01s/mvsa01
2023-03-20 16:05:07 +00:00
142b3a81ff
Add spike-extracted output to zcmp_push
2023-03-20 15:37:38 +00:00
ee6e03e0e6
Add beginnings of Spike-able zcmp_push test
2023-03-20 14:26:53 +00:00
3b2ddee06b
Fix push/pop frame format, fix source regnums for mvsa01/mva01s
2023-03-20 02:35:18 +00:00
7702c44288
Handle timeout in runtests
2023-03-20 01:32:16 +00:00
e966e832d2
First attempt at Zcmp
2023-03-20 00:19:23 +00:00
954bae5cf1
Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
2022-08-29 14:52:01 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
6e2076268c
Update CSR readability/writability tests for new CSRs
2022-08-22 08:50:57 +01:00
6e3799eed0
First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.
2022-08-22 08:47:03 +01:00
8b630d2ac6
Whoops I needed that constant
2022-08-10 01:00:47 +01:00
64dc31244e
Add top/bottom-half IRQ test
2022-08-10 00:09:13 +01:00
a44ff9b6f1
Add test for IRQ force array
2022-08-09 23:38:14 +01:00
5894ddf15c
Fix outdated expected output in irq_set_all_with_pri test
2022-08-08 18:44:58 +01:00
ad5fd24772
- Fix signal named priority, which is a keyword in SV
...
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
2e3d69e98f
Forgot to add expected output for preemption test
2022-08-07 22:08:50 +01:00
5e72ec8941
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test
2022-08-07 22:04:42 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
185194973f
Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
2022-08-06 23:02:08 +01:00
02b303b385
Remove stray old expected output file from sw_testcases dir
2022-06-03 17:20:49 +01:00
e2c9901701
Update readme for runtests
2022-05-30 01:12:16 +01:00
2cfe6aa90e
Add test to check MPRV/MPP behaviour when executing an MRET
2022-05-29 19:51:19 +01:00
f96a0ffb75
Add test for MPRV vs PMP
2022-05-29 19:06:04 +01:00
71eff7649d
Add PMP U-mode read/write permission test
2022-05-29 18:42:44 +01:00
c8afcdbb8f
Extend umode_wfi test to check U-mode WFI doesn't stall the processor if TW=0 or PMP X check fails
2022-05-29 17:42:15 +01:00
66965ac073
Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
2022-05-28 15:36:21 +01:00
81aec325bb
ecall from U-mode has a different mcause value than ecall from M-mode
2022-05-28 12:07:29 +01:00
f2876eb51f
Fix bad mepc reported after branching to a branch in a no-X address range
2022-05-27 22:47:04 +01:00
e208652ad7
Fix misa value in csr_id test
2022-05-26 00:48:12 +01:00
5be8835365
Add missing output to pmp_write_and_lock test
2022-05-25 15:34:28 +01:00
399dcf2cb9
Add test for U-mode X permissions
2022-05-25 13:47:16 +01:00
7340765699
Add simple test to read, write and lock PMP registers
2022-05-25 02:05:24 +01:00
456810b09e
Make vcd generation optional in runtests
2022-05-24 22:56:13 +01:00
64d9f4a111
Add tests for execution of mret and wfi in U mode
2022-05-24 22:14:20 +01:00
7cfc976ef2
Set U RWX permission on all of memory in the U CSR readability test
2022-05-24 19:58:12 +01:00
f033cde874
Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
2022-05-24 17:30:24 +01:00
0199f48087
Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
2022-05-24 16:44:03 +01:00
ef35dc859d
Add zicsr to march in makefiles
2022-05-24 16:17:54 +01:00
07d4b23a9a
Add option to pass test list to runtests
2022-05-24 16:17:54 +01:00
5ab60422ad
Add minimal multicore launch code
2021-12-17 01:24:11 +00:00
88fea7acfa
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
2021-12-12 18:28:23 +00:00
719c21fec3
Add IRQ tests. Disable waves by default in runtests
2021-12-12 15:53:04 +00:00
9fb2af800f
Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
2021-12-12 14:58:50 +00:00
a232833d81
Add CSR writable test
2021-12-12 14:23:34 +00:00
7da67a0600
Similarly for minstret
2021-12-11 22:25:12 +00:00
Luke Wren