Luke Wren
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c5e85dea4c
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Add mconfigptr CSR
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2021-12-01 03:25:56 +00:00 |
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Luke Wren
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fad64bb6c9
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Bump embench test submodule
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2021-11-29 18:51:10 +00:00 |
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Luke Wren
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ba248c832a
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init.S: also print out mcause when trapping an unhandled exception
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2021-11-29 18:49:37 +00:00 |
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Luke Wren
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c8afb4ac33
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Add option for fast high-half multiplies
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2021-11-29 18:48:02 +00:00 |
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Luke Wren
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35c5e213c7
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Bump embench for working benchmarks (except md5)
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2021-11-29 00:59:14 +00:00 |
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Luke Wren
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d29bb13c4a
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Replace SSH submodule URLs with HTTPS, oops
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2021-11-28 22:26:29 +00:00 |
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Luke Wren
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94a3d43f27
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Add Hazard3's registered marchid value to hdl and docs
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2021-11-28 19:53:49 +00:00 |
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Luke Wren
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1aa9dbcddd
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Fix comment typo in APB clock crossing
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2021-11-28 17:40:57 +00:00 |
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Luke Wren
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0fafae1ab1
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Regenerate PDF
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2021-11-28 16:27:54 +00:00 |
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Luke Wren
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e7466ae4be
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Move DM data0 CSR into the M-custom space, and document this
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2021-11-28 15:52:52 +00:00 |
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Luke Wren
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9bf4d5105f
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Describe possible debug topologies. Update pdf.
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2021-11-28 09:01:23 +00:00 |
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Luke Wren
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4e2686d4ab
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Finish documenting CSRs. Draw a debug topology diagram.
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2021-11-28 08:17:23 +00:00 |
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Luke Wren
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76172cdade
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Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
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2021-11-28 06:33:35 +00:00 |
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Luke Wren
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79c29354d2
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Update docs with bitmanip instructions
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2021-11-28 03:16:45 +00:00 |
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Luke Wren
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800b21d2f5
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Remove event feedback path (not logical path) in priority encoder
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2021-11-28 02:19:01 +00:00 |
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Luke Wren
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ba27dd838f
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Bump libfpga for correct bus error response from AHBL splitter in example SoC
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2021-11-28 01:35:52 +00:00 |
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Luke Wren
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47ce2cc8ec
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Add embench submodule, with configs for hazard3
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2021-11-28 00:01:18 +00:00 |
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Luke Wren
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14a4f1a281
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Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
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2021-11-27 17:19:41 +00:00 |
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Luke Wren
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6f1a10724b
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Add bitmanip test vector generation script
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2021-11-26 23:34:06 +00:00 |
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Luke Wren
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5d093487b7
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Update README
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2021-11-26 23:33:46 +00:00 |
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Luke Wren
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1bb7e33b69
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Fix alignment of heap_ptr in init.S. Small ALU cleanup
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2021-11-26 02:59:50 +00:00 |
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Luke Wren
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7410c52aac
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Update readme
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2021-11-26 02:09:39 +00:00 |
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Luke Wren
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8398d7ecb6
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Hook up Zb* extension params on iCEBreaker FPGA
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2021-11-26 01:44:57 +00:00 |
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Luke Wren
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8bcec11c80
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Couple more silly mistakes
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2021-11-26 01:30:13 +00:00 |
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Luke Wren
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41eeb90c7d
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Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
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2021-11-26 01:29:47 +00:00 |
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Luke Wren
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998f3fdeb7
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Clean up silly mistakes
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2021-11-26 00:55:57 +00:00 |
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Luke Wren
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58c20a39d0
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First pass at implementing bitmanip. Breaks CXXRTL. Ooop
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2021-11-25 23:30:35 +00:00 |
Luke Wren
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ed6b6a3660
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Cleanup order of declaration/use of a couple of wires
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2021-11-25 15:16:59 +00:00 |
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Luke Wren
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2aac3d4f91
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Add attempt at CPU backend diagram
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2021-11-23 22:14:55 +00:00 |
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Luke Wren
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e352715fdf
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Fix IO decode in openocd/tb.cpp
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2021-11-23 22:12:51 +00:00 |
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Luke Wren
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49462a8642
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Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh
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2021-11-23 22:11:50 +00:00 |
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Luke Wren
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e05e9a4109
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Add default_nettype none at top of every file, and default_nettype wire at bottom
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2021-11-23 22:10:39 +00:00 |
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Luke Wren
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0b9b706e81
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Safer logic for load/store blocked by preceding WFI
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2021-11-23 22:01:14 +00:00 |
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Luke Wren
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4d14203586
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Update riscv-tests fork for crash loop debug test
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2021-11-23 21:58:39 +00:00 |
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Luke Wren
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60f364e561
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Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker
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2021-11-21 15:55:52 +00:00 |
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Luke Wren
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ba9a7b4a03
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Fix broken link in readme
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2021-11-21 14:58:07 +00:00 |
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Luke Wren
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c1f17b0b23
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Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
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2021-11-06 09:59:27 +00:00 |
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Luke Wren
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cc6a6c09ba
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Vaguely implement wfi
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2021-11-05 18:48:42 +00:00 |
Richard-Gordon
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375a6d60b7
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Correct mnemonic when logging unsigned sltiu instruction
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2021-10-08 12:02:37 +01:00 |
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Luke Wren
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cfe16caf41
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Remove some old todos
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2021-09-05 22:20:40 +01:00 |
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Luke Wren
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e9fccffca0
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Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
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2021-09-05 04:45:38 +01:00 |
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Luke Wren
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65bfca5fdf
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Fix latent bug with asynchronous debug entry during stalled load/store address phase
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2021-09-04 07:49:29 +01:00 |
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Luke Wren
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d03a82a826
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Add instruction fetch faults
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2021-09-04 02:57:39 +01:00 |
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Luke Wren
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9173bcf585
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Experimentally add SPI XIP to SoC (breaks FTDI UART on iCEBreaker -- need to move UART to a PMOD to avoid IO conflict)
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2021-08-21 17:04:15 +01:00 |
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Luke Wren
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e16ae06cb5
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Clean up timer
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2021-08-21 17:03:32 +01:00 |
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Luke Wren
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9dd091b7b5
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Doh typo
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2021-08-21 09:06:20 +01:00 |
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Luke Wren
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b99e5b8a67
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Convert timer to serial for smaller area. Rather untested
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2021-08-20 22:27:15 +01:00 |
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Luke Wren
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4aba165166
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First pass at a 64-bit system timer
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2021-08-20 21:49:05 +01:00 |
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Luke Wren
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924967ee72
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Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k
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2021-07-25 13:41:04 +01:00 |
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Luke Wren
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5976a8a9b7
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Add activity LED to iCEBreaker
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2021-07-25 13:13:41 +01:00 |