Commit Graph

38 Commits

Author SHA1 Message Date
Luke Wren e966e832d2 First attempt at Zcmp 2023-03-20 00:19:23 +00:00
Luke Wren 78d937e5c8 Yeet Zcb into core 2023-03-16 18:48:15 +00:00
Luke Wren 5e7bf0d604 Don't reset register file by default 2022-10-08 16:24:28 +01:00
Luke Wren 489480dc80 Revise default config values, and update docs with new values 2022-10-08 08:43:25 +01:00
Luke Wren 874cb20910 Add config headers to tb_cxxrtl instead of using defparams in Makefile 2022-10-08 08:09:26 +01:00
Luke Wren e6aaf4b801 Avoid IRQ to bus through-path when custom IRQs are disabled 2022-10-06 00:16:10 +01:00
Luke Wren c55d3f0d0b Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module. 2022-10-05 23:53:04 +01:00
Luke Wren 2ae2463b97 First stab at adding wake/sleep state machine 2022-08-28 19:50:04 +01:00
Luke Wren 6e3799eed0 First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested. 2022-08-22 08:47:03 +01:00
Luke Wren 15cb21ae43 First pass at implementing the new IRQ controls. Works well enough that the old tests pass :) 2022-08-07 20:51:12 +01:00
Luke Wren 185194973f Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains 2022-08-06 23:02:08 +01:00
Luke Wren b7d9defcf2 Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3 2022-07-05 03:37:19 +01:00
Luke Wren 0766ec6f8a First pass at adding branch prediction 2022-06-15 02:05:46 +01:00
Luke Wren ea2b8888a4 Update copyright years 2022-06-09 00:12:01 +01:00
Luke Wren ae2784d0ea PMP config: separate granularity config from hardwired region config. Give correct read value for G > 1. 2022-06-03 17:09:43 +01:00
Luke Wren e0a9fb7312 Add option to hardwire PMP regions, or reduce their granularity 2022-06-03 01:19:03 +01:00
Luke Wren d62861159f First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python. 2022-05-24 16:17:54 +01:00
Luke Wren 5466c8131e Sketch in PMP implementation 2022-05-23 18:06:23 +01:00
Luke Wren 5f4127948d Add a parameter to control register file reset, instead of the weird ifdef tree 2022-05-23 13:29:44 +01:00
Luke Wren 43e0b1d16a Implement Zbkb (untested) 2022-05-06 17:36:25 +01:00
Luke Wren 2c8f3974d0 Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i. 2022-04-09 13:49:16 +01:00
Luke Wren be80bd4c18 Radical opinion, we should have good performance by default, not bad 2022-04-02 17:53:22 +01:00
Luke Wren 7dc5046505 Perf option for dedicated branch comparator 2022-04-02 11:40:47 +01:00
Luke Wren b0b8703ea4 Support up to 128 IRQs 2022-03-13 09:27:43 +00:00
Luke Wren bf15b6c49f Fix forward reference to net 2022-01-18 23:02:39 +00:00
Luke Wren b0d28447ab New license headers: DWTFPL -> Apache 2.0 2021-12-13 23:23:40 +00:00
Luke Wren 5e17bb805e Add basic support for lr/sc instructions from the A extension 2021-12-04 15:02:31 +00:00
Luke Wren c5e85dea4c Add mconfigptr CSR 2021-12-01 03:25:56 +00:00
Luke Wren c8afb4ac33 Add option for fast high-half multiplies 2021-11-29 18:48:02 +00:00
Luke Wren 94a3d43f27 Add Hazard3's registered marchid value to hdl and docs 2021-11-28 19:53:49 +00:00
Luke Wren 58c20a39d0 First pass at implementing bitmanip. Breaks CXXRTL. Ooop 2021-11-25 23:30:35 +00:00
Luke Wren 63d661af63 Start hacking in debug support to the core -- seems to work as well as before adding debug! 2021-07-10 18:53:48 +01:00
Luke Wren 3312ea7022 Add draft UART DTM 2021-07-08 17:57:46 +01:00
Luke Wren 6a38fc33a6 Allow MHARTID to be configured at instantiation 2021-07-07 16:08:08 +01:00
Luke Wren 5f8d217395 Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0 2021-05-31 17:54:12 +01:00
Luke Wren 12851d3742 Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set 2021-05-30 19:52:46 +01:00
Luke Wren 565b76672a Make MVENDORID/MARCHID/MIMPID configurable 2021-05-30 18:42:43 +01:00
Luke Wren 844fa8f97f Rename hazard5 -> hazard3 2021-05-21 03:46:29 +01:00