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201 Commits

Author SHA1 Message Date
chxin66 f2e71a3deb
composed Dense & added unit test (#312) 
if shape is 3D or larger, implement it as reshape + fc + reshape

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-03-25 10:49:39 +08:00
Sven 097f8d74cd
Refine customized op support (#327) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-03-22 23:00:52 +08:00
Sven 08500158ba
Fix build error with clang (#326) 
Signed-off-by: ZhangXiang <Xiang.Zhang@verisilicon.com>
 2022-03-22 14:51:12 +08:00
Dahan Gong aaaeda1846
doc: fix some comments (#322) 2022-03-17 12:21:20 +08:00
Zhouheng Zheng b02aa8b8c4
Added customize operator APIs(#315) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2022-03-09 12:10:08 +08:00
Sven e63059857b
Update reshape to reshape2 (#310) 
Update built-in op reshape to reshape2

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-03-01 17:04:02 +08:00
chxin66 242a6bd05a
Add pad value for grouped_conv1d (#292) 
https://github.com/VeriSilicon/TIM-VX/issues/284

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2022-02-21 19:11:36 +08:00
Sven 7c1a00213b
[New API] Add compile_option support - relax_mode (#285) 
Added new API for tim::vx::Context::CreateGraph with a CompileOption

Only one option added in CompileOption:
    relax_mode : Run float32 mode with bfloat16

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-02-09 10:52:11 +08:00
liyuenan e2180a6341
Support that op's all inputs are constant (#264) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-14 12:34:38 +08:00
Antkillerfarm 36e6afa567
add alpha & beta parameters for HardSigmoid (#265) 2022-01-13 14:17:19 +08:00
Zongwu.Yang 4229ad88b3
support conv3d (#238) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2022-01-11 14:13:15 +08:00
liyuenan 7c63ba621e
Map OneHot & unit test (#258) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-05 22:04:49 +08:00
Goose Bomb 8e4ab68213
Fix warnings relating to inheritance (#256) 
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test

* Fix warnings relating to inheritance
 2022-01-04 14:35:17 +08:00
chxin66 cea11422b8
Added RNNCell & unit test (#249) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-29 11:08:24 +08:00
liyuenan 75d39e2cfd
Support layout inference for transpose (#250) 
Added interface GetProdeucerOp(tensor) in Graph


Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-29 11:06:28 +08:00
Zongwu.Yang aed3a48248
Add layout inference and unit test for BatchNorm (#243) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-12-22 09:47:57 +08:00
chxin66 1f85d21558
mapped signal frame & unit test (#234) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-09 10:33:40 +08:00
chxin66 dc31091db5
mapped groupedconv1d & unit test (#233) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-06 19:20:13 +08:00
Antkillerfarm b38bd41933
add DataLayout::IcOcWH for TVM usage (#231) 2021-11-30 21:33:14 +08:00
chxin66 8b1ec74f07
support DMAbuffer (#214) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-11-21 22:46:20 +08:00
Zongwu.Yang c90efe70c5
Refine Lite API (#221) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-11-19 20:30:26 +08:00
Sven e81cba0526
Update license header (#216) 
* Update license for nbg_parser.c

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

* Update license for headers

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-11-12 10:07:28 +08:00
chxin66 516a914c73
Mapped Erf operation & unit tests (#211) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-11-10 20:07:06 +08:00
Zongwu.Yang d019a76db5
Add function for lite driver handle (#209) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-11-10 20:05:31 +08:00
Antkillerfarm 214cbe5874
add Global Pool2d & Adaptive Pool2d (#210) 2021-11-09 20:25:02 +08:00
Kee c9086e0afe
Update Div OP - add scale param (#203) 
Update Div OP - add scale param
 2021-11-04 10:44:52 +08:00
chxin66 e4cc133d36
Add SVDF support - only FLOAT32 supported 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-10-29 16:19:15 +08:00
xiang.zhang 830f26c897 Add headers for nbg_parser 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-10-08 13:38:15 +08:00
lilei 8e63e8c8f3 refine tensor to support attribute access 2021-09-27 17:20:41 +08:00
lilei 073a79f463 add ops.h to contain all operation header file 2021-09-17 22:41:44 +08:00
Chen Xin 633075f689 delete Non-approximate option, recommend to use 
the approximate option

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-09-07 22:44:57 +08:00
Chen Xin 6f2e92ffa6 Add shuffle_channel support & test for tim::vx 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-09-07 22:44:57 +08:00
Antkillerfarm fa930678ea
add Programming_Guide.md & Operators.md (#157) 2021-08-24 12:42:46 +08:00
chxin66 5e09e98c1a
Add Gelu support for tim::vx (#153) 
* Add map for Gelu

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-08-17 20:37:12 +08:00
jing.tang a364c3eafb add Swish op 2021-08-16 19:30:14 +08:00
xiang.zhang e27e15925c Add unidirectional sequence lstm support 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-08-09 13:43:33 +08:00
Kainan Cha 6a949bb315 Add align_corners support for SpatialTransformer 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-08-03 10:52:51 +08:00
yuenan.li 2f8f87d1cb Add Clone API for SpatialTrasformer 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 17:34:57 +08:00
zhao.xia 8aa11f5f29 Support SpatialTransformer 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-07-06 12:56:28 +08:00
yuenan.li 29f1efc492 add API 'Clone' to tim_vx op and support default layout inference 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 12:29:18 +08:00
zhao.xia 21ecf5262e Add map for Matmul 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-29 16:06:35 +08:00
zhao.xia 3fa2bf519a Add map for moments 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-29 15:58:51 +08:00
zhao.xia 0ed1e8947f Add new APIs for conv, deconv and fc 
The new apis remvoe weights, oc_count and ksize.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-07 21:48:13 +08:00
zhao.xia f59f26412b Add GroupedConv2d 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-04 16:53:25 +08:00
zhao.xia 353feca56a Add tile 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 18:29:32 +08:00
zhao.xia bd9c5df70a Add pad parameter to pool2d 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 16:28:42 +08:00
zhao.xia 748658e47d Add Unstack 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 16:24:31 +08:00
zhao.xia 8a15abf12b Add ScatterND 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 11:22:58 +08:00
Kainan Cha 39bd5ddd32 Add support for Linear Activation 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-02 17:10:57 +08:00
yuenan.li 1f08618403 Supprt layout inference for Operations 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-02 00:53:11 +08:00
jing.tang ebad62ab02 [NNRT-1111] add memory layout for doc 2021-06-01 16:59:55 +08:00
zhao.xia 26948d6646 Rename Unmaxpool2d to MaxUnpool2d 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-31 12:48:51 +08:00
Nightingale 9c60671031
Add map for UnMaxpool2d (#83) 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-28 17:09:26 +08:00
Kainan Cha 18a928ee69 Add Op MaxpoolWithArgmax 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-27 18:59:35 +08:00
liyuenan fae5cede7a
Support layout inference for ops (#77) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-27 10:33:44 +08:00
zhao.xia a1ba85691a Add map for LogSoftmax 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-26 11:37:16 +08:00
zhao.xia 37f686c34d Remove DownScaleSizeRounding type 
Use RoundType instead of DownScaleSizeRounding.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-25 16:48:50 +08:00
Kainan Cha eccc117ec5 Remove unused enum 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-25 15:00:46 +08:00
Nightingale f90f3eedfd
Add map for Resize1d (#69) 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-25 10:27:23 +08:00
Kainan Cha d0dadbc0fb Add support for FloorDiv 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-25 01:20:43 +08:00
Nightingale 33fd1f0c58
Add map for DeConv1d (#62) 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-24 23:41:15 +08:00
Sven 410cd8e516
Refine the cmake build (#63) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-24 13:40:37 +08:00
jing.tang 3339135c82 add docs for ops 2021-05-21 18:39:59 +08:00
jing.tang a85fe89cf6 add docs for ops 2021-05-21 18:39:59 +08:00
zhao.xia be0a566042 Add map for Conv1D 
Convolution 1D operation, support float32, int8, int16, uint8.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-21 12:46:56 +08:00
zhao.xia 88f7141cfe Support LayerNormalization 
Layer normalization only support float32 data type.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-21 12:46:19 +08:00
zhao.xia b4b6a369a7 Add map for InstanceNormalization 
Currently instance normalization only support float32 data type.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-20 12:41:25 +08:00
xiang.zhang b1b7eadefc Add group parameter for deconv API 
Limitation: only support depthwise deconvolution

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-20 06:15:28 +08:00
Nightingale 90e451749f
Update tim lite api (#48) 
* Add lenet sample with TIM-LITE

A lenet sample with TIM-LITE executable.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>

* Update TIM-LITE API

Update handle usage.
Use Execution::Trigger instead of Execution::Exec

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>

* Update lenet lite case to use new api

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-17 22:08:10 +08:00
Sven 66dd29703e
Refine cmake build: add gtest (#47) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-17 13:04:45 +08:00
liyuenan cc3b8c1fe0
Support layout inference for FC and Resize (#45) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-15 22:42:11 +08:00
liyuenan 55ef50385e
Change back the inferface name (#44) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-14 20:08:53 +08:00
zhao.xia 0a034252c6 Support tim-lite 
Lite module for vip lite driver.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-14 17:37:35 +08:00
Zongwu.Yang b38cad9f1d
Add data layout for kernel to support TVM conv2d (#40) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-14 14:00:02 +08:00
liyuenan 748274143b
support layout inference for operations (#39) 
Add layout inference support for space2depth, depth2space, space2batch, batch2space, pad and
reduce.

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-13 22:27:23 +08:00
Kainan Cha d645494dcc Refine support for data copy operation 
* Properly support tensor handle for both input and output
* Fix UT to use size_in_bytes instead of size in elements

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-12 22:59:36 +08:00
Kainan Cha 301d88a5a6 Add support for relational ops 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 23:39:22 +08:00
Kainan Cha d92e08e502 Add support for Cast and Floor operation 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 18:45:28 +08:00
Kainan Cha 2b29d5d41c Fix file permission 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 11:01:21 +08:00
Kainan Cha c2e10efb50 Add support for Reorg 
The Reorg implementation is that of YOLOv2.

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 10:57:56 +08:00
Sven a42517fdce
Align directory name to namespace for layout inference (#38) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-11 09:46:46 +08:00
Zongwu.Yang 22d423714f
Optimize permute op for constant tensor (#37) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-10 23:06:04 +08:00
xiang.zhang 205f7d53f0 Align declare and definition for TensorSpec 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-08 11:46:05 +08:00
Zongwu.Yang 77b801a590
Add layout inference feature (#34) 
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass

Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-08 09:29:47 +08:00
zhengzhouheng eff71c38bf add argmin and argmax op 2021-04-16 00:34:29 +08:00
yuenan.li c9d3416c6b Add the Squeeze op 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-04-15 11:22:48 +08:00
Jia 11480f18f3 Store operation into graph 
because the operation is a shared pointor, in app, the operation is
created as:
    auto op = graph->CreateOperation();

uses natively think the operation had been register into the graph and
would not manage the op locally.

if running the graph in another fucntion instead of the function that
create the operation, the operation would had been delete.

so the operation should be stored into the graph.

Signed-off-by: Jia <juku.jia@verisilicon.com>
 2021-04-15 11:21:56 +08:00
zhengzhouheng dc67e9ac63 add the Stack op 2021-04-07 19:57:28 +08:00
Kainan Cha 165b3fcf8f Minor clean up 
Fix typos and move functions into appropriate files

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-04-07 13:03:56 +08:00
zhengzhouheng 07fc3b9914 add the clip, dropout, batchnorm op 2021-04-07 13:00:41 +08:00
Kainan Cha 90a52ea6c9 Add support for Mish, SoftRelu and HardSigmoid 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-31 12:00:02 +08:00
yuenan.li b5f2666e92 Map Select 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-03-25 17:27:04 +08:00
Kainan Cha 0d7afd9d51 Minor cleanup 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-19 11:12:12 +08:00
Kainan Cha c46904c339 Add op support for Deconv2d 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-02-26 09:54:01 +08:00
zhengzhouheng c8b0180e7a fix the bug of pooling layer output shape mismatch 2021-02-24 10:15:24 +08:00
xiang.zhang 9d44b4477b Added NBG support 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-02-22 11:38:21 +08:00
yuenan.li bd4d277ac1 Support multiply attribute for tensor spec 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-02-01 14:10:03 +08:00
yuenan.li 44af63b9e9 [NNRT-811]Map Slice 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-01-22 14:32:43 +08:00
yuenan.li 0e422b1e6a Map [NNRT-824]LeakyRelu/[NNRT-817]LogicalOr/And/[NNRT-831]GatherNd 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-01-19 16:44:43 +08:00
Jiang Bo 90b7a6fc32 Rename Op 'Permute' to 'Transpose' 
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-01-12 11:21:51 +08:00
Jiang Bo 7972af0697 Initial Commit for VERSION 1.1.28 
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-01-11 18:27:48 +08:00