26c3bcb78f
Merge pull request #42 from danielmlynek/readme_upd_for_aldec1
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Riviera simulator added to Readme
2020-03-04 11:13:19 -05:00
f2e40ff2c8
Update README.md
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Updated version number to 1.5.1
2020-02-28 14:21:35 -08:00
cbb7080411
Update RISC-V_SweRV_EH1_PRM.pdf
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Minor update
2020-02-28 14:19:14 -08:00
040d2807c9
Fix Riviera -l switch
2020-02-27 09:59:42 +01:00
e1aec7d193
Riviera simulator added to Readme
2020-02-27 09:40:53 +01:00
0dbee1c24c
Merge pull request #30 from danielmlynek/make_for_riviera
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Make for riviera
2020-02-26 19:38:57 -06:00
91ac750284
Update release-notes.md
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Remove from the 1.5 release notes items that were accidentally carried over from a previous release.
2020-02-26 19:27:55 -06:00
7d85fc74d0
Delete flist.riviera
2020-02-25 16:54:32 +01:00
0070c22195
Merge branch 'master' into make_for_riviera
2020-02-25 16:53:53 +01:00
70b6f74b11
Merge pull request #40 from olofk/fusesoc-1.5
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Add initial FuseSoC support
2020-02-24 15:39:31 -06:00
cb5a7a141d
Update dmi_jtag_to_core_sync.v
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Follow syntax used in internal repository.
2020-02-24 15:00:46 -06:00
2a1d9be0c2
Update dmi_jtag_to_core_sync.v
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Fixed incorrect syntax
2020-02-24 14:52:54 -06:00
63e74e2391
Add initial FuseSoC support
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This adds support for using SweRV with FuseSoC. For SweRV itself, it allows linting with verilator running simulations with the provided testbench using most available simulators and doing synthesis for resource usage analysis with Vivado. It also allows SweRV to be integrated into FuseSoC-built SoCs, such as [SweRVolf](https://github.com/chipsalliance/Cores-SweRVolf )
**Quickstart**
1. Install [FuseSoC](https://github.com/olofk/fusesoc ) and Verilator
2. Create an empty workspace directory. All subsequent commands are run from this directory
3. Add SweRV as FuseSoC library `fusesoc library add swerv https://github.com/chipsalliance/Cores-SweRV `
4. Run linting with Verilator `fusesoc run --target=lint chipsalliance.org:cores:SweRV_EH1`
5. Run testbench with default simulator (Verilator) `fusesoc run --target=sim chipsalliance.org:cores:SweRV_EH1`
6. Run testbench with another supported simulator (e.g. ModelSim) `fusesoc run --target=sim --tool=modelsim chipsalliance.org:cores:SweRV_EH1`
7. Run synthesis with Vivado `fusesoc run --target=synth chipsalliance.org:cores:SweRV_EH1`
* configs/swerv_config_gen.py is a wrapper around `configs/swerv.config` to dynamically create a SweRV configuration by setting parameters in the FuseSoC .core file
* swerv.core is the FuseSoC core description file
* tools/vivado.tcl marks `common_defines.vh` as a global include file when using Vivado
2020-02-24 21:28:54 +01:00
ee77552301
Version 1.5
2020-02-19 18:57:15 -08:00
cecb89057a
Version 1.5
2020-02-19 18:25:44 -08:00
b65d4dd8f1
Version 1.5
2020-02-19 18:25:04 -08:00
790c48cd0b
Version 1.5
2020-02-19 18:24:28 -08:00
36675abd25
Updated release notes.
2020-02-19 18:18:48 -08:00
480c765eb4
Cleanup release notes.
2020-02-19 07:07:31 -08:00
d0c6e56012
Formatting changes.
2020-02-18 13:51:15 -08:00
a44ef01adf
Changed version to 1.5.
2020-02-18 13:41:42 -08:00
9228e01812
Added release notes for version 1.5.
2020-02-18 13:40:11 -08:00
e57b032cd7
makefile updated for ALDECs riviera
2019-12-12 08:46:21 +01:00
6ca86d86a9
makefile updated for ALDECs riviera
2019-12-12 08:45:34 +01:00
1651bdf99a
Merge pull request #29 from arupde171/master
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Fixed FPGA build error
2019-12-06 17:50:19 -05:00
aa2bc2269d
Fixed FPGA build error
2019-12-06 09:50:38 -08:00
c89f6b7511
Update README.md
2019-11-20 11:02:15 -08:00
9840fabd5c
Added SweRV CoreMark document
2019-11-20 10:39:09 -08:00
3820e84e20
Move declarations to top of Verilog file to fix fpga compile issues.
2019-10-15 13:14:36 -07:00
5fce5b0a26
Update README.md
2019-09-08 11:15:25 -04:00
cf4d56c78c
Added basic commit register update trace in exec.log
2019-09-08 11:13:17 -04:00
761e69df4e
Update release-notes.md
2019-09-04 17:44:15 -04:00
811e9c3d24
Change clock header instance name in beh_lib.sv
2019-09-04 14:39:10 -07:00
35bc589b09
Merge branch 'master' of https://github.com/chipsalliance/Cores-SweRV
2019-09-04 13:32:48 -07:00
b35d7e9e1b
Make the FPGA optimization code work with the latest version of Verilator. Move JTAG TAP to swerv_wrapper module.
2019-09-04 13:29:39 -07:00
fc331027c2
Conditioned declaration of finished per issue #13
2019-09-03 21:35:43 -04:00
2108e722c8
Merge branch 'master' of https://github.com/chipsalliance/Cores-SweRV
2019-08-13 15:48:48 -07:00
68f4383d96
Update RISC-V SweRV EH1 PRM.pdf
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Rev. 1.2
2019-08-13 15:48:28 -07:00
4e161e6c3b
Minor cleanup in config script.
2019-08-13 15:47:53 -07:00
189ce25027
Updated release notes
2019-08-13 16:42:26 -05:00
8242950a58
Fixed branch numbers
2019-08-13 15:30:00 -05:00
c5a699aa40
Fixed release notes
2019-08-13 15:08:45 -05:00
d9bb036633
Updated hello world message. Updated last compilation time.
2019-08-13 12:57:04 -07:00
7ff8d7fb5a
Untabified files.
2019-08-13 12:48:48 -07:00
85a510db19
Updated release notes.
2019-08-13 12:43:09 -07:00
ac92841999
Adjust CSR MFDC reset value for the AXI bus.
2019-08-13 12:38:50 -07:00
e20f012de7
Removed refernce to version 1.1.
2019-08-10 13:42:48 -07:00
40db638de6
Mention 1.1.1 release.
2019-08-10 13:23:53 -07:00
e7f57a0d5d
Added 1.1.1 release notes.
2019-08-10 13:23:08 -07:00
6a528a9a8b
Ignore ebreak/ecall w.r.t MINSTRET
2019-08-09 19:18:41 -07:00
aprnath
Thomas Wicki
Daniel Mlynek
jrahmeh
danielmlynek
Olof Kindgren
Joseph Rahmeh
danielm
Arup De
Arup De
Ajay Nath