2df1179994
Wire privilege through from core to bus masters. Tied off inside core.
2022-05-24 14:05:26 +01:00
c0b5d73cbd
Typo in for loop, surprised Yosys accepted this
2022-05-23 18:15:36 +01:00
5466c8131e
Sketch in PMP implementation
2022-05-23 18:06:23 +01:00
06647b78c6
Fix IALIGN fault to trap on the control flow instruction instead of its target
2022-05-23 16:25:43 +01:00
da244f54c3
Remove unused FAKE_DUALPORT option from regfile
2022-05-23 16:22:01 +01:00
f849517202
Split CSR addresses into separate header file
2022-05-23 15:54:37 +01:00
5f4127948d
Add a parameter to control register file reset, instead of the weird ifdef tree
2022-05-23 13:29:44 +01:00
df0fd536eb
Fix IRQ priority to match the priv spec
2022-05-23 12:56:37 +01:00
96a9ee18e1
Add IALIGN exception to non-RVC implementations
2022-05-23 12:47:48 +01:00
c4e81922da
Don't store bit 1 of mepc on non-RVC implementations
2022-05-23 12:27:07 +01:00
210dbeae64
Correct the name and operation of the brev8 (formerly rev.b) instruction
2022-05-20 15:28:18 +01:00
a2582976fc
Fix opcodes for zip/unzip, which are wrong in the bitmanip copy of the Zbkb spec, but correct in the crypto copy of that spec
2022-05-20 15:15:37 +01:00
43e0b1d16a
Implement Zbkb (untested)
2022-05-06 17:36:25 +01:00
2c8f3974d0
Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i.
2022-04-09 13:49:16 +01:00
35651f52a7
Stronger property for correct predecode
2022-04-05 08:18:00 +01:00
20cf408632
Add fine (as well as coarse) register predecode, so that predecoded regnum can be used in bypass zeroing.
2022-04-04 20:16:19 +01:00
357efac66e
Don't decode unnecessary bits in register predecode logic
2022-04-04 18:22:09 +01:00
be80bd4c18
Radical opinion, we should have good performance by default, not bad
2022-04-02 17:53:22 +01:00
7dc5046505
Perf option for dedicated branch comparator
2022-04-02 11:40:47 +01:00
3c61fae9ef
Remove the halfword fetch thing, was only really useful on RISCBoy
2022-04-02 10:54:16 +01:00
7b8fe43c1c
Fix bad timing of predecoded regnum register update (thanks BMC)
2022-04-02 10:11:55 +01:00
b80b09afe5
Typo -- fully encode all 128 possible IRQs
2022-03-15 09:01:55 +00:00
b0b8703ea4
Support up to 128 IRQs
2022-03-13 09:27:43 +00:00
887c93dbf0
Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
2022-03-02 18:35:16 +00:00
96c69d0bb0
Cut in->out paths on debug halt/resume request
...
Should be harmless, because in practice these should always be driven from a register
in the DM, but still better to cut the path
2022-03-01 21:14:49 +00:00
8fbffbe133
Assign full width of fifo_valid in non-reset clause (cosmetic fix)
2022-02-24 12:00:27 +00:00
9ed99d8695
Use define to guard X-checks, instead of hot comments
2022-02-24 10:35:16 +00:00
bf15b6c49f
Fix forward reference to net
2022-01-18 23:02:39 +00:00
0a369efc06
Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
2021-12-18 15:41:05 +00:00
1b0e205f87
Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami
2021-12-18 14:51:46 +00:00
6b8d4913ee
Remove unnecessary mux of mw_result -> m_result
2021-12-18 01:34:25 +00:00
79fec3a2f5
Overload mw_result register for capturing AMO read data. Save some LCs.
2021-12-18 01:24:26 +00:00
28b53ef7b5
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
2021-12-18 00:35:13 +00:00
7485269ddf
Use the branch target adder for load/store addresses. Preparing for AMO ALU deletion
2021-12-17 22:36:40 +00:00
a35739baf1
Fix AMO failing to loop on global monitor write fail
2021-12-17 17:04:22 +00:00
b0d28447ab
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
f1cda26bcc
Oops, try a little harder this time to ensure local monitor is cleared by sc.w errors _always_, even if lined up with trap entry stalls etc
2021-12-12 23:32:01 +00:00
25b44d04cf
Add more properties wrt AMO. Fix awful bugs in interaction between AMOs and prior lr/sc, prior load/store exception, or IRQ which is asserted then deasserted. Fix sc with HRESP=1 HEXOKAY=1 not clearing the local monitor (not a bug, but unfriendly).
2021-12-12 23:24:25 +00:00
88fea7acfa
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
2021-12-12 18:28:23 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
2bbc3637a2
Simplify CSR update logic. Showed promise in block synth but no difference to example soc. Still cleaner RTL.
2021-12-12 00:38:30 +00:00
9460b3cd04
Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
2021-12-11 15:52:34 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
7d2fa6a049
Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic
2021-12-09 06:26:31 +00:00
116e34df49
Fix commented out frontend properties which relied on non-constant past reset values
2021-12-07 20:24:29 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
6ef3503ef5
Add A bit to MISA, update docs
2021-12-07 05:10:20 +00:00
93be227d8a
Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
2021-12-06 20:12:23 +00:00
ed22d502fd
Fix bus stall getting stuck high when a bus fault exception isn't immediately accepted by the frontend
2021-12-06 19:28:21 +00:00
50d3d5d3b3
Maintain AMO IRQ holdoff when transitioning from data phase to error phase, to prevent error possibly being flushed
2021-12-06 19:27:20 +00:00
Luke Wren
Luke Wren