Luke Wren
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51750eb81d
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Add mstatus.tw to control U-mode WFI, and prevent mret execution in U-mode.
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2022-05-24 21:12:44 +01:00 |
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Luke Wren
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c93228d13e
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Integrate PMP, and fix a couple of PMP bugs
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2022-05-24 19:57:45 +01:00 |
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Luke Wren
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4878a752d6
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Plumb privilege state through to the bus ports
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2022-05-24 18:24:34 +01:00 |
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Luke Wren
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f033cde874
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Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
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2022-05-24 17:30:24 +01:00 |
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Luke Wren
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0199f48087
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Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
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2022-05-24 16:44:03 +01:00 |
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Luke Wren
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d62861159f
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First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
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2022-05-24 16:17:54 +01:00 |
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Luke Wren
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2df1179994
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Wire privilege through from core to bus masters. Tied off inside core.
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2022-05-24 14:05:26 +01:00 |
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Luke Wren
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c0b5d73cbd
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Typo in for loop, surprised Yosys accepted this
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2022-05-23 18:15:36 +01:00 |
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Luke Wren
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5466c8131e
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Sketch in PMP implementation
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2022-05-23 18:06:23 +01:00 |
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Luke Wren
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06647b78c6
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Fix IALIGN fault to trap on the control flow instruction instead of its target
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2022-05-23 16:25:43 +01:00 |
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Luke Wren
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da244f54c3
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Remove unused FAKE_DUALPORT option from regfile
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2022-05-23 16:22:01 +01:00 |
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Luke Wren
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f849517202
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Split CSR addresses into separate header file
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2022-05-23 15:54:37 +01:00 |
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Luke Wren
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5f4127948d
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Add a parameter to control register file reset, instead of the weird ifdef tree
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2022-05-23 13:29:44 +01:00 |
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Luke Wren
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df0fd536eb
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Fix IRQ priority to match the priv spec
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2022-05-23 12:56:37 +01:00 |
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Luke Wren
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96a9ee18e1
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Add IALIGN exception to non-RVC implementations
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2022-05-23 12:47:48 +01:00 |
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Luke Wren
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c4e81922da
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Don't store bit 1 of mepc on non-RVC implementations
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2022-05-23 12:27:07 +01:00 |
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Luke Wren
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210dbeae64
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
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Luke Wren
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a2582976fc
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Fix opcodes for zip/unzip, which are wrong in the bitmanip copy of the Zbkb spec, but correct in the crypto copy of that spec
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2022-05-20 15:15:37 +01:00 |
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Luke Wren
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43e0b1d16a
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Implement Zbkb (untested)
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2022-05-06 17:36:25 +01:00 |
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Luke Wren
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2c8f3974d0
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Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i.
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2022-04-09 13:49:16 +01:00 |
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Luke Wren
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35651f52a7
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Stronger property for correct predecode
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2022-04-05 08:18:00 +01:00 |
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Luke Wren
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20cf408632
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Add fine (as well as coarse) register predecode, so that predecoded regnum can be used in bypass zeroing.
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2022-04-04 20:16:19 +01:00 |
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Luke Wren
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357efac66e
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Don't decode unnecessary bits in register predecode logic
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2022-04-04 18:22:09 +01:00 |
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Luke Wren
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be80bd4c18
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Radical opinion, we should have good performance by default, not bad
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2022-04-02 17:53:22 +01:00 |
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Luke Wren
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7dc5046505
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Perf option for dedicated branch comparator
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2022-04-02 11:40:47 +01:00 |
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Luke Wren
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3c61fae9ef
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Remove the halfword fetch thing, was only really useful on RISCBoy
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2022-04-02 10:54:16 +01:00 |
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Luke Wren
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7b8fe43c1c
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Fix bad timing of predecoded regnum register update (thanks BMC)
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2022-04-02 10:11:55 +01:00 |
Luke Wren
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b80b09afe5
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Typo -- fully encode all 128 possible IRQs
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2022-03-15 09:01:55 +00:00 |
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Luke Wren
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b0b8703ea4
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Support up to 128 IRQs
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2022-03-13 09:27:43 +00:00 |
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Luke Wren
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887c93dbf0
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Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
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2022-03-02 18:35:16 +00:00 |
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Luke Wren
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96c69d0bb0
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Cut in->out paths on debug halt/resume request
Should be harmless, because in practice these should always be driven from a register
in the DM, but still better to cut the path
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2022-03-01 21:14:49 +00:00 |
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Luke Wren
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8fbffbe133
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Assign full width of fifo_valid in non-reset clause (cosmetic fix)
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2022-02-24 12:00:27 +00:00 |
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Luke Wren
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9ed99d8695
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Use define to guard X-checks, instead of hot comments
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2022-02-24 10:35:16 +00:00 |
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Luke Wren
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bf15b6c49f
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Fix forward reference to net
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2022-01-18 23:02:39 +00:00 |
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Luke Wren
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0a369efc06
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Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
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2021-12-18 15:41:05 +00:00 |
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Luke Wren
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1b0e205f87
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Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami
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2021-12-18 14:51:46 +00:00 |
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Luke Wren
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6b8d4913ee
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Remove unnecessary mux of mw_result -> m_result
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2021-12-18 01:34:25 +00:00 |
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Luke Wren
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79fec3a2f5
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Overload mw_result register for capturing AMO read data. Save some LCs.
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2021-12-18 01:24:26 +00:00 |
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Luke Wren
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28b53ef7b5
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Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
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2021-12-18 00:35:13 +00:00 |
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Luke Wren
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7485269ddf
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Use the branch target adder for load/store addresses. Preparing for AMO ALU deletion
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2021-12-17 22:36:40 +00:00 |
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Luke Wren
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a35739baf1
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Fix AMO failing to loop on global monitor write fail
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2021-12-17 17:04:22 +00:00 |
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Luke Wren
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b0d28447ab
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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Luke Wren
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f1cda26bcc
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Oops, try a little harder this time to ensure local monitor is cleared by sc.w errors _always_, even if lined up with trap entry stalls etc
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2021-12-12 23:32:01 +00:00 |
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Luke Wren
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25b44d04cf
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Add more properties wrt AMO. Fix awful bugs in interaction between AMOs and prior lr/sc, prior load/store exception, or IRQ which is asserted then deasserted. Fix sc with HRESP=1 HEXOKAY=1 not clearing the local monitor (not a bug, but unfriendly).
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2021-12-12 23:24:25 +00:00 |
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Luke Wren
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88fea7acfa
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Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
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2021-12-12 18:28:23 +00:00 |
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Luke Wren
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8a003dbbed
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Make mcycle/minstret inhibited by default
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2021-12-12 13:55:33 +00:00 |
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Luke Wren
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2bbc3637a2
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Simplify CSR update logic. Showed promise in block synth but no difference to example soc. Still cleaner RTL.
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2021-12-12 00:38:30 +00:00 |
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Luke Wren
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9460b3cd04
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Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
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2021-12-11 15:52:34 +00:00 |
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Luke Wren
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3d2c912b4f
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Add test script to make it easier to add software testcases
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2021-12-09 22:25:18 +00:00 |
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Luke Wren
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7d2fa6a049
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Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic
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2021-12-09 06:26:31 +00:00 |