7340765699
Add simple test to read, write and lock PMP registers
2022-05-25 02:05:24 +01:00
456810b09e
Make vcd generation optional in runtests
2022-05-24 22:56:13 +01:00
64d9f4a111
Add tests for execution of mret and wfi in U mode
2022-05-24 22:14:20 +01:00
20f06c4a02
Build tb with 4 PMP regions by default
2022-05-24 20:06:57 +01:00
7cfc976ef2
Set U RWX permission on all of memory in the U CSR readability test
2022-05-24 19:58:12 +01:00
cfed35b3da
Fix the stupid printf warning on x86-64 as well as arm64
2022-05-24 18:22:25 +01:00
f033cde874
Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
2022-05-24 17:30:24 +01:00
ba81b533d2
Build core with U mode support for tb
2022-05-24 16:44:22 +01:00
0199f48087
Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
2022-05-24 16:44:03 +01:00
4ba3f7ceb9
Fix format warning in tb.cpp on arm64
2022-05-24 16:17:54 +01:00
ef35dc859d
Add zicsr to march in makefiles
2022-05-24 16:17:54 +01:00
07d4b23a9a
Add option to pass test list to runtests
2022-05-24 16:17:54 +01:00
31061bd472
Add Zbkb to bitmanip tests and regenerate vectors
2022-05-21 17:15:46 +01:00
4ffe007a84
Add zicsr to march in bitmanip tests, so it builds on newer toolchains
2022-05-20 01:32:21 +01:00
4946248dc4
RVFI monitor: blank out instructions which experienced an instruction fetch fault.
...
(previous monitor logic was ok when fetch faults weren't implemented.
If the blanked instruction has side effects, these will break other test
properties, which we would detect.)
2022-04-12 13:38:19 +01:00
8a61fe5243
Fix RVFI monitor assuming rs2 data is equivalent to store data
...
(this used to be true, but was re-plumbed when optimising A extension implementation)
2022-04-12 13:27:53 +01:00
9e27db0884
Connect or tie off missing ports on RVFI wrapper
2022-04-12 13:27:03 +01:00
7dc5046505
Perf option for dedicated branch comparator
2022-04-02 11:40:47 +01:00
3c61fae9ef
Remove the halfword fetch thing, was only really useful on RISCBoy
2022-04-02 10:54:16 +01:00
5aca1381ac
Couple of fixups for rvpy which I forgot to commit at some point
2022-03-01 20:27:18 +00:00
0a369efc06
Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
2021-12-18 15:41:05 +00:00
1b0e205f87
Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami
2021-12-18 14:51:46 +00:00
28b53ef7b5
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
2021-12-18 00:35:13 +00:00
a81d129961
Add exclusives monitor to testbench
2021-12-17 17:03:35 +00:00
5ab60422ad
Add minimal multicore launch code
2021-12-17 01:24:11 +00:00
01d9617f9c
Add multicore tb integration file
2021-12-17 00:41:23 +00:00
207566660d
tb: handle both ports identically. Preparing for dual core
2021-12-17 00:04:00 +00:00
88fea7acfa
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
2021-12-12 18:28:23 +00:00
719c21fec3
Add IRQ tests. Disable waves by default in runtests
2021-12-12 15:53:04 +00:00
9fb2af800f
Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
2021-12-12 14:58:50 +00:00
a232833d81
Add CSR writable test
2021-12-12 14:23:34 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
7da67a0600
Similarly for minstret
2021-12-11 22:25:12 +00:00
1b722b5f27
Add mcycle test, fix incorrect description of mcycle in docs
2021-12-11 21:21:31 +00:00
93eca19aeb
Add test for lr/sc RAW stalls
2021-12-11 19:16:41 +00:00
763a5cd364
Add test for readability of all implemented CSRs
2021-12-11 17:50:12 +00:00
7b1da32af1
Move expected_output into tests inline
2021-12-11 16:58:25 +00:00
9460b3cd04
Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
2021-12-11 15:52:34 +00:00
f64f44f7af
Add test for identification CSRs vs expected values
2021-12-11 13:26:59 +00:00
4066e941ef
Fix sim cmdline in bitmanip-random tests
2021-12-11 13:13:21 +00:00
3fe0d92d41
Add load/store alignment testcases
2021-12-11 12:53:37 +00:00
c90727b05a
Remove padding after vector table in init.S
2021-12-11 12:22:23 +00:00
6076eba61f
Add run_all script under riscv-compliance
2021-12-11 12:08:53 +00:00
52d58fdee4
Add keep wires for debug port on bus compliance tb
2021-12-11 12:06:10 +00:00
6edfbfae8b
Add ebreak size/alignment test
2021-12-11 11:17:24 +00:00
abe1769929
Add instruction access fault testcase
2021-12-11 09:54:00 +00:00
933f2cd65c
Fix remaining fallout from tb args change
2021-12-11 09:53:39 +00:00
6d55cd2d55
Consolidate openocd and bin-load testbenches
2021-12-11 09:46:38 +00:00
fadb9601de
Illegal instruction test
2021-12-10 00:11:18 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
Luke Wren