Luke Wren
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88fea7acfa
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Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
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2021-12-12 18:28:23 +00:00 |
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Luke Wren
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719c21fec3
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Add IRQ tests. Disable waves by default in runtests
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2021-12-12 15:53:04 +00:00 |
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Luke Wren
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9fb2af800f
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Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
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2021-12-12 14:58:50 +00:00 |
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Luke Wren
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a232833d81
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Add CSR writable test
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2021-12-12 14:23:34 +00:00 |
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Luke Wren
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8a003dbbed
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Make mcycle/minstret inhibited by default
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2021-12-12 13:55:33 +00:00 |
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Luke Wren
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7da67a0600
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Similarly for minstret
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2021-12-11 22:25:12 +00:00 |
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Luke Wren
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1b722b5f27
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Add mcycle test, fix incorrect description of mcycle in docs
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2021-12-11 21:21:31 +00:00 |
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Luke Wren
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93eca19aeb
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Add test for lr/sc RAW stalls
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2021-12-11 19:16:41 +00:00 |
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Luke Wren
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763a5cd364
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Add test for readability of all implemented CSRs
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2021-12-11 17:50:12 +00:00 |
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Luke Wren
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7b1da32af1
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Move expected_output into tests inline
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2021-12-11 16:58:25 +00:00 |
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Luke Wren
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9460b3cd04
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Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
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2021-12-11 15:52:34 +00:00 |
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Luke Wren
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f64f44f7af
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Add test for identification CSRs vs expected values
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2021-12-11 13:26:59 +00:00 |
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Luke Wren
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4066e941ef
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Fix sim cmdline in bitmanip-random tests
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2021-12-11 13:13:21 +00:00 |
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Luke Wren
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3fe0d92d41
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Add load/store alignment testcases
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2021-12-11 12:53:37 +00:00 |
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Luke Wren
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c90727b05a
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Remove padding after vector table in init.S
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2021-12-11 12:22:23 +00:00 |
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Luke Wren
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6076eba61f
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Add run_all script under riscv-compliance
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2021-12-11 12:08:53 +00:00 |
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Luke Wren
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6edfbfae8b
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Add ebreak size/alignment test
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2021-12-11 11:17:24 +00:00 |
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Luke Wren
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abe1769929
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Add instruction access fault testcase
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2021-12-11 09:54:00 +00:00 |
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Luke Wren
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933f2cd65c
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Fix remaining fallout from tb args change
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2021-12-11 09:53:39 +00:00 |
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Luke Wren
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6d55cd2d55
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Consolidate openocd and bin-load testbenches
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2021-12-11 09:46:38 +00:00 |
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Luke Wren
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fadb9601de
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Illegal instruction test
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2021-12-10 00:11:18 +00:00 |
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Luke Wren
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3d2c912b4f
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Add test script to make it easier to add software testcases
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2021-12-09 22:25:18 +00:00 |
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Luke Wren
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ac9285846f
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Timer struct in IO header
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2021-12-06 17:16:21 +00:00 |
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Luke Wren
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c57a80f358
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Add AMO + timer testcase
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2021-12-06 07:47:20 +00:00 |
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Luke Wren
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d86b2849c9
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Bump to latest version of riscv-arch-test
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2021-12-06 02:18:48 +00:00 |
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Luke Wren
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df658d86ff
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First plausibly working AMOs. Add AMOs to instruction timings list
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2021-12-04 23:44:22 +00:00 |
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Luke Wren
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5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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c5d6be24f3
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Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
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2021-12-04 14:06:48 +00:00 |
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Luke Wren
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5db6c68c56
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Update riscv-tests for correct misa.x value
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2021-12-04 11:19:43 +00:00 |
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Luke Wren
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52ba930638
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Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
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2021-12-04 01:17:57 +00:00 |
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Luke Wren
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be6b2f3f76
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Fix up DTMs to use byte addressing
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2021-12-02 02:05:23 +00:00 |
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Luke Wren
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1ebccb7cce
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Switch DM to use byte addresses on APB, not word addresses
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2021-12-02 01:47:30 +00:00 |
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Luke Wren
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fad64bb6c9
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Bump embench test submodule
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2021-11-29 18:51:10 +00:00 |
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Luke Wren
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ba248c832a
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init.S: also print out mcause when trapping an unhandled exception
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2021-11-29 18:49:37 +00:00 |
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Luke Wren
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c8afb4ac33
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Add option for fast high-half multiplies
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2021-11-29 18:48:02 +00:00 |
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Luke Wren
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35c5e213c7
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Bump embench for working benchmarks (except md5)
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2021-11-29 00:59:14 +00:00 |
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Luke Wren
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94a3d43f27
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Add Hazard3's registered marchid value to hdl and docs
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2021-11-28 19:53:49 +00:00 |
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Luke Wren
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e7466ae4be
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Move DM data0 CSR into the M-custom space, and document this
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2021-11-28 15:52:52 +00:00 |
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Luke Wren
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47ce2cc8ec
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Add embench submodule, with configs for hazard3
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2021-11-28 00:01:18 +00:00 |
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Luke Wren
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14a4f1a281
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Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
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2021-11-27 17:19:41 +00:00 |
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Luke Wren
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6f1a10724b
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Add bitmanip test vector generation script
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2021-11-26 23:34:06 +00:00 |
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Luke Wren
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1bb7e33b69
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Fix alignment of heap_ptr in init.S. Small ALU cleanup
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2021-11-26 02:59:50 +00:00 |
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Luke Wren
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e352715fdf
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Fix IO decode in openocd/tb.cpp
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2021-11-23 22:12:51 +00:00 |
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Luke Wren
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4d14203586
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Update riscv-tests fork for crash loop debug test
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2021-11-23 21:58:39 +00:00 |
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Luke Wren
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c1f17b0b23
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Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
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2021-11-06 09:59:27 +00:00 |
Richard-Gordon
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375a6d60b7
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Correct mnemonic when logging unsigned sltiu instruction
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2021-10-08 12:02:37 +01:00 |
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Luke Wren
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6fcc74a043
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Add some instructions to Readme
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2021-07-24 11:53:08 +01:00 |
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Luke Wren
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b0d11c0ab7
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Add RISC-V debug tests
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2021-07-22 17:50:04 +01:00 |
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Luke Wren
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c14960ee1b
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Add mtime/mtimecmp to openocd testbench
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2021-07-22 17:31:26 +01:00 |
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Luke Wren
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5d2a562f65
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Just use read_verilog; write_cxxrtl when building tb_cxxrtl
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2021-07-22 17:30:30 +01:00 |