Luke Wren
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8bfc089660
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Slightly more strict holdoff of IRQs on AMO
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2021-12-06 18:13:43 +00:00 |
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Luke Wren
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0b3629564c
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Don't apply shifter assertions to rotates
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2021-12-06 18:12:23 +00:00 |
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Luke Wren
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4c532240f8
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Hold off IRQ when AMO is past the point of no return
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2021-12-06 07:45:13 +00:00 |
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Luke Wren
|
260491405a
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Fix atomic instructions not asserting decode error when A extension is disabled
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2021-12-06 07:28:50 +00:00 |
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Luke Wren
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cc38f46848
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Fix AMO wdata valid left high when entering trap at just the right time
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2021-12-06 07:28:50 +00:00 |
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Luke Wren
|
12c79c0b41
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Fix feature-flag for Zbs instructions in decoder
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2021-12-05 02:05:35 +00:00 |
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Luke Wren
|
9b9120960d
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Fix missing RAW stall on sc.w succes result. Closing laptop again.
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2021-12-05 01:05:01 +00:00 |
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Luke Wren
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df658d86ff
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First plausibly working AMOs. Add AMOs to instruction timings list
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2021-12-04 23:44:22 +00:00 |
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Luke Wren
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5c098866f2
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Sketch in AMO support
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2021-12-04 20:46:39 +00:00 |
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Luke Wren
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34e57f0b14
|
Sketch in an AMO ALU
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2021-12-04 18:52:41 +00:00 |
|
Luke Wren
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a8933c332d
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Fix illegal issue of pipelined exclusives on the bus, and document correct timings
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2021-12-04 18:23:01 +00:00 |
|
Luke Wren
|
5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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607147f280
|
Rewrite byte pick/sign-extend logic, preparing to handle more memops
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2021-12-04 12:08:54 +00:00 |
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Luke Wren
|
a988adfec8
|
Add RISC-V opcodes and memory operation codes for atomics
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2021-12-04 11:16:24 +00:00 |
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Luke Wren
|
52ba930638
|
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
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2021-12-04 01:17:57 +00:00 |
|
Luke Wren
|
dfb07822ee
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Remove UART DTM
|
2021-12-02 02:08:16 +00:00 |
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Luke Wren
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be6b2f3f76
|
Fix up DTMs to use byte addressing
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2021-12-02 02:05:23 +00:00 |
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Luke Wren
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1ebccb7cce
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Switch DM to use byte addresses on APB, not word addresses
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2021-12-02 01:47:30 +00:00 |
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Luke Wren
|
c5e85dea4c
|
Add mconfigptr CSR
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2021-12-01 03:25:56 +00:00 |
|
Luke Wren
|
c8afb4ac33
|
Add option for fast high-half multiplies
|
2021-11-29 18:48:02 +00:00 |
|
Luke Wren
|
94a3d43f27
|
Add Hazard3's registered marchid value to hdl and docs
|
2021-11-28 19:53:49 +00:00 |
|
Luke Wren
|
1aa9dbcddd
|
Fix comment typo in APB clock crossing
|
2021-11-28 17:40:57 +00:00 |
|
Luke Wren
|
e7466ae4be
|
Move DM data0 CSR into the M-custom space, and document this
|
2021-11-28 15:52:52 +00:00 |
|
Luke Wren
|
76172cdade
|
Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
|
2021-11-28 06:33:35 +00:00 |
|
Luke Wren
|
800b21d2f5
|
Remove event feedback path (not logical path) in priority encoder
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2021-11-28 02:19:01 +00:00 |
|
Luke Wren
|
14a4f1a281
|
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
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2021-11-27 17:19:41 +00:00 |
|
Luke Wren
|
5d093487b7
|
Update README
|
2021-11-26 23:33:46 +00:00 |
|
Luke Wren
|
1bb7e33b69
|
Fix alignment of heap_ptr in init.S. Small ALU cleanup
|
2021-11-26 02:59:50 +00:00 |
|
Luke Wren
|
8bcec11c80
|
Couple more silly mistakes
|
2021-11-26 01:30:13 +00:00 |
|
Luke Wren
|
41eeb90c7d
|
Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
|
2021-11-26 01:29:47 +00:00 |
|
Luke Wren
|
998f3fdeb7
|
Clean up silly mistakes
|
2021-11-26 00:55:57 +00:00 |
|
Luke Wren
|
58c20a39d0
|
First pass at implementing bitmanip. Breaks CXXRTL. Ooop
|
2021-11-25 23:30:35 +00:00 |
Luke Wren
|
ed6b6a3660
|
Cleanup order of declaration/use of a couple of wires
|
2021-11-25 15:16:59 +00:00 |
|
Luke Wren
|
49462a8642
|
Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh
|
2021-11-23 22:11:50 +00:00 |
|
Luke Wren
|
e05e9a4109
|
Add default_nettype none at top of every file, and default_nettype wire at bottom
|
2021-11-23 22:10:39 +00:00 |
|
Luke Wren
|
0b9b706e81
|
Safer logic for load/store blocked by preceding WFI
|
2021-11-23 22:01:14 +00:00 |
|
Luke Wren
|
cc6a6c09ba
|
Vaguely implement wfi
|
2021-11-05 18:48:42 +00:00 |
|
Luke Wren
|
cfe16caf41
|
Remove some old todos
|
2021-09-05 22:20:40 +01:00 |
|
Luke Wren
|
e9fccffca0
|
Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
|
2021-09-05 04:45:38 +01:00 |
|
Luke Wren
|
65bfca5fdf
|
Fix latent bug with asynchronous debug entry during stalled load/store address phase
|
2021-09-04 07:49:29 +01:00 |
|
Luke Wren
|
d03a82a826
|
Add instruction fetch faults
|
2021-09-04 02:57:39 +01:00 |
|
Luke Wren
|
e16ae06cb5
|
Clean up timer
|
2021-08-21 17:03:32 +01:00 |
|
Luke Wren
|
9dd091b7b5
|
Doh typo
|
2021-08-21 09:06:20 +01:00 |
|
Luke Wren
|
b99e5b8a67
|
Convert timer to serial for smaller area. Rather untested
|
2021-08-20 22:27:15 +01:00 |
|
Luke Wren
|
4aba165166
|
First pass at a 64-bit system timer
|
2021-08-20 21:49:05 +01:00 |
|
Luke Wren
|
8263ee3a5d
|
Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception
|
2021-07-24 15:31:33 +01:00 |
|
Luke Wren
|
70a44d9681
|
Small code cleanup
|
2021-07-24 10:08:27 +01:00 |
|
Luke Wren
|
155d3ba554
|
Tie off 1 or 2 LSBs of DPC depending on IALIGN
|
2021-07-23 23:09:03 +01:00 |
|
Luke Wren
|
115cb2c50f
|
Tweaks to example soc configuration
|
2021-07-23 23:08:23 +01:00 |
|
Luke Wren
|
279e4b4f29
|
Implement mstatush as hardwired-0, as required by priv-1.12
|
2021-07-23 21:52:01 +01:00 |