d3667769d2
Arrange for address buses to be 0 when processor is held in reset
2022-10-08 16:50:58 +01:00
633a07fef9
Tidy up priority tie-offs in irq_ctrl
2022-10-08 16:25:05 +01:00
5e7bf0d604
Don't reset register file by default
2022-10-08 16:24:28 +01:00
489480dc80
Revise default config values, and update docs with new values
2022-10-08 08:43:25 +01:00
874cb20910
Add config headers to tb_cxxrtl instead of using defparams in Makefile
2022-10-08 08:09:26 +01:00
bf1bca2ca5
Remove FPGA synth netlist checked in by mistake
2022-10-06 16:00:27 +01:00
1036d15467
Clean up duplicate declaration of external_irq_pending in hazard3_irq_ctrl
2022-10-06 15:59:54 +01:00
e6aaf4b801
Avoid IRQ to bus through-path when custom IRQs are disabled
2022-10-06 00:16:10 +01:00
c55d3f0d0b
Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module.
2022-10-05 23:53:04 +01:00
d1d70efa60
Fix some width issues introduced by last commit
2022-10-05 22:19:02 +01:00
6f8b75c041
Make IRQ vectors right-sized. CXXRTL was spending > 1/3rd of its time in the CSR update.
2022-10-05 22:11:53 +01:00
0915cc2834
Doh
2022-09-08 15:11:24 +01:00
9eb8590858
Add generate to avoid elaborating internals of PMP/triggers with 0 PMP regions or triggers.
2022-09-05 00:36:41 +01:00
18c64bd633
Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression
2022-09-04 23:56:14 +01:00
787a7ec372
Fix bad preprocessor conditional in ECP5 JTAG DTM
2022-09-04 23:48:58 +01:00
c594ec42e9
Change style of IRQ register tie-offs as Yosys was not able to trim them for iCE40 synthesis.
2022-09-04 23:43:24 +01:00
624d39669d
Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.
2022-08-29 19:20:09 +01:00
1c2249dbef
Typo
2022-08-29 16:25:12 +01:00
6abd93eb49
Oops, masked the wakeup-on-halt request path when I masked IRQs on WFI state.
2022-08-29 16:15:19 +01:00
099f0467fb
Clean up remnants of the 'wfi_is_nop' thing that seemed like a good idea at the time
2022-08-29 15:56:57 +01:00
954bae5cf1
Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
2022-08-29 14:52:01 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
bf38d93d33
Remove references to AHB-Lite, describe buses as (a subset of) AHB5
2022-08-28 14:15:20 +01:00
9a60f06c43
Fix trigger enable condition
2022-08-23 01:05:46 +01:00
fef6d80fd4
tcontrol.mpte is not supposed to change on trap exit, unlike mstatus.mpie
2022-08-23 00:19:56 +01:00
9e11c0e5a8
Fix tdata1.dmode being writable from M-mode
2022-08-23 00:08:17 +01:00
04f138ae0e
Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant
2022-08-23 00:05:30 +01:00
49c2edeff8
Avoid reserved keyword
2022-08-22 10:26:20 +01:00
53902a901b
Fix bad rdata width for tdata1 (which also caused the trigger type to appear as legacy SiFive, oops)
2022-08-22 09:47:19 +01:00
b90d12efed
CSRs: avoid use of wdata_update in rdata for meicontext, which the SMT2 backend sees as a loop.
...
There is no functional loop here since this is an acyclic path between different bits of the rdata vector, but it makes sense that this would confuse tools that don't bitblast all the vectors.
2022-08-22 09:18:57 +01:00
ba775563d5
Fix suspicious gating of jump request
2022-08-22 09:10:12 +01:00
6e3799eed0
First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.
2022-08-22 08:47:03 +01:00
5d6b5a80b0
Standardise on ifndef YOSYS around default_nettype wire
2022-08-21 13:22:55 +01:00
4c098d76a7
Fix some whitespace issues, and avoid redefinition of RVOPC macros
2022-08-21 13:09:28 +01:00
b994674c5a
Cleanup to avoid negative array index (legal but causes whinging)
2022-08-20 18:13:45 +01:00
3b7cd9bc96
Cleanup some unused signals
2022-08-20 16:44:39 +01:00
96e55a5446
Replace localparams with defines in rv_opcodes.vh, to avoid slightly dubious localparam to casez Z-propagation
2022-08-20 16:22:04 +01:00
d299a3ca4e
More width tweaks
2022-08-20 16:11:58 +01:00
bc274867c0
More width mismatch fixes
2022-08-20 15:27:14 +01:00
dbe9a7824a
Cleanup of some width mismatches in instruction decompress
2022-08-20 14:58:41 +01:00
276830ecb6
Fix missing default assignment of i_m in PMP decode
2022-08-16 09:23:42 +01:00
be05dc32d4
Oops, typo in update of new pmpcfg_m field
2022-08-11 20:46:32 +01:00
5819f8eb7e
Remove wrong/useless mxr logic in PMP
2022-08-08 18:45:37 +01:00
92ebbbe95f
Add pmpcfgm0 register: make regions M-mode without locking them
2022-08-08 18:34:55 +01:00
65e3d1c48b
Fix bad IRQ_IMPL_MASK indexing in meipra write
2022-08-08 18:15:38 +01:00
ef927d0d23
Dumb typo
2022-08-08 10:26:36 +01:00
ad5fd24772
- Fix signal named priority, which is a keyword in SV
...
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
5e72ec8941
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test
2022-08-07 22:04:42 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
cc12b586ca
Fix implicit net in cpu_1port, this yosys bug is a pain in the ass
2022-08-07 20:30:26 +01:00
185194973f
Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
2022-08-06 23:02:08 +01:00
797bff81ab
DM: fix any/allnonexistent going low when hasel is set. The hart array mask is in addition to the hart selected by hartsel.
2022-07-30 19:55:22 +01:00
9787c604ad
Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
2022-07-30 17:31:53 +01:00
0567c2c9fe
Two minor DM bugs:
...
- Writes to dmcontrol.resumereq should be ignored if dmcontrol.haltreq is also set
- aarsize and regno should be ignored when command.transfer is not set
2022-07-30 17:22:46 +01:00
add19506a5
Oops, bad if block nesting in PMP
2022-07-25 13:09:03 +01:00
b7d9defcf2
Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
2022-07-05 03:37:19 +01:00
254350d300
Clean up tie-off of hardwired PMP registers
2022-07-04 14:31:42 +01:00
6e80492723
Typo
2022-07-04 12:09:21 +01:00
cac98568e6
Ignore read data from failed SBA accesses
2022-07-03 20:58:01 +01:00
c7a32c4d00
SBA: fix alignment check using a stale address when the trigger is an sbaddress write. Fix new transfers being allowed to start when sberror or sbbusyerror are set.
2022-07-03 19:02:30 +01:00
ae11d04b10
Add HMASTER output to processor wrappers, to indicate when the bus cycle is driven by SBA rather than the core
2022-07-03 18:02:47 +01:00
b1225c386c
Add missing 1port SBA change, and update example soc and bus compliance tb to reflect
2022-07-03 17:57:03 +01:00
9e15cd3485
Add standalone SBA-to-AHB shim, and make SBA off by default in the DM
2022-07-03 15:30:33 +01:00
d5cd3e0681
Add SBA patch-through to 1-core wrapper.
...
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
2022-07-03 15:17:44 +01:00
d6bef56788
Fix missing byte picking/replication in non-word-aligned SBA transfers
2022-07-03 14:22:12 +01:00
51bc26f8ac
First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
2022-07-03 00:25:47 +01:00
36cee73d1f
Fix acmd FSM not selecting the correct hart signal for its state transitions, and make flush take precedence over debug injection in frontend. (Changes from aborted abstract access memory implementation, see abstract-access-memory branch)
2022-07-02 22:46:20 +01:00
edfe7f601e
Clear local monitor on non-debug trap entry/exit
2022-06-26 21:55:51 +01:00
c2756e79fc
Fix misreading of spec: hartsel hart is selected in addition to those bits set in hart array mask, when hasel is set.
2022-06-26 19:58:01 +01:00
fb15894731
Hopefully fix case where we jump to the address immediately after a
...
halfword-sized word-aligned predicted-taken branch, and an
address-phase hold causes the jump target to go to the fetch address
counter, causing a spurious BTB match on the branch.
2022-06-26 15:28:08 +01:00
33cec49952
Fix bad predbranch tracking on a jump to a predicted-taken non-taken
...
branch which is halfword-sized and halfword-aligned, causing CIR
and PC to diverge.
2022-06-26 15:26:04 +01:00
5455349961
Add menvcfg CSR, and comment explaining why we don't have mseccfg CSR
2022-06-26 01:25:48 +01:00
ad8f883406
First pass at hart array mask register in DM
2022-06-25 20:34:53 +01:00
5193dfe477
Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,
...
and enable it only on the bus compliance model checks. Trying to make
the solver's life easier in instruction_fetch_match.
2022-06-25 20:08:40 +01:00
173f5dba9d
Fix jump target being unstable during a CIR-locked branch-to-self on a partial predicted branch match, due to the addr_is_regoffs decode not being tied off.
2022-06-25 20:07:43 +01:00
8ef9d77be8
Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations.
...
Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)
2022-06-25 13:11:40 +01:00
31efd07042
Fix incorrect tracking of predictedness of fetch data phase. Fixes performance regression in RV32IMC CoreMark (now runs faster, as it should.)
2022-06-25 11:32:56 +01:00
979e80be99
Attempt to fix fetch mismatch caused by jumping halfway into a 32-bit
...
instruction that precedes a taken branch.
The bookkeeping in the frontend has been tightened up so that the entire
branch instruction, and nothing but the branch instruction, is marked as a
taken branch. This required some extra state, e.g. remembering the size of
the taken branch instruction, but saved an incrementer on the BTB source
address value.
2022-06-24 19:58:21 +01:00
d9389fb23e
Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
2022-06-16 01:42:28 +01:00
f8aad6d2f3
Fix some bugs, too tired to list them, look at the diff
2022-06-15 04:05:31 +01:00
0766ec6f8a
First pass at adding branch prediction
2022-06-15 02:05:46 +01:00
3703b1fc4c
Allow use of cir_flush_behind in frontend_match formal tb
2022-06-13 20:36:15 +01:00
e68d8a6cd6
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
2022-06-13 01:23:32 +01:00
26d54d0023
Re-rewrite frontend to track the halfword-validity of in-flight transfers, and clean up the old cir_lock mechanism to be a modified flush
2022-06-12 21:01:39 +01:00
e3da922f8b
Revert previous frontend changes. Seemed promising but is a dead end for area.
...
The original frontend design can probably be tweaked to support predictions.
2022-06-12 16:25:42 +01:00
940b7e4009
Actually still need 7 halfwords for full throughput in the case of sequential word-sized halfword-aligned instructions
2022-06-12 16:21:56 +01:00
8458dff083
Fix bus errors not being applied in frontend
2022-06-12 05:28:21 +01:00
23b4dbe7f3
Redesign fetch queue: 2x32 + 3x16 -> 6x16.
...
Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
2022-06-12 02:44:08 +01:00
d5a202e4a5
Add standalone frontend formal tb
2022-06-11 20:14:24 +01:00
3b5879da66
Small code cleanup in frontend. The address phase alignment state no longer needs to be tracked, since we just generate word accesses always, for simplicity.
2022-06-11 14:27:59 +01:00
de9b51b787
Remove default zeroing of fetch address when no fetch is asserted -- this puts LUTs on a critical path and arguably causes more toggling than asserting the sequentially next address by default.
2022-06-11 14:26:40 +01:00
11596a5bd7
Remove unused/untested RISC-V timer implementation
2022-06-09 00:12:26 +01:00
ea2b8888a4
Update copyright years
2022-06-09 00:12:01 +01:00
ae2784d0ea
PMP config: separate granularity config from hardwired region config. Give correct read value for G > 1.
2022-06-03 17:09:43 +01:00
e0a9fb7312
Add option to hardwire PMP regions, or reduce their granularity
2022-06-03 01:19:03 +01:00
66965ac073
Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
2022-05-28 15:36:21 +01:00
81aec325bb
ecall from U-mode has a different mcause value than ecall from M-mode
2022-05-28 12:07:29 +01:00
f2876eb51f
Fix bad mepc reported after branching to a branch in a no-X address range
2022-05-27 22:47:04 +01:00
0e462574b2
Move declaration of x_exec_pmp_fail to before its first use
2022-05-27 15:04:43 +01:00
156fbcd019
Update behaviour of mstatus.mpp and mprv on mret to match priv-1.12 spec
2022-05-26 00:42:50 +01:00
Luke Wren
Luke Wren