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59 Commits

Author SHA1 Message Date
Luke Wren d9300ee127 Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry 2021-07-17 19:26:45 +01:00
Luke Wren 8014239d47 openocd tb: report AHB error response when processor accesses outside of RAM/IO 2021-07-17 19:26:05 +01:00
Luke Wren 5deff12f95 DM: don't report as running/halted in dmstatus if unavailable. 2021-07-17 16:46:39 +01:00
Luke Wren ab0b4a04f0 Also support progbuf in abstractauto. 2021-07-17 15:08:00 +01:00
Luke Wren 46f95f859d Some doc updates 2021-07-17 13:07:09 +01:00
Luke Wren 14ba030271 Example soc tweaks, add openocd config 2021-07-16 20:44:25 +01:00
Luke Wren 8e3dc62b97 Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions 2021-07-16 20:43:24 +01:00
Luke Wren 5aca6be572 Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR. 2021-07-16 18:28:30 +01:00
Luke Wren ce5152a4f4 Implement HALTSUM0 and HALTSUM1 registers 2021-07-16 17:58:28 +01:00
Luke Wren 62822b2e1d Couple of usability improvements for openocd testbench 2021-07-15 19:42:49 +01:00
Luke Wren 011008efd1 Fix detection of exception-like vs IRQ-like halt/trap entries 2021-07-15 19:41:35 +01:00
Luke Wren 71ec9fa283 Fix exception entry not counting as a step point for dcsr.step, and mask off IRQs in step mode (we tie dcsr.stepie = 0) 2021-07-14 20:39:51 +01:00
Luke Wren 9643a57ba9 Slightly less braindead TCP interactions for openocd JTAG bitbang testbench, much more interactive now 2021-07-14 19:20:27 +01:00
Luke Wren f4952ab66d Add simple example SoC, hangs nextpnr for some reason! 2021-07-13 03:40:06 +01:00
Luke Wren 307955c810 Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference 2021-07-13 01:10:55 +01:00
Luke Wren 93c7039ea1 Sync doc updates 2021-07-12 22:13:31 +01:00
Luke Wren 4b650ac437 DM: add missing w1c to abstract cmderr, add capture of last abstract command for use with abstractauto 2021-07-12 21:26:00 +01:00
Luke Wren 42632e325a Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core 2021-07-12 21:21:16 +01:00
Luke Wren 27674be996 Start hacking in a JTAG-DTM 2021-07-12 01:49:32 +01:00
Luke Wren f7b3097ad6 Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works 2021-07-11 16:20:39 +01:00
Luke Wren 0dce59daaf Start hacking together a DM 2021-07-11 05:11:19 +01:00
Luke Wren 5cc483898d Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode 2021-07-10 21:02:18 +01:00
Luke Wren 47fa7f4d10 Associated doc updates 2021-07-10 18:53:59 +01:00
Luke Wren 63d661af63 Start hacking in debug support to the core -- seems to work as well as before adding debug! 2021-07-10 18:53:48 +01:00
Luke Wren 83244c6651 Add Read ID command to UART DTM 2021-07-10 16:14:35 +01:00
Luke Wren 3312ea7022 Add draft UART DTM 2021-07-08 17:57:46 +01:00
Luke Wren 6a38fc33a6 Allow MHARTID to be configured at instantiation 2021-07-07 16:08:08 +01:00
Luke Wren 58a6b8b4c8 Add 32IM testlist 2021-06-05 12:03:05 +01:00
Luke Wren be79a611e1 Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why. 2021-06-04 09:19:18 +01:00
Luke Wren c03bc2efb5 Update init.S for new IRQ functionality 2021-06-04 08:16:54 +01:00
Luke Wren 278dc8b6a2 meie0 default to all-zeroes 2021-06-04 07:37:02 +01:00
Luke Wren af684c4e82 Some cleanup; correctly decode 16-bit EBREAK 2021-06-03 20:03:43 +01:00
Luke Wren 5f8d217395 Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0 2021-05-31 17:54:12 +01:00
Luke Wren 4053458485 Document some IRQ CSRs, and instruction timings 2021-05-31 15:57:05 +01:00
Luke Wren 12851d3742 Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set 2021-05-30 19:52:46 +01:00
Luke Wren cec5dc4e3b Remove old MCYCLE/MCYCLEH, implement MCOUNTINHIBIT fully, always decode tied-off HPM counters 2021-05-30 19:20:53 +01:00
Luke Wren 565b76672a Make MVENDORID/MARCHID/MIMPID configurable 2021-05-30 18:42:43 +01:00
Luke Wren 12205f12c7 Add instruction fetch match check 2021-05-30 11:22:36 +01:00
Luke Wren 16dc905dce Add simple formal bus properties check 2021-05-30 10:19:42 +01:00
Luke Wren 2330b84b73 Use .f for riscv-formal tb dependencies, small reshuffling of directories 2021-05-30 09:44:57 +01:00
Luke Wren 089bcc7c43 Typo 2021-05-29 23:24:18 +01:00
Luke Wren ad8f251ba2 RVFI wrapper: use proper bus assumptions. RVFI monitor: don't mark instruction which is aligned with IRQ as invalid, because the IRQ entry is notionally behind it 2021-05-29 23:24:02 +01:00
Luke Wren ea5db61582 Fix exception being passed to M when X is stalled but M is not (a load which had an unaligned address spuriously during a RAW stall on the result register) 2021-05-29 22:52:50 +01:00
Luke Wren 4b9a3c2c78 Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F) 2021-05-29 19:32:12 +01:00
Luke Wren f23ec3f941 Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere 2021-05-29 18:57:43 +01:00
Luke Wren 65075df0e5 More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus 2021-05-29 18:00:43 +01:00
Luke Wren 1b252d4bda Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2 2021-05-23 11:59:46 +01:00
Luke Wren 5e61c9f9ac Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc 2021-05-23 09:12:50 +01:00
Luke Wren 90acfdcbe8 Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
Luke Wren 7a3ce494e4 Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth) 2021-05-23 06:40:44 +01:00