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  • 1f1ed068a0 Update 325T master Colin 2024-11-08 01:27:22 +0800
  • cca9d908ef Add program hex support in uriscv. colin.liang 2023-01-07 16:15:54 +0800
  • c2e4068c8a Add uriscv/tb. colin.liang 2023-01-07 16:14:56 +0800
  • 5fb3787307 reset from top.v. colin.liang 2023-01-06 21:19:54 +0800
  • 31c90f22f6 Refine top.v. colin.liang 2023-01-05 21:37:01 +0800
  • c57450fa1c Add ivlpp to gen single file of RTL. colin.liang 2023-01-05 21:28:53 +0800
  • 44161e293f Reset Readme. colin.liang 2023-01-04 22:40:08 +0800
  • 270f695fbf Update Readme colin.liang 2022-11-03 17:00:26 +0800
  • 32fff97ff5 Update gnu build. colin 2022-07-07 12:06:04 +0000
  • e23aca0cfc Delete rvdff by fpga. colin 2022-05-23 15:37:09 +0000
  • a8c8d46382 Remove ahb connect axi4. colin 2022-05-23 14:51:42 +0000
  • 902f44a21c Default use axi4 without ahb_lite. colin 2022-05-23 14:45:23 +0000
  • 6bf845bb46 Format sv and v code. colin 2022-05-23 14:16:04 +0000
  • 2f8715aeb6 Delete unuse file and configs. colin 2022-05-23 13:53:58 +0000
  • a9bfa80cc1 Test jtag demo will incorrect when add instruction in loop3. colin 2022-05-11 03:31:51 +0000
  • 29696841ff Refine flow asm code. colin 2022-05-10 13:44:14 +0000
  • fd64d8618a Copy Cores-SweRV-EL2 to flow. colin 2022-05-10 13:06:26 +0000
  • 11312aee91 Refine uriscv to verilator. colin 2022-05-10 12:50:30 +0000
  • ded2df85f8 Refine Readme of uriscv. colin 2022-05-10 04:20:23 +0000
  • 1dfaaa39ef Add uriscv, a smallest riscv implementation. colin 2022-05-10 04:19:18 +0000
  • 15467611cf Update Readme. colin 2022-03-27 09:56:02 +0000
  • 937a29de67 Update Cores-EL2 and Quasar. colin 2022-03-27 09:55:41 +0000
  • bd392cfb7c Refine reset vector in Cores-SweRV. colin 2022-03-22 23:25:11 +0000
  • 5b6bdcc8b0 Update .gitignore. colin 2022-03-22 23:24:30 +0000
  • 388db4a82e Delete quasar in Cores-SweRV. colin 2022-03-22 23:24:01 +0000
  • 386e1f1a54 Add Miner420T submodule colin 2022-03-22 23:14:02 +0000
  • be80eb1063 Update Quasar. colin 2022-03-20 09:06:23 +0000
  • 49c8aab2fd Update Readme. colin 2022-03-20 09:06:02 +0000
  • 03549f1f93 Update Quasar colin 2022-03-18 10:06:26 +0000
  • b2c15ca508 Update xilinx Readme. colin 2022-03-11 05:08:19 +0000
  • b9d70b7a1c Update Quasar colin 2022-03-10 13:15:49 +0000
  • d806515276 Add submodule of quasar. colin 2022-03-10 08:58:15 +0000
  • 2be1901f7b update EL2 colin 2022-03-09 14:46:24 +0000
  • e513374a7e Add submodule of sweRV EL2. colin 2022-03-09 11:17:07 +0000
  • beab126fc5 add quasar fpga. colin 2022-03-09 11:16:13 +0000
  • 33885bbccb Add Bit-Vector install in readme colin 2022-03-07 04:08:12 +0000
  • 27fade0b6d Add EL2 cores implement by Chisel in quaser. colin 2022-03-06 04:22:17 +0000
  • 0a00e20cfe Update riscv gcc version and usage. colin 2022-03-06 04:21:41 +0000
  • 3da81c5916 Add install commond in riscv gnu tools. colin 2022-03-01 13:22:23 +0000
  • e26d5260de start to add ecp5 support,current donet support jlink colin 2022-02-28 03:34:59 +0000
  • 2c4658ddb9 Refine murax sim config file colin 2022-02-28 03:33:41 +0000
  • 28d08fc3ad Refine Readme of install openocd. colin 2022-02-28 03:33:08 +0000
  • e0f77ceead Add configuration to flash by ecpdap. colin 2022-02-27 15:39:45 +0000
  • 94c99367ba remove gen file in fpga colin 2022-02-27 04:49:27 +0000
  • 1d1237c223 Add VexRiscv fpga generation to ecp5. colin 2022-02-26 15:14:43 +0000
  • 25a557365b Enable VexRiscv murax jtag simulator by verilator. colin 2022-02-26 14:34:25 +0000
  • e3968e6fa7 Refine opene906 gdb sample. colin 2022-02-25 12:24:03 +0000
  • 65545d5e03 Add VexRiscv. colin 2022-02-25 11:56:36 +0000
  • ccc993e003 Refine gdb sample code colin 2022-02-24 06:04:58 +0000
  • 3258c057e3 Enable demo openocd and gdb. colin 2022-02-24 03:18:07 +0000
  • 1d7ba86749 Add dome on opene906 colin 2022-02-22 06:44:45 +0000
  • 0d940ba004 Add opene906 colin 2022-02-21 10:41:54 +0000
  • 51730ed20d Add xilinx readme. colin 2022-02-20 14:49:47 +0000
  • 3972a891ca Add fpga demo in Cores. colin 2022-02-20 04:11:18 +0000
  • 3edc87e0ea Switch mem bus from ahb to axi. colin 2022-02-17 11:35:01 +0000
  • cffec82632 Add clean before fpga ram make all colin 2022-02-17 06:20:57 +0000
  • 8e190efed0 Split from soc.mk to soc_sim.mk and soc_top.mk colin 2022-02-15 08:27:53 +0000
  • 1f222dd1e3 Split soc and verilator to two part system verilog. colin 2022-02-14 12:32:21 +0000
  • a6038fde4a Set DCCM and ICCM size to 32KB colin 2022-02-11 12:17:21 +0000
  • 547f0dbdc3 remove axi4 in demo soc use ahb as default colin 2022-02-10 12:17:10 +0000
  • 18c8352c09 Add ram test and verilator in fpga DEMO. colin 2022-02-09 12:47:35 +0000
  • 3c3cfccfd5 add ram test. colin 2022-02-08 03:00:40 +0000
  • a7ef641f0d Refine io level colin 2022-02-07 13:34:50 +0000
  • 3405c88c9e Correct blink and use sample blink code colin 2022-02-07 13:23:34 +0000
  • 3370d01917 Add verilator install method in readme. colin 2022-02-07 08:13:16 +0000
  • 3ba8533996 Add fpga colin 2022-02-02 03:43:53 +0000
  • a15c797e93 add jtag to ESP32 colin 2022-02-02 03:39:59 +0000
  • 853d12f17c Init to abstract accelerator project colin 2022-02-02 03:34:37 +0000
  • f299211d91 Refine readme for rocket tool build colin 2022-02-01 15:50:30 +0000
  • d8c2a6861b refine Readme for demo Colin 2022-01-27 16:42:31 +0800
  • 3ed8011eaa add jtag demo for GDB which openocd Colin 2022-01-22 08:08:47 +0000
  • 5f80832b1a add jtag demo and refine Makefile Colin 2022-01-20 03:44:59 +0000
  • a8fc3642ad Add dpi of jtag Colin 2022-01-19 12:32:39 +0000
  • 65f5085afa refine makefile Colin 2022-01-19 09:57:37 +0000
  • 9174bfe249 mv flist to soc folder Colin 2022-01-17 12:18:33 +0000
  • 1437f0fcf3 move swerv config and json to soc Colin 2022-01-17 12:14:05 +0000
  • 7aff1ae5f1 add soc for common test with soc. Colin 2022-01-17 11:53:50 +0000
  • 3be1146718 refine define file build Colin 2022-01-17 11:40:11 +0000
  • 1d8069026b remove no use file in demo Colin 2022-01-17 11:10:22 +0000
  • 2b298f0fff rename test to demo Colin 2022-01-17 06:43:14 +0000
  • 0eb74fdc10 refine test use function Colin 2022-01-05 03:47:27 +0000
  • 6567357739 add llvm build flow from .c file Colin 2022-01-04 12:39:14 +0000
  • be63e84a1d Add build from llvm Colin 2021-12-17 13:29:59 +0000
  • 911f65874f add test of verilator in one folder Colin 2021-12-16 12:07:50 +0000
  • 87c23b9952
         Merge pull request #101 from antmicro/fix-vivado-tcl Ajay Nath 2021-10-08 17:45:03 -0400
  • f57cce19ff Remove not existing file from vivado.tcl Kamil Rakoczy 2021-08-27 15:27:02 +0200
  • 81bff1c0d7 reverting to 0242c9e for swerv_config_gen.py Ajay Nath 2021-03-12 08:02:57 -0500
  • d4e7b25f71
         Merge pull request #93 from antmicro/variable-order-fix Ajay Nath 2021-02-19 15:03:43 -0500
  • 74a6bdb50d Do not use variables before declaration Tomasz Gorochowik 2021-02-17 10:58:22 +0100
  • f3da044f15
         Delete testbench/tests/cmark_dccm directory Ajay Nath 2021-02-16 08:56:23 -0500
  • 5e23462bd0
         Update README.md Thomas Wicki 2021-02-03 13:26:41 -0800
  • 695883a674 Removed dead code. Joseph Rahmeh 2021-02-03 11:08:48 -0800
  • 0c92ea167b Version 1.9 Joseph Rahmeh 2021-02-03 07:07:10 -0800
  • ec254f5491 Version 1.9. Joseph Rahmeh 2021-01-27 09:36:43 -0800
  • bcb5b33726
         Merge pull request #82 from chipsalliance/quartus_core_fix Ajay Nath 2021-01-21 17:59:41 -0500
  • bb9f9ef37b
         Merge pull request #89 from olofk/scan_mode Ajay Nath 2021-01-21 17:58:36 -0500
  • bcf505751e Remove unused scan_mode input from dmi_wrapper Olof Kindgren 2021-01-15 17:14:47 +0100
  • 3918a8d345
         Only load Vivado TCL files when using Vivado Olof Kindgren 2020-11-24 09:31:52 +0100
  • 7332edc0ad
         Merge pull request #76 from olofk/snapshot_dir2 Ajay Nath 2020-09-24 10:26:32 -0400
  • 0242c9e6d2 Explicitly use python3 Olof Kindgren 2020-09-24 15:24:30 +0200