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403 Commits

Author SHA1 Message Date
Clifford Wolf cd72560937 Update rvfi_order according to current rvfi spec 2017-09-05 01:10:04 +02:00
Clifford Wolf 99f0cafd19 Add simple UART to PicoSoC 2017-08-11 19:30:53 +02:00
Clifford Wolf febb4b1318 Improve and cleanup picosoc firmware 2017-08-11 16:15:07 +02:00
Clifford Wolf 78f2f5efd2 Add support for QSPI DDR mode, Add SPI MEMIO config reg 2017-08-11 15:57:42 +02:00
Clifford Wolf 53b175d0fb Add spimemio QSPI support 2017-08-11 15:02:31 +02:00
Clifford Wolf 89ad9fc85a Fix bug in picosoc spimemio and some cleanups in hx8kdemo 2017-08-08 12:07:17 +02:00
Clifford Wolf 8821696748 Major rewrite of picosoc spimemio core 2017-08-07 22:36:58 +02:00
Clifford Wolf ff7855900d Refactor picosoc flash_io interfaces 2017-08-07 16:27:57 +02:00
Clifford Wolf db2222ec02 Refactor picosoc code 2017-08-07 15:13:27 +02:00
Clifford Wolf caef4e3753 Rename "spiflash" example to "picosoc" 2017-08-07 13:38:07 +02:00
Clifford Wolf 571f5d5df7 Add spiflash testbench and add support for QSPI and DDR QSPI to SPI flash sim model 2017-08-05 17:08:16 +02:00
Clifford Wolf 82a51bc8a4 Change spiflash pin interfaces to support quad SPI 2017-08-04 21:05:05 +02:00
Clifford Wolf cb87f93cf8 Improve spiflash testbench and firmware 2017-07-29 21:34:29 +02:00
Clifford Wolf 995f366d0e Add prefetching to spimemio 2017-07-29 21:34:11 +02:00
Clifford Wolf fdb2e5feb5 Update spiflash README 2017-07-29 16:09:29 +02:00
Clifford Wolf 098829e579 Add spiflash example project 2017-07-29 16:01:39 +02:00
Clifford Wolf 4ce36a87d1 Update README 2017-07-29 10:26:23 +02:00
Clifford Wolf 98ee8098b9 Add testbench_ez 2017-07-27 21:36:38 +02:00
Clifford Wolf 9dbc96e330 Update vivado evaluations 2017-07-20 09:56:30 +02:00
Clifford Wolf f99cd747da Suppress writes to cpuregs[0] to prevent confusion 2017-07-14 11:20:55 +02:00
Clifford Wolf 2bc93eb8d0 Fix scripts/torture gcc calls 2017-07-10 11:52:10 +02:00
Larry Doolittle c9de8001fe Remove some trailing whitespace 2017-06-13 13:22:25 +02:00
Clifford Wolf 45b80f985a Add rvfi_halt and rvfi_intr ports 2017-06-06 20:27:45 +02:00
Clifford Wolf f295b900bc Add RVFI to AXI and WB wrappers modules, Add RVFI monitor support to test bench 2017-05-27 19:58:44 +02:00
Clifford Wolf bb9ebeb9e3 Fixed jalr, c_jalr, and c_jr insns (bug discovered by riscv-formal) 2017-05-18 17:19:08 +02:00
Clifford Wolf 436544ccab Fix decoding of C.ADDI instruction 
See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/mr3H6S6IIts
for discussion. There was a bug in the ISA manual.
 2017-05-13 12:28:54 +02:00
Clifford Wolf cd30db3425 Add riscv-formal alu/regs blackboxing 2017-05-11 00:13:01 +02:00
Clifford Wolf bf9687028d Fix decoding of illegal/reserved opcodes as other valid opcodes 2017-05-07 21:13:46 +02:00
Clifford Wolf a13512c86a Update riscv-gnu-toolchain to git rev 4e51f26 2017-05-05 11:32:22 +02:00
Clifford Wolf 3675375072 Update riscv-gnu-toolchain to git rev 0c8f87d 2017-04-07 11:43:05 +02:00
Clifford Wolf 1b22a099f9 Merge pull request #40 from open-design/20170406.wishbone 
testbench_wb.v: unify verbose output with axi testbench
 2017-04-07 10:05:13 +02:00
Antony Pavlov 7c852571f0 testbench_wb.v: unify verbose output with axi testbench 
Unification of testbench output makes it possible to use the diff
utility for comparing testbench instruction traces.

Alas the testbench and testbench_wb traces are differ
because of interrupts, e.g.

    picorv32$ make testbench_wb.vvp
    iverilog -o testbench_wb.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench_wb.v picorv32.v
    chmod -x testbench_wb.vvp
    picorv32$ make testbench.vvp
    iverilog -o testbench.vvp -DCOMPRESSED_ISA -DRISCV_FORMAL testbench.v picorv32.v
    chmod -x testbench.vvp
    picorv32$ vvp -N testbench_wb.vvp +verbose | head -n 856 > /tmp/testbench_wb.log
    picorv32$ vvp -N testbench.vvp +verbose | head -n 856 > /tmp/testbench.log
    picorv32$ diff -u /tmp/testbench.log /tmp/testbench_wb.log
    --- /tmp/testbench.log  2017-04-06 06:56:06.079804549 +0300
    +++ /tmp/testbench_wb.log       2017-04-06 06:55:58.763485130 +0300
    @@ -850,7 +850,7 @@
     RD: ADDR=000056a0 DATA=00000013 INSN
     RD: ADDR=000056a4 DATA=fff00113 INSN
     RD: ADDR=000056a8 DATA=00000013 INSN
    -RD: ADDR=000056ac DATA=14208463 INSN  <--- testbench: no interrupt
    -RD: ADDR=000056b0 DATA=00120213 INSN
    -RD: ADDR=000056b4 DATA=00200293 INSN
    -RD: ADDR=000056b8 DATA=fe5212e3 INSN
    +RD: ADDR=00000010 DATA=0200a10b INSN  <--- testbench_wb: interrupt
    +RD: ADDR=00000014 DATA=0201218b INSN
    +RD: ADDR=00000018 DATA=000000b7 INSN
    +RD: ADDR=0000001c DATA=16008093 INSN

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-04-06 06:56:39 +03:00
Clifford Wolf 2c6cbcf72f Merge pull request #39 from open-design/20170324.wishbone 
testbench_wb.v: drop unused stuff
 2017-03-24 11:50:50 +01:00
Antony Pavlov dded496cfb testbench_wb.v: drop unused stuff 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-17 07:00:33 +03:00
Clifford Wolf 5d2ff0129a Add GIT_ENV Makefile variable (for things like http proxy settings) 2017-03-15 16:35:02 +01:00
Clifford Wolf 22ee418a74 Merge pull request #37 from open-design/20170315.testbenches 
20170315.testbenches
 2017-03-15 11:30:19 +01:00
Antony Pavlov 8e55b93541 Makefile: use automatic variables in testbench rules 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-15 07:15:31 +03:00
Antony Pavlov 1fbe25c994 testbench.v: fix whitespaces 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-15 07:15:31 +03:00
Antony Pavlov 0967a39c1d testbench_wb.v: fix output stuff 
This patch fixes wishbone testbench output issue:
'DNNE' instead of 'DONE', i.e.

    Cycle counter ......... 546536
    Instruction counter .... 69770
    CPI: 7.83
    DNNE

    ------------------------------------------------------------
    EBREAK instruction at 0x000006C4

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-15 07:10:37 +03:00
Clifford Wolf 726a76c1cc Merge branch 'wishbone' 2017-03-14 11:51:27 +01:00
Clifford Wolf 3495604877 Fix indenting in wishbone code 2017-03-14 11:51:09 +01:00
Antony Pavlov a25597532d WIP: add WISHBONE testbench 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-14 09:37:05 +03:00
Antony Pavlov e59fa1dfb2 WIP: add WISHBONE interconnect support 
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
 2017-03-14 09:37:04 +03:00
Clifford Wolf ce862f09f5 Rename "testbench_vcd" make target to "test_vcd", remove "view" 2017-03-12 10:59:22 +01:00
Clifford Wolf f33ddd3654 Fix in rvfi_mem_ handling (when compressed isa is enabled) 2017-02-27 14:21:42 +01:00
Clifford Wolf aaa9e25756 Add DEBUGNETS debug flag 2017-02-26 16:56:13 +01:00
Clifford Wolf 75830805b8 Rename "make testbench.vcd" to "make testbench_vcd" so VCD file is not removed on Ctrl-C 2017-02-21 11:17:43 +01:00
Clifford Wolf c7cc32ed95 Fix verilog code for modelsim 2017-02-17 15:23:58 +01:00
Clifford Wolf e4312b0fab Fix "mem_xfer is used before its declaration" warning 2017-02-11 12:52:18 +01:00
Clifford Wolf 42b4397390 Add scripts/presyn/ example 2017-02-09 15:15:46 +01:00