1d0fc21430
Readme.md / doc: clarify "naturally aligned regions", no TOR support
...
While NA4 and NAPOT are the only "naturally aligned" addressing modes
in the RISC-V PMP (Privileged) Spec, calling their support out by
name, and clearly stating that the TOR addressing mode is not
supported, can clarify this fact for software / OS developers.
This is a common point of confusion and frustration when porting to
new RISC-V chips and so increased visbility of this limitation in the
documentation and README might help.
2024-08-08 20:44:43 -07:00
aa140fb244
Do a quick pass over all the documentation.
...
Fill out port definitions for the AHB5 interfaces.
Snip the appendix of instruction pseudocode as it's strictly redundant
vs the specs. No need to pad this document.
Rearrange the implementation section to put ports before parameters, and
add some brief notes on synthesis.
2024-08-07 13:10:27 -07:00
fe4781627f
Add port definitions to documentation
2024-08-07 08:16:51 -07:00
4a1d2b5008
Save a cycle on popret/popretz by executing the stack adjust after the jump
2023-03-23 02:50:34 +00:00
b074d370a6
Add Zcb/Zcmp instruction timings to docs
2023-03-23 01:12:38 +00:00
56586def8d
List Zcb/Zcmp in docs, and rebuild PDF
2023-03-22 03:04:16 +00:00
78d937e5c8
Yeet Zcb into core
2023-03-16 18:48:15 +00:00
f329d30713
Typo in docs introduction
2022-10-08 15:10:45 +01:00
489480dc80
Revise default config values, and update docs with new values
2022-10-08 08:43:25 +01:00
4b94c9a2d4
Document new configuration for IRQ and PMPM extensions
2022-10-06 00:19:13 +01:00
b352d3878d
Update docs for new power control extension
2022-08-28 19:54:55 +01:00
ce93c45e69
Add docs section for custom extensions
2022-08-28 15:50:26 +01:00
7d18a21734
Editing
2022-08-27 20:49:55 +01:00
d56e217a40
Work on docs. Document config options, expand the intro, move instruction timings and pseudocode to appendices.
2022-08-27 20:13:21 +01:00
9e11c0e5a8
Fix tdata1.dmode being writable from M-mode
2022-08-23 00:08:17 +01:00
f47f603595
Doc typos
2022-08-09 00:05:51 +01:00
cd69fcdbbc
Docs: Add date to title page, and rebuild PDF with recent CSR changes
2022-08-08 23:57:20 +01:00
259a402e28
Describe new pmpcfgm0 register
2022-08-08 23:15:28 +01:00
457b5e5f1a
Fix some doc sections which assumed only M-mode was supported
2022-08-08 17:35:39 +01:00
026b529bc5
Fix asm example in docs to set meicontext.clearts when saving
2022-08-07 23:17:39 +01:00
69917ccbbe
Docs: Tweak meicontext with thoughts that came up whilst implementing it
2022-08-07 20:31:14 +01:00
054c4a6a9c
Fix reversed pseudocode for ctz/clz
2022-08-02 21:21:44 +01:00
adf81abfdc
Oops, description of shxadd had operands swapped
2022-07-31 17:45:14 +01:00
e76b82e447
More thoughts about interrupts, starting to look plausible
2022-07-31 16:16:16 +01:00
106c4c3d28
Update docs CSR section to reflect addition of U-mode, PMP etc.
2022-07-30 21:19:30 +01:00
c73c09a48a
More thinking about interrupt priorities
2022-07-30 15:42:26 +01:00
7946432d7a
Speculatively update docs with new interrupt array/priority stuff, and sleep register
2022-07-28 01:18:13 +01:00
ae30d7c0d2
Add instruction pseudocode (no A extension)
2022-07-10 19:16:43 +01:00
956b386a20
Update instruction listings in docs
2022-07-10 05:47:19 +01:00
e68d8a6cd6
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
2022-06-13 01:23:32 +01:00
1697192c62
Fix cycle timing docs for sc.w: 2 cycles if next instruction is RAW-dependent.
2021-12-12 20:50:26 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
7da67a0600
Similarly for minstret
2021-12-11 22:25:12 +00:00
1b722b5f27
Add mcycle test, fix incorrect description of mcycle in docs
2021-12-11 21:21:31 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
6ef3503ef5
Add A bit to MISA, update docs
2021-12-07 05:10:20 +00:00
9e7ea4adb6
Fix column width
2021-12-06 17:14:23 +00:00
df658d86ff
First plausibly working AMOs. Add AMOs to instruction timings list
2021-12-04 23:44:22 +00:00
a8933c332d
Fix illegal issue of pipelined exclusives on the bus, and document correct timings
2021-12-04 18:23:01 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
52ba930638
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
2021-12-04 01:17:57 +00:00
cd1b391714
More docs cleanup
2021-12-02 02:29:34 +00:00
ebe87dce46
Reorganise CSR section of docs
2021-12-02 01:35:18 +00:00
c5e85dea4c
Add mconfigptr CSR
2021-12-01 03:25:56 +00:00
94a3d43f27
Add Hazard3's registered marchid value to hdl and docs
2021-11-28 19:53:49 +00:00
0fafae1ab1
Regenerate PDF
2021-11-28 16:27:54 +00:00
e7466ae4be
Move DM data0 CSR into the M-custom space, and document this
2021-11-28 15:52:52 +00:00
9bf4d5105f
Describe possible debug topologies. Update pdf.
2021-11-28 09:01:23 +00:00
4e2686d4ab
Finish documenting CSRs. Draw a debug topology diagram.
2021-11-28 08:17:23 +00:00
76172cdade
Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
2021-11-28 06:33:35 +00:00
Leon Schuermann
Luke Wren