194c9a9052
Implement WFI in rvcpp. The umode_wfi test still does not pass, because it relies on a bug in Hazard3 (mstatus.mie disables IRQs in U-mode as well as M-mode, but is supposed to be ignored in U-mode).
2024-04-27 20:48:30 +01:00
78260e86e7
rvcpp: parameterise number of PMP regions, and set to match tb default. Fix region locking. Mask pmpaddr to 30 bits, to match Hazard3 32-bit physical address space.
2024-04-27 19:57:18 +01:00
ebe5a44454
rvcpp: fix up PMP address mask for all-ones pmpaddr, and raise instruction fault on instruction stradding two PMP regions, like the hardware
2024-04-27 19:34:17 +01:00
7d370292b0
Fix transposition of RWX <-> XWR in PMP implementation.
...
None of upstream tests used for Hazard3 seem to cover X != R. The
Hazard3 tests covered this case, but the header file for the tests has
the same mistake. Fix the header.
2024-04-27 13:52:43 +01:00
fce1c087d4
Add basic PMP implementation to rvcpp. Seems like the RWX vs XWR order might be transposed in both the hardware and the tests
2024-04-27 13:38:10 +01:00
117c52e7b1
rvcpp: fix handling of CSR instructions which both read and write
2024-04-27 13:30:34 +01:00
a313493371
Add timer and soft IRQ support to rvcpp. Relevant sw_testcases now pass.
2024-03-22 00:52:01 +00:00
b1be56fe94
Clean up rvcpp file structure
2024-03-21 23:27:01 +00:00
b473575b7e
rvcpp: correctly model memory access faults. relevant sw_testcases now pass.
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Also, grab the special-case core RAM change from the Sv32 fork, for better performance
2024-03-21 00:33:54 +00:00
fd584ea24b
Add Xh3bextm instructions to rvcpp, and rename xh3b test to xh3bextm
2024-03-20 23:45:30 +00:00
8cbf5fceee
rvcpp: fix busted RMW CSR logic, fix ordering of CSR write vs update, csr_mcycle testcase now passes
2024-03-20 01:37:04 +00:00
55504fa8f3
Add support for Zba, Zbb, Zbc, Zbs, Zbkb to rvcpp. Passes tests
2024-03-20 01:06:13 +00:00
e1bb341876
Add support for testcase return code propagation to rvcpp.
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Hook up mtvec in bitmanip testcases to exit sim when exception taken.
2024-03-20 01:05:24 +00:00
32f65fb142
Expand rvcpp counter CSR implementation
2024-03-19 08:44:24 +00:00
af08c0becd
Fix initiation of SBA reads not being masked by previous SBA error or busy error.
2024-03-17 05:49:45 +00:00
c11581e80b
Fix use of non-always-on clock for arbitration of load/store vs SBA,
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which prevents SBA accesses from making progress whilst the processor
clock is gated during sleep.
2024-03-17 05:46:01 +00:00
0ec5caa379
formal.mk: add clk2fflogic before async2sync, to avoid complaint from that pass about asserts having TRG_WIDTH > 1
2024-03-17 05:42:39 +00:00
9bb6ed4a3e
Update tb for new cxxrtl debug_info API
2024-03-17 05:32:47 +00:00
404aeead92
Additional assertions for cm.mvsa01/mva01s IRQ testcase
2024-03-17 05:04:59 +00:00
a693cdd632
Fix up cxxrtl include paths for new yosys
2023-12-12 19:00:26 +00:00
d4212f8976
Limit multilib-gen-gen to more-useful ISA combinations
2023-11-30 05:32:39 +00:00
e8b4578b40
Add test for cm.mvsa01/cm.mva01s tearing on IRQs
2023-11-04 14:08:07 +00:00
10a6c2616a
Add utility script for generating long multilib configure lines when building riscv-gnu-toolchain
2023-11-04 12:27:31 +00:00
514ab0bb32
Typo in zcmp_irq_kill tests
2023-11-04 12:24:45 +00:00
9955807520
Check in missing xoroshiro header from amo_ops testcase
2023-11-04 12:17:04 +00:00
817a1ddfcb
Update src_only_app.mk to make overriding TB executable path easier
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(e.g. for running tests against rvcpp or an external simulator
2023-11-04 12:16:39 +00:00
2f6e98335f
Add two new tests for IRQs-over-Zcmp, and fix a bug they found:
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Interrupting the PC-setting step of a cm.popret (only) can sample the return target
as the exception return PC, which will cause the stack pointer adjust to be skipped
when returning from the IRQ. Fix this by making the PC-setting step uninterruptible
(note the PC-setting step is the instruction we execute first out of the group
of instructions specified in the Zc spec as being atomic wrt interrupts. This
does not itself imply that the PC-setting step is uninterruptible, it just
requires that when the PC-setting step retires, all following steps also retire.
However this is not sufficient given the special case logic that allows the jr
ra PC-setting step to execute before the final stack adjust as an optimisation.)
2023-11-03 21:12:21 +00:00
ef386f43c6
Disable zbs in sw_testcases compilation as a workaround for regression in GCC 12.3
2023-11-03 20:09:27 +00:00
8b301c5692
Silence useless linker rwx warning
2023-11-03 20:09:02 +00:00
31642b6d4a
Add amo_ops testcase
2023-04-01 08:47:29 +01:00
a536e3baa7
rvcpp sim: add A extension and M-mode traps
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(now passes a lot of the Hazard3 tests)
2023-04-01 08:21:43 +01:00
26d699e18c
rvcpp simulator: fix bad regnum decode for c.slli outside of x8..x15
2023-04-01 06:02:45 +01:00
54f0a593c8
Fix +x permission of riscv-compliance/clean_all script
2023-04-01 04:42:15 +01:00
d8cc132a49
tb_cxxrtl Makefile: make synthesis depend on config headers
2023-04-01 04:41:39 +01:00
86fc4e3f2d
Update embench config and readme
2023-03-31 03:02:06 +01:00
ca40c077be
Capture JTAG bitbang log from most recent SMP debug test.
...
Regarding intermittent failure of SMP debug MemorySampleSingle test:
https://twitter.com/wren6991/status/1640153934445543426
Seems to be an OpenOCD issue, not a Hazard3 issue.
2023-03-31 02:16:23 +01:00
e89ab0d095
tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ
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(i.e. single-core testbench). Avoids some odd behaviour with wide
assignment to single-bit wire from the CXXRTL harness.
2023-03-31 02:11:52 +01:00
5aee830ac0
Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH
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(clean up fallout from Zc implementation -- ensure Readme instructions will get you to hello world)
2023-03-31 01:53:28 +01:00
a861a110c1
Update to the latest riscv-arch-test. This uses the new test
...
framework -- scripts are a little janky for now.
Note there is one test failure (cebreak-01) -- analysis shows
this is due to the reference vector expecting mtval to be set
informatively, whereas our implementation (legally) ties it
to zero. Non-mtval-related signature for that test is correct
so I'm saying this is fine.
2023-03-31 01:39:48 +01:00
18d3b03cc8
Fix rm of build directory in tb_cxxrtl/Makefile
2023-03-30 22:43:48 +01:00
97121afa91
Extend testbench to allow dumping/replaying JTAG to text file.
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This allows debugging of tests that behave differently when VCD dumping
is enabled, due to the difference in execution speed.
(A couple of the SMP debug tests fail intermittently.)
2023-03-27 00:17:11 +01:00
c41fe0609b
Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests.
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Fix a couple of minor test script issues.
2023-03-26 23:00:18 +01:00
94bd965e4e
Add script for running SMP debug tests
2023-03-24 18:45:11 +00:00
97509f548a
tb_cxxrtl Makefile: better support for building multiple tb configurations
2023-03-24 18:44:37 +00:00
cbb490da6a
Bump riscv-tests for hazard3 SMP debug test config changes
2023-03-24 18:11:08 +00:00
0dd6be181d
Fix up HwbpManual test in riscv-tests fork, and update debug test list
2023-03-24 00:28:02 +00:00
43130a16e4
Fix readback of tdata2 and tinfo CSRs
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(Found due to latest riscv-openocd failing to enumerate triggers,
as it now scans tinfo before going for tdata1/mcontrol)
2023-03-23 23:33:39 +00:00
532e27dbc9
Bump riscv-tests for new debug and ISA tests. (Rebase of Hazard3 patches)
2023-03-23 23:32:28 +00:00
afcb6d283c
Missing default assignment
2023-03-23 10:57:50 +00:00
2905c1f820
Revert default for EXTENSION_ZC* to match docs in hazard3_config.vh
2023-03-23 03:07:09 +00:00
Luke Wren