8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
2bbc3637a2
Simplify CSR update logic. Showed promise in block synth but no difference to example soc. Still cleaner RTL.
2021-12-12 00:38:30 +00:00
7da67a0600
Similarly for minstret
2021-12-11 22:25:12 +00:00
1b722b5f27
Add mcycle test, fix incorrect description of mcycle in docs
2021-12-11 21:21:31 +00:00
93eca19aeb
Add test for lr/sc RAW stalls
2021-12-11 19:16:41 +00:00
763a5cd364
Add test for readability of all implemented CSRs
2021-12-11 17:50:12 +00:00
7b1da32af1
Move expected_output into tests inline
2021-12-11 16:58:25 +00:00
9460b3cd04
Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
2021-12-11 15:52:34 +00:00
f64f44f7af
Add test for identification CSRs vs expected values
2021-12-11 13:26:59 +00:00
4066e941ef
Fix sim cmdline in bitmanip-random tests
2021-12-11 13:13:21 +00:00
3fe0d92d41
Add load/store alignment testcases
2021-12-11 12:53:37 +00:00
c90727b05a
Remove padding after vector table in init.S
2021-12-11 12:22:23 +00:00
6076eba61f
Add run_all script under riscv-compliance
2021-12-11 12:08:53 +00:00
52d58fdee4
Add keep wires for debug port on bus compliance tb
2021-12-11 12:06:10 +00:00
6edfbfae8b
Add ebreak size/alignment test
2021-12-11 11:17:24 +00:00
cccc32fe16
Update instructions for running hello world under debugger
2021-12-11 10:25:29 +00:00
abe1769929
Add instruction access fault testcase
2021-12-11 09:54:00 +00:00
933f2cd65c
Fix remaining fallout from tb args change
2021-12-11 09:53:39 +00:00
6d55cd2d55
Consolidate openocd and bin-load testbenches
2021-12-11 09:46:38 +00:00
fadb9601de
Illegal instruction test
2021-12-10 00:11:18 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
7d2fa6a049
Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic
2021-12-09 06:26:31 +00:00
116e34df49
Fix commented out frontend properties which relied on non-constant past reset values
2021-12-07 20:24:29 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
dbc331dbb4
Add exclusives bus properties
2021-12-07 05:47:25 +00:00
6ef3503ef5
Add A bit to MISA, update docs
2021-12-07 05:10:20 +00:00
93be227d8a
Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
2021-12-06 20:12:23 +00:00
ed22d502fd
Fix bus stall getting stuck high when a bus fault exception isn't immediately accepted by the frontend
2021-12-06 19:28:21 +00:00
50d3d5d3b3
Maintain AMO IRQ holdoff when transitioning from data phase to error phase, to prevent error possibly being flushed
2021-12-06 19:27:20 +00:00
29c5c8ca7f
Fix AMO stall falling through when write data phase should proceed to error phase
2021-12-06 18:28:56 +00:00
8bfc089660
Slightly more strict holdoff of IRQs on AMO
2021-12-06 18:13:43 +00:00
0b3629564c
Don't apply shifter assertions to rotates
2021-12-06 18:12:23 +00:00
ac9285846f
Timer struct in IO header
2021-12-06 17:16:21 +00:00
9e7ea4adb6
Fix column width
2021-12-06 17:14:23 +00:00
c57a80f358
Add AMO + timer testcase
2021-12-06 07:47:20 +00:00
4c532240f8
Hold off IRQ when AMO is past the point of no return
2021-12-06 07:45:13 +00:00
260491405a
Fix atomic instructions not asserting decode error when A extension is disabled
2021-12-06 07:28:50 +00:00
cc38f46848
Fix AMO wdata valid left high when entering trap at just the right time
2021-12-06 07:28:50 +00:00
d86b2849c9
Bump to latest version of riscv-arch-test
2021-12-06 02:18:48 +00:00
1fa773c67a
Minimal RV32IMA + debug that fits on iCEBreaker. Not sure why area has regressed so much recently.
2021-12-05 02:16:54 +00:00
12c79c0b41
Fix feature-flag for Zbs instructions in decoder
2021-12-05 02:05:35 +00:00
9b9120960d
Fix missing RAW stall on sc.w succes result. Closing laptop again.
2021-12-05 01:05:01 +00:00
723016a739
Update ISA support in Readme
2021-12-04 23:50:50 +00:00
df658d86ff
First plausibly working AMOs. Add AMOs to instruction timings list
2021-12-04 23:44:22 +00:00
5c098866f2
Sketch in AMO support
2021-12-04 20:46:39 +00:00
34e57f0b14
Sketch in an AMO ALU
2021-12-04 18:52:41 +00:00
a8933c332d
Fix illegal issue of pipelined exclusives on the bus, and document correct timings
2021-12-04 18:23:01 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
c5d6be24f3
Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
2021-12-04 14:06:48 +00:00
607147f280
Rewrite byte pick/sign-extend logic, preparing to handle more memops
2021-12-04 12:08:54 +00:00
Luke Wren