Luke Wren
|
42632e325a
|
Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core
|
2021-07-12 21:21:16 +01:00 |
|
Luke Wren
|
27674be996
|
Start hacking in a JTAG-DTM
|
2021-07-12 01:49:32 +01:00 |
|
Luke Wren
|
f7b3097ad6
|
Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works
|
2021-07-11 16:20:39 +01:00 |
|
Luke Wren
|
0dce59daaf
|
Start hacking together a DM
|
2021-07-11 05:11:19 +01:00 |
|
Luke Wren
|
5cc483898d
|
Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
|
2021-07-10 21:02:18 +01:00 |
|
Luke Wren
|
47fa7f4d10
|
Associated doc updates
|
2021-07-10 18:53:59 +01:00 |
|
Luke Wren
|
63d661af63
|
Start hacking in debug support to the core -- seems to work as well as before adding debug!
|
2021-07-10 18:53:48 +01:00 |
|
Luke Wren
|
83244c6651
|
Add Read ID command to UART DTM
|
2021-07-10 16:14:35 +01:00 |
|
Luke Wren
|
3312ea7022
|
Add draft UART DTM
|
2021-07-08 17:57:46 +01:00 |
|
Luke Wren
|
6a38fc33a6
|
Allow MHARTID to be configured at instantiation
|
2021-07-07 16:08:08 +01:00 |
|
Luke Wren
|
58a6b8b4c8
|
Add 32IM testlist
|
2021-06-05 12:03:05 +01:00 |
|
Luke Wren
|
be79a611e1
|
Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why.
|
2021-06-04 09:19:18 +01:00 |
|
Luke Wren
|
c03bc2efb5
|
Update init.S for new IRQ functionality
|
2021-06-04 08:16:54 +01:00 |
|
Luke Wren
|
278dc8b6a2
|
meie0 default to all-zeroes
|
2021-06-04 07:37:02 +01:00 |
Luke Wren
|
af684c4e82
|
Some cleanup; correctly decode 16-bit EBREAK
|
2021-06-03 20:03:43 +01:00 |
|
Luke Wren
|
5f8d217395
|
Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
|
2021-05-31 17:54:12 +01:00 |
|
Luke Wren
|
4053458485
|
Document some IRQ CSRs, and instruction timings
|
2021-05-31 15:57:05 +01:00 |
|
Luke Wren
|
12851d3742
|
Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
|
2021-05-30 19:52:46 +01:00 |
|
Luke Wren
|
cec5dc4e3b
|
Remove old MCYCLE/MCYCLEH, implement MCOUNTINHIBIT fully, always decode tied-off HPM counters
|
2021-05-30 19:20:53 +01:00 |
|
Luke Wren
|
565b76672a
|
Make MVENDORID/MARCHID/MIMPID configurable
|
2021-05-30 18:42:43 +01:00 |
|
Luke Wren
|
12205f12c7
|
Add instruction fetch match check
|
2021-05-30 11:22:36 +01:00 |
|
Luke Wren
|
16dc905dce
|
Add simple formal bus properties check
|
2021-05-30 10:19:42 +01:00 |
|
Luke Wren
|
2330b84b73
|
Use .f for riscv-formal tb dependencies, small reshuffling of directories
|
2021-05-30 09:44:57 +01:00 |
|
Luke Wren
|
089bcc7c43
|
Typo
|
2021-05-29 23:24:18 +01:00 |
|
Luke Wren
|
ad8f251ba2
|
RVFI wrapper: use proper bus assumptions. RVFI monitor: don't mark instruction which is aligned with IRQ as invalid, because the IRQ entry is notionally behind it
|
2021-05-29 23:24:02 +01:00 |
|
Luke Wren
|
ea5db61582
|
Fix exception being passed to M when X is stalled but M is not (a load which had an unaligned address spuriously during a RAW stall on the result register)
|
2021-05-29 22:52:50 +01:00 |
|
Luke Wren
|
4b9a3c2c78
|
Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F)
|
2021-05-29 19:32:12 +01:00 |
|
Luke Wren
|
f23ec3f941
|
Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere
|
2021-05-29 18:57:43 +01:00 |
|
Luke Wren
|
65075df0e5
|
More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
|
2021-05-29 18:00:43 +01:00 |
|
Luke Wren
|
1b252d4bda
|
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
|
2021-05-23 11:59:46 +01:00 |
|
Luke Wren
|
5e61c9f9ac
|
Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc
|
2021-05-23 09:12:50 +01:00 |
|
Luke Wren
|
90acfdcbe8
|
Organise test directory into formal and sim
|
2021-05-23 07:42:35 +01:00 |
|
Luke Wren
|
7a3ce494e4
|
Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth)
|
2021-05-23 06:40:44 +01:00 |
|
Luke Wren
|
dec78a728d
|
Fix a few things that were obviously wrong, and the first signs of a plausible RVFI bridge circuit
|
2021-05-22 15:35:52 +01:00 |
|
Luke Wren
|
08e986912c
|
Also fix RAW stall on JALR instructions, oops. Runs CoreMark and Dhrystone now
|
2021-05-22 11:18:56 +01:00 |
|
Luke Wren
|
6692c1f26d
|
Fix premature taking of branches with RAW data dependencies on the previous instruction
|
2021-05-22 10:18:47 +01:00 |
|
Luke Wren
|
cc6f590f2e
|
Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still
|
2021-05-22 10:16:02 +01:00 |
|
Luke Wren
|
692abbad8b
|
Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
|
2021-05-22 07:55:13 +01:00 |
|
Luke Wren
|
844fa8f97f
|
Rename hazard5 -> hazard3
|
2021-05-21 03:46:29 +01:00 |
|
Luke Wren
|
af0af41385
|
Add small readme
|
2021-05-21 03:39:10 +01:00 |
|
Luke Wren
|
5de4f01aae
|
Change how constants are plumbed through the hierarchy. Some small cleanups of variable declaration order etc
|
2021-05-21 03:23:44 +01:00 |
|
Luke Wren
|
6dad4e20bb
|
Import from hazard5 9743a1b
|
2021-05-21 02:34:16 +01:00 |