Luke Wren
|
5db6c68c56
|
Update riscv-tests for correct misa.x value
|
2021-12-04 11:19:43 +00:00 |
|
Luke Wren
|
a988adfec8
|
Add RISC-V opcodes and memory operation codes for atomics
|
2021-12-04 11:16:24 +00:00 |
|
Luke Wren
|
52ba930638
|
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
|
2021-12-04 01:17:57 +00:00 |
|
Luke Wren
|
cd1b391714
|
More docs cleanup
|
2021-12-02 02:29:34 +00:00 |
|
Luke Wren
|
dfb07822ee
|
Remove UART DTM
|
2021-12-02 02:08:16 +00:00 |
|
Luke Wren
|
be6b2f3f76
|
Fix up DTMs to use byte addressing
|
2021-12-02 02:05:23 +00:00 |
|
Luke Wren
|
1ebccb7cce
|
Switch DM to use byte addresses on APB, not word addresses
|
2021-12-02 01:47:30 +00:00 |
|
Luke Wren
|
ebe87dce46
|
Reorganise CSR section of docs
|
2021-12-02 01:35:18 +00:00 |
|
Luke Wren
|
c5e85dea4c
|
Add mconfigptr CSR
|
2021-12-01 03:25:56 +00:00 |
|
Luke Wren
|
fad64bb6c9
|
Bump embench test submodule
|
2021-11-29 18:51:10 +00:00 |
|
Luke Wren
|
ba248c832a
|
init.S: also print out mcause when trapping an unhandled exception
|
2021-11-29 18:49:37 +00:00 |
|
Luke Wren
|
c8afb4ac33
|
Add option for fast high-half multiplies
|
2021-11-29 18:48:02 +00:00 |
|
Luke Wren
|
35c5e213c7
|
Bump embench for working benchmarks (except md5)
|
2021-11-29 00:59:14 +00:00 |
|
Luke Wren
|
d29bb13c4a
|
Replace SSH submodule URLs with HTTPS, oops
|
2021-11-28 22:26:29 +00:00 |
|
Luke Wren
|
94a3d43f27
|
Add Hazard3's registered marchid value to hdl and docs
|
2021-11-28 19:53:49 +00:00 |
|
Luke Wren
|
1aa9dbcddd
|
Fix comment typo in APB clock crossing
|
2021-11-28 17:40:57 +00:00 |
|
Luke Wren
|
0fafae1ab1
|
Regenerate PDF
|
2021-11-28 16:27:54 +00:00 |
|
Luke Wren
|
e7466ae4be
|
Move DM data0 CSR into the M-custom space, and document this
|
2021-11-28 15:52:52 +00:00 |
|
Luke Wren
|
9bf4d5105f
|
Describe possible debug topologies. Update pdf.
|
2021-11-28 09:01:23 +00:00 |
|
Luke Wren
|
4e2686d4ab
|
Finish documenting CSRs. Draw a debug topology diagram.
|
2021-11-28 08:17:23 +00:00 |
|
Luke Wren
|
76172cdade
|
Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
|
2021-11-28 06:33:35 +00:00 |
|
Luke Wren
|
79c29354d2
|
Update docs with bitmanip instructions
|
2021-11-28 03:16:45 +00:00 |
|
Luke Wren
|
800b21d2f5
|
Remove event feedback path (not logical path) in priority encoder
|
2021-11-28 02:19:01 +00:00 |
|
Luke Wren
|
ba27dd838f
|
Bump libfpga for correct bus error response from AHBL splitter in example SoC
|
2021-11-28 01:35:52 +00:00 |
|
Luke Wren
|
47ce2cc8ec
|
Add embench submodule, with configs for hazard3
|
2021-11-28 00:01:18 +00:00 |
|
Luke Wren
|
14a4f1a281
|
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
|
2021-11-27 17:19:41 +00:00 |
|
Luke Wren
|
6f1a10724b
|
Add bitmanip test vector generation script
|
2021-11-26 23:34:06 +00:00 |
|
Luke Wren
|
5d093487b7
|
Update README
|
2021-11-26 23:33:46 +00:00 |
|
Luke Wren
|
1bb7e33b69
|
Fix alignment of heap_ptr in init.S. Small ALU cleanup
|
2021-11-26 02:59:50 +00:00 |
|
Luke Wren
|
7410c52aac
|
Update readme
|
2021-11-26 02:09:39 +00:00 |
|
Luke Wren
|
8398d7ecb6
|
Hook up Zb* extension params on iCEBreaker FPGA
|
2021-11-26 01:44:57 +00:00 |
|
Luke Wren
|
8bcec11c80
|
Couple more silly mistakes
|
2021-11-26 01:30:13 +00:00 |
|
Luke Wren
|
41eeb90c7d
|
Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
|
2021-11-26 01:29:47 +00:00 |
|
Luke Wren
|
998f3fdeb7
|
Clean up silly mistakes
|
2021-11-26 00:55:57 +00:00 |
|
Luke Wren
|
58c20a39d0
|
First pass at implementing bitmanip. Breaks CXXRTL. Ooop
|
2021-11-25 23:30:35 +00:00 |
Luke Wren
|
ed6b6a3660
|
Cleanup order of declaration/use of a couple of wires
|
2021-11-25 15:16:59 +00:00 |
|
Luke Wren
|
2aac3d4f91
|
Add attempt at CPU backend diagram
|
2021-11-23 22:14:55 +00:00 |
|
Luke Wren
|
e352715fdf
|
Fix IO decode in openocd/tb.cpp
|
2021-11-23 22:12:51 +00:00 |
|
Luke Wren
|
49462a8642
|
Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh
|
2021-11-23 22:11:50 +00:00 |
|
Luke Wren
|
e05e9a4109
|
Add default_nettype none at top of every file, and default_nettype wire at bottom
|
2021-11-23 22:10:39 +00:00 |
|
Luke Wren
|
0b9b706e81
|
Safer logic for load/store blocked by preceding WFI
|
2021-11-23 22:01:14 +00:00 |
|
Luke Wren
|
4d14203586
|
Update riscv-tests fork for crash loop debug test
|
2021-11-23 21:58:39 +00:00 |
|
Luke Wren
|
60f364e561
|
Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker
|
2021-11-21 15:55:52 +00:00 |
|
Luke Wren
|
ba9a7b4a03
|
Fix broken link in readme
|
2021-11-21 14:58:07 +00:00 |
|
Luke Wren
|
c1f17b0b23
|
Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
|
2021-11-06 09:59:27 +00:00 |
|
Luke Wren
|
cc6a6c09ba
|
Vaguely implement wfi
|
2021-11-05 18:48:42 +00:00 |
Richard-Gordon
|
375a6d60b7
|
Correct mnemonic when logging unsigned sltiu instruction
|
2021-10-08 12:02:37 +01:00 |
|
Luke Wren
|
cfe16caf41
|
Remove some old todos
|
2021-09-05 22:20:40 +01:00 |
|
Luke Wren
|
e9fccffca0
|
Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
|
2021-09-05 04:45:38 +01:00 |
|
Luke Wren
|
65bfca5fdf
|
Fix latent bug with asynchronous debug entry during stalled load/store address phase
|
2021-09-04 07:49:29 +01:00 |