f1cda26bcc
Oops, try a little harder this time to ensure local monitor is cleared by sc.w errors _always_, even if lined up with trap entry stalls etc
2021-12-12 23:32:01 +00:00
25b44d04cf
Add more properties wrt AMO. Fix awful bugs in interaction between AMOs and prior lr/sc, prior load/store exception, or IRQ which is asserted then deasserted. Fix sc with HRESP=1 HEXOKAY=1 not clearing the local monitor (not a bug, but unfriendly).
2021-12-12 23:24:25 +00:00
88fea7acfa
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
2021-12-12 18:28:23 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
2bbc3637a2
Simplify CSR update logic. Showed promise in block synth but no difference to example soc. Still cleaner RTL.
2021-12-12 00:38:30 +00:00
9460b3cd04
Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
2021-12-11 15:52:34 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
7d2fa6a049
Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic
2021-12-09 06:26:31 +00:00
116e34df49
Fix commented out frontend properties which relied on non-constant past reset values
2021-12-07 20:24:29 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
6ef3503ef5
Add A bit to MISA, update docs
2021-12-07 05:10:20 +00:00
93be227d8a
Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
2021-12-06 20:12:23 +00:00
ed22d502fd
Fix bus stall getting stuck high when a bus fault exception isn't immediately accepted by the frontend
2021-12-06 19:28:21 +00:00
50d3d5d3b3
Maintain AMO IRQ holdoff when transitioning from data phase to error phase, to prevent error possibly being flushed
2021-12-06 19:27:20 +00:00
29c5c8ca7f
Fix AMO stall falling through when write data phase should proceed to error phase
2021-12-06 18:28:56 +00:00
8bfc089660
Slightly more strict holdoff of IRQs on AMO
2021-12-06 18:13:43 +00:00
0b3629564c
Don't apply shifter assertions to rotates
2021-12-06 18:12:23 +00:00
4c532240f8
Hold off IRQ when AMO is past the point of no return
2021-12-06 07:45:13 +00:00
260491405a
Fix atomic instructions not asserting decode error when A extension is disabled
2021-12-06 07:28:50 +00:00
cc38f46848
Fix AMO wdata valid left high when entering trap at just the right time
2021-12-06 07:28:50 +00:00
12c79c0b41
Fix feature-flag for Zbs instructions in decoder
2021-12-05 02:05:35 +00:00
9b9120960d
Fix missing RAW stall on sc.w succes result. Closing laptop again.
2021-12-05 01:05:01 +00:00
df658d86ff
First plausibly working AMOs. Add AMOs to instruction timings list
2021-12-04 23:44:22 +00:00
5c098866f2
Sketch in AMO support
2021-12-04 20:46:39 +00:00
34e57f0b14
Sketch in an AMO ALU
2021-12-04 18:52:41 +00:00
a8933c332d
Fix illegal issue of pipelined exclusives on the bus, and document correct timings
2021-12-04 18:23:01 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
607147f280
Rewrite byte pick/sign-extend logic, preparing to handle more memops
2021-12-04 12:08:54 +00:00
a988adfec8
Add RISC-V opcodes and memory operation codes for atomics
2021-12-04 11:16:24 +00:00
52ba930638
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
2021-12-04 01:17:57 +00:00
dfb07822ee
Remove UART DTM
2021-12-02 02:08:16 +00:00
be6b2f3f76
Fix up DTMs to use byte addressing
2021-12-02 02:05:23 +00:00
1ebccb7cce
Switch DM to use byte addresses on APB, not word addresses
2021-12-02 01:47:30 +00:00
c5e85dea4c
Add mconfigptr CSR
2021-12-01 03:25:56 +00:00
c8afb4ac33
Add option for fast high-half multiplies
2021-11-29 18:48:02 +00:00
94a3d43f27
Add Hazard3's registered marchid value to hdl and docs
2021-11-28 19:53:49 +00:00
1aa9dbcddd
Fix comment typo in APB clock crossing
2021-11-28 17:40:57 +00:00
e7466ae4be
Move DM data0 CSR into the M-custom space, and document this
2021-11-28 15:52:52 +00:00
76172cdade
Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
2021-11-28 06:33:35 +00:00
800b21d2f5
Remove event feedback path (not logical path) in priority encoder
2021-11-28 02:19:01 +00:00
14a4f1a281
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
2021-11-27 17:19:41 +00:00
5d093487b7
Update README
2021-11-26 23:33:46 +00:00
1bb7e33b69
Fix alignment of heap_ptr in init.S. Small ALU cleanup
2021-11-26 02:59:50 +00:00
8bcec11c80
Couple more silly mistakes
2021-11-26 01:30:13 +00:00
41eeb90c7d
Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
2021-11-26 01:29:47 +00:00
998f3fdeb7
Clean up silly mistakes
2021-11-26 00:55:57 +00:00
58c20a39d0
First pass at implementing bitmanip. Breaks CXXRTL. Ooop
2021-11-25 23:30:35 +00:00
ed6b6a3660
Cleanup order of declaration/use of a couple of wires
2021-11-25 15:16:59 +00:00
49462a8642
Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh
2021-11-23 22:11:50 +00:00
e05e9a4109
Add default_nettype none at top of every file, and default_nettype wire at bottom
2021-11-23 22:10:39 +00:00
Luke Wren
Luke Wren