fbd96363c8
PPA: predecode stage 2 bypass mux controls at end of stage 1
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OR-of-ANDs style mux is used because it maps well on FPGA (particularly
this 3-input mux maps straight onto LUT6) and because this allows the
zeroing of x0 to be implemented directly in the mux
2024-06-06 08:36:55 +01:00
35745117d9
Fix typo in src_only_app.mk
2024-06-06 08:33:55 +01:00
2665e2acc6
Fix case overlap lint in instr_decompress. Now verilator lint clean
2024-06-06 07:18:52 +01:00
e3b3893cdf
Fix partial case overlap lint for shared A/Zbb ALU ops
2024-06-06 06:58:59 +01:00
e34aa5bb45
rvcpp: implement MPRV, and fix up CSR write tracing
2024-06-02 12:46:41 +01:00
877c6aa5ee
Add trace disassembly annotation script for rvcpp, and add runtests support for passing flags to tb, and running post-processing commands on test results.
2024-06-02 11:20:58 +01:00
b026814674
runtests: use argparse for argument parsing, and support passing a different tb executable
2024-06-02 10:36:29 +01:00
a9ba69f4dd
Better default flags for CoreMark
2024-06-02 10:25:07 +01:00
a38981f989
Enable -Wextra for rvcpp
2024-06-02 10:18:40 +01:00
cbc2172930
rvcpp: Add Zcb support. Also fix -Wparentheses as sometimes it does find things
2024-06-02 10:15:57 +01:00
3a747e1dde
Disable zcmp in multilib-gen-gen for now, as it is still not supported in latest binutils release
2024-06-01 18:24:06 +01:00
b883be3c20
Update multilib-gen-gen for GCC14 extensions: Zicond, Zcmp, Zcb. Hopefully handle the Zca vs C thing gracefully.
2024-06-01 18:01:09 +01:00
7430523c45
Update .gitignore in riscv-tests to ignore output of debug tests
2024-06-01 15:53:53 +01:00
96e0e66597
Fix fence.i being marked invalid in debug mode.
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This was done because the implementation depends on the value of PC
(it's a jump-to-next), and PC-dependent instructions are permitted to
be flagged as invalid in debug mode, to permit sharing of PC and the
dpc CSR.
However this is not valid in this case because the dependency on PC is
an implementation detail, not an architected dependency. Instead just
suppress the jump in debug mode. Suppressing the jump is still required
to avoid flushing following program buffer entries from the prefetch
queue during debug mode execution.
From a functional point of view not much has changed, it just removes
an inconsistency where fence.i appeared to be implemented in M/U mode
but not in debug mode. This removes a complaint from openocd when it
executes a fence + fence.i after writing to memory.
2024-06-01 15:38:33 +01:00
b55e43eb16
Fix event loops reported by Verilator UNOPTFLAT lints.
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Decode is now split into a block which depends only on the instruction
bits, and a block which gates critical decode signals based on fetch
faults, invalidity etc.
Apply a similar transform to the gating of the uop counter update.
cxxrtl performance seems unchanged after removing the event loops, but
verilator and live-scheduled simulators should improve.
2024-06-01 15:25:16 +01:00
26f78732fd
Fix final two width lints in JTAG DTM. They now shrink the design by 100 LUTs instead of growing it? A mystery
2024-05-29 15:58:45 +01:00
d1f1421728
Fix width lints in muldiv_seq, onehot_priority_dynamic, and irq_ctrl. All cosmetic.
2024-05-29 15:52:53 +01:00
799f4f2c26
Fix verilator lint width issues in triggers, PMP, DM.
...
There was one genuine issue introduced by PPA changes in 78a5cb98e
2024-05-29 15:32:45 +01:00
0b027390fa
Remove conditioning of uop_atomic flag on non-invalid instructions,
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which is unnecessary and came up on a Verilator UNOPTFLAT report. Add
assertion to make sure this case is unreachable.
2024-05-29 15:32:38 +01:00
6da0e12bbd
Merge latest riscv-tests: updates for debug + ISA tests.
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Add a list of excluded tests, with reasons, to run-debug-tests.sh
2024-05-29 14:03:17 +01:00
d239de803c
Do not rely on environment variables for any intra-project paths
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It's no longer necessary to source `sourceme` before running any
of the project Makefiles.
2024-05-27 16:53:06 +01:00
8b9503c804
lint: clean up a couple of width fixes in JTAG DTM, and add missing
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default case to DM acmd state machine. Also remove unnecessary clear
of JTAG DR shifter on TAP reset state, which saves a bit of logic. Two
width mismatches are left unfixed in the DTM (the ones with shifts)
because they bizarrely increase area by 100 LUT4s when fixed.
2024-05-27 13:12:18 +01:00
141da55507
tb: remove the WIDE_TIMER_IRQ flag in favour of always having the same tb interface. Second timer IRQ is ignored in single-core tb. Also, fix hmaster not being connected, which Verilator complains about.
2024-05-27 12:24:54 +01:00
5b31e26790
tb Makefile: use clang++-16 explicitly, because clang++-18 (now default on Ubuntu 24.04) has a >20x compile time regression
2024-05-27 11:06:50 +01:00
78a5cb98ea
PPA: Register instruction injection output from DM, to reduce routing impact on frontend prefetch queue
2024-05-27 08:12:07 +01:00
360b034f76
Fix a few width issues identified by verilator lint. All of them gave
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well-defined correct results already (i.e. correctly zero-extended per
spec) but best to avoid the noise.
2024-05-26 17:32:24 +01:00
ee8876f68a
Avoid zero-total-width concatenations for parameters parameterised
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by other parameters (was safe because uses of these parameters are
generated out when their widths are zero, but verilator rightfully
complains)
2024-05-26 16:47:20 +01:00
fbacbe82a7
PPA: simplify generation of uop_atomic and uop_seq_end flags in instr_decompress to be independent of most instruction bits. Add some new assertions on behaviour of uop signals outside of uop sequences.
2024-05-26 16:24:07 +01:00
c550d79047
Debug tests: workaround recent GCC requiring Zicsr set for CSR instructions
2024-05-12 13:33:14 +01:00
a6558e554a
Set misa.b when all of Zba, Zbb and Zbs are enabled.
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(The B extension has now been ratified as this combination of extensions.)
2024-05-11 12:13:35 +01:00
6db1edc675
Add dummy h3.msleep CSR to rvcpp
2024-05-11 11:02:01 +01:00
a84742abd4
Fix mstatus.mie still being respected when privilege is less than M.
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Extend umode_wfi testcase to cover this, and in particular to check
that when entering U-mode with IRQs pending, the IRQs execute before any
exceptions occurring as a result of the U-mode instructions.
2024-05-11 10:49:13 +01:00
194c9a9052
Implement WFI in rvcpp. The umode_wfi test still does not pass, because it relies on a bug in Hazard3 (mstatus.mie disables IRQs in U-mode as well as M-mode, but is supposed to be ignored in U-mode).
2024-04-27 20:48:30 +01:00
78260e86e7
rvcpp: parameterise number of PMP regions, and set to match tb default. Fix region locking. Mask pmpaddr to 30 bits, to match Hazard3 32-bit physical address space.
2024-04-27 19:57:18 +01:00
ebe5a44454
rvcpp: fix up PMP address mask for all-ones pmpaddr, and raise instruction fault on instruction stradding two PMP regions, like the hardware
2024-04-27 19:34:17 +01:00
7d370292b0
Fix transposition of RWX <-> XWR in PMP implementation.
...
None of upstream tests used for Hazard3 seem to cover X != R. The
Hazard3 tests covered this case, but the header file for the tests has
the same mistake. Fix the header.
2024-04-27 13:52:43 +01:00
fce1c087d4
Add basic PMP implementation to rvcpp. Seems like the RWX vs XWR order might be transposed in both the hardware and the tests
2024-04-27 13:38:10 +01:00
117c52e7b1
rvcpp: fix handling of CSR instructions which both read and write
2024-04-27 13:30:34 +01:00
a313493371
Add timer and soft IRQ support to rvcpp. Relevant sw_testcases now pass.
2024-03-22 00:52:01 +00:00
b1be56fe94
Clean up rvcpp file structure
2024-03-21 23:27:01 +00:00
b473575b7e
rvcpp: correctly model memory access faults. relevant sw_testcases now pass.
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Also, grab the special-case core RAM change from the Sv32 fork, for better performance
2024-03-21 00:33:54 +00:00
fd584ea24b
Add Xh3bextm instructions to rvcpp, and rename xh3b test to xh3bextm
2024-03-20 23:45:30 +00:00
8cbf5fceee
rvcpp: fix busted RMW CSR logic, fix ordering of CSR write vs update, csr_mcycle testcase now passes
2024-03-20 01:37:04 +00:00
55504fa8f3
Add support for Zba, Zbb, Zbc, Zbs, Zbkb to rvcpp. Passes tests
2024-03-20 01:06:13 +00:00
e1bb341876
Add support for testcase return code propagation to rvcpp.
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Hook up mtvec in bitmanip testcases to exit sim when exception taken.
2024-03-20 01:05:24 +00:00
32f65fb142
Expand rvcpp counter CSR implementation
2024-03-19 08:44:24 +00:00
af08c0becd
Fix initiation of SBA reads not being masked by previous SBA error or busy error.
2024-03-17 05:49:45 +00:00
c11581e80b
Fix use of non-always-on clock for arbitration of load/store vs SBA,
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which prevents SBA accesses from making progress whilst the processor
clock is gated during sleep.
2024-03-17 05:46:01 +00:00
0ec5caa379
formal.mk: add clk2fflogic before async2sync, to avoid complaint from that pass about asserts having TRG_WIDTH > 1
2024-03-17 05:42:39 +00:00
9bb6ed4a3e
Update tb for new cxxrtl debug_info API
2024-03-17 05:32:47 +00:00
Luke Wren