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  • d03a82a826 Add instruction fetch faults Luke Wren 2021-09-04 02:57:39 +0100
  • 9173bcf585 Experimentally add SPI XIP to SoC (breaks FTDI UART on iCEBreaker -- need to move UART to a PMOD to avoid IO conflict) Luke Wren 2021-08-21 17:04:15 +0100
  • e16ae06cb5 Clean up timer Luke Wren 2021-08-21 17:03:32 +0100
  • 9dd091b7b5 Doh typo Luke Wren 2021-08-20 23:02:31 +0100
  • b99e5b8a67 Convert timer to serial for smaller area. Rather untested Luke Wren 2021-08-20 22:27:15 +0100
  • 4aba165166 First pass at a 64-bit system timer Luke Wren 2021-08-20 21:49:05 +0100
  • 924967ee72 Back off ULX3S frequency to 40 MHz -- 50 works fine but fails to close after increasing RAM from 4k to 128k Luke Wren 2021-07-25 13:29:41 +0100
  • 5976a8a9b7 Add activity LED to iCEBreaker Luke Wren 2021-07-25 13:13:41 +0100
  • 91edd62ea1 Bump libfpga for FIFO coding style tweak Luke Wren 2021-07-24 22:06:57 +0100
  • 8263ee3a5d Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception Luke Wren 2021-07-24 15:31:33 +0100
  • 6fcc74a043 Add some instructions to Readme Luke Wren 2021-07-24 11:50:23 +0100
  • 70a44d9681 Small code cleanup Luke Wren 2021-07-24 10:08:27 +0100
  • 2b1dee4bcc Fix broken submodule path Vadzim Dambrouski 2021-07-24 02:05:55 +0300
  • 155d3ba554 Tie off 1 or 2 LSBs of DPC depending on IALIGN Luke Wren 2021-07-23 23:09:03 +0100
  • 115cb2c50f Tweaks to example soc configuration Luke Wren 2021-07-23 23:08:23 +0100
  • 279e4b4f29 Implement mstatush as hardwired-0, as required by priv-1.12 Luke Wren 2021-07-23 21:52:01 +0100
  • 2ae30183aa Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG. Luke Wren 2021-07-23 18:32:47 +0100
  • 8ceae7e9e6 Start hacking on ECP5 JTAG DTM Luke Wren 2021-07-23 00:36:55 +0100
  • 41477ce479 Extract DTM bus/control logic from the JTAG-related parts Luke Wren 2021-07-22 19:25:50 +0100
  • b0d11c0ab7 Add RISC-V debug tests Luke Wren 2021-07-22 17:50:04 +0100
  • c14960ee1b Add mtime/mtimecmp to openocd testbench Luke Wren 2021-07-22 17:31:26 +0100
  • 5d2a562f65 Just use read_verilog; write_cxxrtl when building tb_cxxrtl Luke Wren 2021-07-22 17:30:30 +0100
  • 8cdde82248 Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends Luke Wren 2021-07-20 00:12:55 +0100
  • 7d24f42da9 Oops, properly fix platform IRQ mcause numbers Luke Wren 2021-07-19 09:32:59 +0100
  • 65fb62901e Mask off trap entry assertion from IRQs when in debug mode. Because the IRQ is level-sensitive, this caused trap entry to be held asserted when an IRQ fired in debug mode. This was exposed by the last bug fix -- it is only seen now that MIE+MPIE shuffling is correctly disabled in debug mode. Luke Wren 2021-07-19 00:19:56 +0100
  • 70443fa557 Disable shifting of MIE/MPIE stack when in or entering debug mode Luke Wren 2021-07-18 21:14:11 +0100
  • e4b0d999cb Minor doc updates Luke Wren 2021-07-18 20:45:08 +0100
  • d30fc46f5b Fix IRQ mcause not being set correctly when vectoring is disabled Luke Wren 2021-07-18 20:44:39 +0100
  • c56c75e14b More dicking with yosys cmd for tb_cxxrtl; Luke Wren 2021-07-18 16:45:48 +0100
  • 12bf9bb570 Make CXXRTL testbench ~25% faster whitequark 2021-07-18 13:30:38 +0000
  • 2618ae0c07 Double-step() after clock posedge to workaround CXXRTL port propagation issue Luke Wren 2021-07-18 16:03:53 +0100
  • ce5cc1f150 oops, bounds checking on free-running tb_cxxrtl Luke Wren 2021-07-18 15:20:25 +0100
  • e95b465e26 Typo in address of mcountinhibit! Luke Wren 2021-07-17 19:27:01 +0100
  • d9300ee127 Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry Luke Wren 2021-07-17 19:26:45 +0100
  • 8014239d47 openocd tb: report AHB error response when processor accesses outside of RAM/IO Luke Wren 2021-07-17 19:26:05 +0100
  • 5deff12f95 DM: don't report as running/halted in dmstatus if unavailable. Luke Wren 2021-07-17 16:45:36 +0100
  • ab0b4a04f0 Also support progbuf in abstractauto. Luke Wren 2021-07-17 15:08:00 +0100
  • 46f95f859d Some doc updates Luke Wren 2021-07-17 12:58:08 +0100
  • 14ba030271 Example soc tweaks, add openocd config Luke Wren 2021-07-16 20:44:14 +0100
  • 8e3dc62b97 Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions Luke Wren 2021-07-16 20:43:24 +0100
  • 5aca6be572 Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR. Luke Wren 2021-07-16 18:28:30 +0100
  • ce5152a4f4 Implement HALTSUM0 and HALTSUM1 registers Luke Wren 2021-07-16 17:58:28 +0100
  • 62822b2e1d Couple of usability improvements for openocd testbench Luke Wren 2021-07-15 19:42:49 +0100
  • 011008efd1 Fix detection of exception-like vs IRQ-like halt/trap entries Luke Wren 2021-07-15 19:41:35 +0100
  • 71ec9fa283 Fix exception entry not counting as a step point for dcsr.step, and mask off IRQs in step mode (we tie dcsr.stepie = 0) Luke Wren 2021-07-14 20:39:51 +0100
  • 9643a57ba9 Slightly less braindead TCP interactions for openocd JTAG bitbang testbench, much more interactive now Luke Wren 2021-07-14 19:20:27 +0100
  • f4952ab66d Add simple example SoC, hangs nextpnr for some reason! Luke Wren 2021-07-13 03:40:06 +0100
  • 307955c810 Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference Luke Wren 2021-07-13 01:10:55 +0100
  • 93c7039ea1 Sync doc updates Luke Wren 2021-07-12 22:13:31 +0100
  • 4b650ac437 DM: add missing w1c to abstract cmderr, add capture of last abstract command for use with abstractauto Luke Wren 2021-07-12 21:26:00 +0100
  • 42632e325a Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core Luke Wren 2021-07-12 21:21:16 +0100
  • 27674be996 Start hacking in a JTAG-DTM Luke Wren 2021-07-12 01:49:32 +0100
  • f7b3097ad6 Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works Luke Wren 2021-07-11 16:20:39 +0100
  • 0dce59daaf Start hacking together a DM Luke Wren 2021-07-11 05:11:19 +0100
  • 5cc483898d Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode Luke Wren 2021-07-10 21:02:18 +0100
  • 47fa7f4d10 Associated doc updates Luke Wren 2021-07-10 18:53:59 +0100
  • 63d661af63 Start hacking in debug support to the core -- seems to work as well as before adding debug! Luke Wren 2021-07-10 18:53:41 +0100
  • 83244c6651 Add Read ID command to UART DTM Luke Wren 2021-07-10 16:14:35 +0100
  • 3312ea7022 Add draft UART DTM Luke Wren 2021-07-08 17:57:46 +0100
  • 6a38fc33a6 Allow MHARTID to be configured at instantiation Luke Wren 2021-07-07 16:08:08 +0100
  • 58a6b8b4c8 Add 32IM testlist Luke Wren 2021-06-05 12:03:05 +0100
  • be79a611e1 Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why. Luke Wren 2021-06-04 09:19:18 +0100
  • c03bc2efb5 Update init.S for new IRQ functionality Luke Wren 2021-06-04 08:16:54 +0100
  • 278dc8b6a2 meie0 default to all-zeroes Luke Wren 2021-06-04 07:37:02 +0100
  • af684c4e82 Some cleanup; correctly decode 16-bit EBREAK Luke Wren 2021-06-03 20:03:43 +0100
  • 5f8d217395 Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0 Luke Wren 2021-05-31 17:54:12 +0100
  • 4053458485 Document some IRQ CSRs, and instruction timings Luke Wren 2021-05-31 15:57:05 +0100
  • 12851d3742 Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set Luke Wren 2021-05-30 19:52:46 +0100
  • cec5dc4e3b Remove old MCYCLE/MCYCLEH, implement MCOUNTINHIBIT fully, always decode tied-off HPM counters Luke Wren 2021-05-30 19:20:53 +0100
  • 565b76672a Make MVENDORID/MARCHID/MIMPID configurable Luke Wren 2021-05-30 18:42:43 +0100
  • 12205f12c7 Add instruction fetch match check Luke Wren 2021-05-30 11:22:36 +0100
  • 16dc905dce Add simple formal bus properties check Luke Wren 2021-05-30 10:19:42 +0100
  • 2330b84b73 Use .f for riscv-formal tb dependencies, small reshuffling of directories Luke Wren 2021-05-30 09:44:57 +0100
  • 089bcc7c43 Typo Luke Wren 2021-05-29 23:24:18 +0100
  • ad8f251ba2 RVFI wrapper: use proper bus assumptions. RVFI monitor: don't mark instruction which is aligned with IRQ as invalid, because the IRQ entry is notionally behind it Luke Wren 2021-05-29 23:24:02 +0100
  • ea5db61582 Fix exception being passed to M when X is stalled but M is not (a load which had an unaligned address spuriously during a RAW stall on the result register) Luke Wren 2021-05-29 22:52:50 +0100
  • 4b9a3c2c78 Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F) Luke Wren 2021-05-29 19:32:12 +0100
  • f23ec3f941 Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere Luke Wren 2021-05-29 18:57:43 +0100
  • 65075df0e5 More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus Luke Wren 2021-05-29 18:00:43 +0100
  • 1b252d4bda Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2 Luke Wren 2021-05-23 11:59:46 +0100
  • 5e61c9f9ac Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc Luke Wren 2021-05-23 09:12:50 +0100
  • 90acfdcbe8 Organise test directory into formal and sim Luke Wren 2021-05-23 07:41:03 +0100
  • 7a3ce494e4 Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth) Luke Wren 2021-05-23 06:40:44 +0100
  • dec78a728d Fix a few things that were obviously wrong, and the first signs of a plausible RVFI bridge circuit Luke Wren 2021-05-22 15:35:52 +0100
  • 08e986912c Also fix RAW stall on JALR instructions, oops. Runs CoreMark and Dhrystone now Luke Wren 2021-05-22 11:18:56 +0100
  • 6692c1f26d Fix premature taking of branches with RAW data dependencies on the previous instruction Luke Wren 2021-05-22 10:18:47 +0100
  • cc6f590f2e Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still Luke Wren 2021-05-22 10:16:02 +0100
  • 692abbad8b Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance Luke Wren 2021-05-22 07:54:04 +0100
  • 844fa8f97f Rename hazard5 -> hazard3 Luke Wren 2021-05-21 03:46:29 +0100
  • af0af41385 Add small readme Luke Wren 2021-05-21 03:39:10 +0100
  • 5de4f01aae Change how constants are plumbed through the hierarchy. Some small cleanups of variable declaration order etc Luke Wren 2021-05-21 03:23:44 +0100
  • 6dad4e20bb Import from hazard5 9743a1b Luke Wren 2021-05-21 02:34:16 +0100