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119 Commits

Author SHA1 Message Date
Chen Xin eb28f8b3ed move ArraysMatch function into src/tim/vx/test_utils.h 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-08-26 16:28:08 +08:00
Chen Xin 3d64cfc4ef add avgpool test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-08-26 16:28:08 +08:00
chxin66 5e09e98c1a
Add Gelu support for tim::vx (#153) 
* Add map for Gelu

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-08-17 20:37:12 +08:00
jing.tang a364c3eafb add Swish op 2021-08-16 19:30:14 +08:00
Jing.Deng 4d53e042c8 add the customer case.(only include wrong case) 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-08-13 11:57:57 +08:00
xiang.zhang e27e15925c Add unidirectional sequence lstm support 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-08-09 13:43:33 +08:00
xiang.zhang d4a13e18a9 Minor refinement: use tensor pointer after check 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-08-04 11:31:26 +08:00
jing.tang f0d4118f87 Update ops doc for internal 1.1.32.1 2021-08-04 11:30:45 +08:00
Kainan Cha 6a949bb315 Add align_corners support for SpatialTransformer 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-08-03 10:52:51 +08:00
Kainan Cha 4d4bc08d6a Update internal to 1.1.32.1 
SHA: 215204

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-08-02 16:19:21 +08:00
zhao.xia 8fb3a7e6fb Remove customer test 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-07-30 11:19:32 +08:00
Your Name 70c427256d Fix groupconv2d pad parameter 2021-07-29 17:23:45 +08:00
Chen Xin a09ffe8b98 addn unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-07-22 10:41:25 +08:00
Jing.Deng 3a0bc515a1 add unit test for customer use case 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-07-22 09:55:48 +08:00
Jing.Deng f9cb2dbe45 fix the axis issue about perchannel quantized conv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-07-09 14:56:39 +08:00
yuenan.li 2f8f87d1cb Add Clone API for SpatialTrasformer 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 17:34:57 +08:00
zhao.xia 8aa11f5f29 Support SpatialTransformer 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-07-06 12:56:28 +08:00
yuenan.li 29f1efc492 add API 'Clone' to tim_vx op and support default layout inference 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 12:29:18 +08:00
zhao.xia 21ecf5262e Add map for Matmul 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-29 16:06:35 +08:00
zhao.xia 3fa2bf519a Add map for moments 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-29 15:58:51 +08:00
Kainan Cha 3c59694025 Update internal to 1.1.32 
SHA: 9aa0b0f

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-29 11:25:36 +08:00
yuenan.li 98b9759663 Refine arg in layout inference 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-29 11:24:28 +08:00
Jing.Deng be066fb9bd add float32, uint8 and int8 unit_tests for transposeConv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-24 21:27:16 +08:00
yuenan.li 1e42cfd668 Support layout inference for nbg 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-24 17:28:02 +08:00
yuenan.li f8f2c6d519 Fix layout inference for traspose convolution 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-21 17:14:16 +08:00
Jing.Deng 1672ef99ed add uint8 and int8 unit_test for depthwise convolution. modify the api of 'conv2d' constructor 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-18 14:10:11 +08:00
xiang.zhang 574c036a69 Fix FullyConnect layer crash 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-06-16 16:05:16 +08:00
Robert Kalmar 64989c6b4a Added option to use extenal OVXLIB library 
Signed-off-by: Robert Kalmar <robert.kalmar@nxp.com>
 2021-06-16 15:00:35 +08:00
Jing.Deng c77217745f add float32 unit_test for depthwise convolution 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-13 12:03:13 +08:00
Jing.Deng e2c52d2d8a add int8 quantized unit_test for conv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-10 11:38:26 +08:00
Kainan Cha a7d962ac5c Minor fixup for unit test case naming 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-09 10:51:26 +08:00
zhao.xia 0ed1e8947f Add new APIs for conv, deconv and fc 
The new apis remvoe weights, oc_count and ksize.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-07 21:48:13 +08:00
Jing.Deng 8d35c4dd7a add uint8 quantized unit_test for conv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-07 13:30:43 +08:00
Kainan Cha 9e10d88fc7 Update OP ReadMe 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-07 12:39:42 +08:00
zhao.xia f59f26412b Add GroupedConv2d 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-04 16:53:25 +08:00
zhao.xia 353feca56a Add tile 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 18:29:32 +08:00
zhao.xia bd9c5df70a Add pad parameter to pool2d 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 16:28:42 +08:00
zhao.xia 748658e47d Add Unstack 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 16:24:31 +08:00
Kainan Cha 89c7b27693 Update README 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-03 12:10:24 +08:00
zhao.xia 8a15abf12b Add ScatterND 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 11:22:58 +08:00
Kainan Cha 39bd5ddd32 Add support for Linear Activation 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-02 17:10:57 +08:00
Kainan Cha 94fe57489b Update OP readme 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-02 01:03:20 +08:00
yuenan.li 1f08618403 Supprt layout inference for Operations 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-02 00:53:11 +08:00
zhao.xia 26948d6646 Rename Unmaxpool2d to MaxUnpool2d 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-31 12:48:51 +08:00
Nightingale 9c60671031
Add map for UnMaxpool2d (#83) 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-28 17:09:26 +08:00
Kainan Cha 18a928ee69 Add Op MaxpoolWithArgmax 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-27 18:59:35 +08:00
liyuenan fae5cede7a
Support layout inference for ops (#77) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-27 10:33:44 +08:00
zhao.xia a1ba85691a Add map for LogSoftmax 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-26 11:37:16 +08:00
zhao.xia 37f686c34d Remove DownScaleSizeRounding type 
Use RoundType instead of DownScaleSizeRounding.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-25 16:48:50 +08:00
zhao.xia 260b0c3f2d Update Resize1d cases 
Fix resize1d uint8 bilinear case to float.
Add new uint8 resize nearest case.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-25 13:55:30 +08:00