1d0fc21430
Readme.md / doc: clarify "naturally aligned regions", no TOR support
...
While NA4 and NAPOT are the only "naturally aligned" addressing modes
in the RISC-V PMP (Privileged) Spec, calling their support out by
name, and clearly stating that the TOR addressing mode is not
supported, can clarify this fact for software / OS developers.
This is a common point of confusion and frustration when porting to
new RISC-V chips and so increased visbility of this limitation in the
documentation and README might help.
2024-08-08 20:44:43 -07:00
0003e016a0
Update Readme.md
2024-08-08 08:11:54 -07:00
7d70dcedec
Add new branch names to Readme.md
2024-08-07 22:51:04 -07:00
f3cb354b76
Typo in readme
2024-08-07 22:22:05 -07:00
42c4ac305b
Fix deprecation warning for tb openocd.cfg, and update example output in Readme.md
2024-08-07 16:44:43 -07:00
a9555c8d8c
Add Contributing.md
2024-08-07 14:16:32 -07:00
9c56e669cd
Standardise on a single ISA variant for default test builds, and align this with the lightweight toolchain config in the Readme
...
(Automated test builds for multiple ISA variants still yet to be implemented)
2024-08-07 13:34:36 -07:00
ddf7fcacdc
Add note on clang-16 to Readme
2024-08-07 13:19:37 -07:00
12d7550be5
Readme: Use non-recursive clone for riscv-gnu-toolchain. Use shallow clone for gcc14. (Save bandwidth and disk space)
2024-08-07 11:40:55 -07:00
0076b408fd
Update readme instructions for Ubuntu 24.04
2024-08-07 07:28:51 -07:00
d239de803c
Do not rely on environment variables for any intra-project paths
...
It's no longer necessary to source `sourceme` before running any
of the project Makefiles.
2024-05-27 16:53:06 +01:00
86fc4e3f2d
Update embench config and readme
2023-03-31 03:02:06 +01:00
b58cde882a
Add link to Zcb/Zcmp specs
2023-03-22 02:48:56 +00:00
c4e0c15160
Fix hookup of uop_atomic signal
2023-03-20 02:40:49 +00:00
99c0660c3e
Fix decompress of c.sb/c.sh
...
Can now run CoreMark, Hazard3 sw testcases etc using core-v compiler
with Zcb enabled.
2023-03-16 20:36:36 +00:00
78d937e5c8
Yeet Zcb into core
2023-03-16 18:48:15 +00:00
d56e217a40
Work on docs. Document config options, expand the intro, move instruction timings and pseudocode to appendices.
2022-08-27 20:13:21 +01:00
f9dafa3867
Update readme
2022-08-22 09:25:37 +01:00
9bc72cca08
Update configure line for riscv-gnu-toolchain in readme
2022-07-06 22:41:32 +01:00
5455349961
Add menvcfg CSR, and comment explaining why we don't have mseccfg CSR
2022-06-26 01:25:48 +01:00
b823132a6e
Remove experimental description from U-mode and PMP. Add list of specifications.
2022-05-31 01:24:36 +01:00
10ca3aec80
Add U-mode and PMP to readme
2022-05-24 20:41:25 +01:00
cccc32fe16
Update instructions for running hello world under debugger
2021-12-11 10:25:29 +00:00
723016a739
Update ISA support in Readme
2021-12-04 23:50:50 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
14a4f1a281
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
2021-11-27 17:19:41 +00:00
5d093487b7
Update README
2021-11-26 23:33:46 +00:00
7410c52aac
Update readme
2021-11-26 02:09:39 +00:00
60f364e561
Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker
2021-11-21 15:55:52 +00:00
ba9a7b4a03
Fix broken link in readme
2021-11-21 14:58:07 +00:00
6fcc74a043
Add some instructions to Readme
2021-07-24 11:53:08 +01:00
e4b0d999cb
Minor doc updates
2021-07-18 20:45:08 +01:00
46f95f859d
Some doc updates
2021-07-17 13:07:09 +01:00
1b252d4bda
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
2021-05-23 11:59:46 +01:00
af0af41385
Add small readme
2021-05-21 03:39:10 +01:00
Leon Schuermann
Luke Wren