2f6e98335f
Add two new tests for IRQs-over-Zcmp, and fix a bug they found:
...
Interrupting the PC-setting step of a cm.popret (only) can sample the return target
as the exception return PC, which will cause the stack pointer adjust to be skipped
when returning from the IRQ. Fix this by making the PC-setting step uninterruptible
(note the PC-setting step is the instruction we execute first out of the group
of instructions specified in the Zc spec as being atomic wrt interrupts. This
does not itself imply that the PC-setting step is uninterruptible, it just
requires that when the PC-setting step retires, all following steps also retire.
However this is not sufficient given the special case logic that allows the jr
ra PC-setting step to execute before the final stack adjust as an optimisation.)
2023-11-03 21:12:21 +00:00
ef386f43c6
Disable zbs in sw_testcases compilation as a workaround for regression in GCC 12.3
2023-11-03 20:09:27 +00:00
8b301c5692
Silence useless linker rwx warning
2023-11-03 20:09:02 +00:00
31642b6d4a
Add amo_ops testcase
2023-04-01 08:47:29 +01:00
a536e3baa7
rvcpp sim: add A extension and M-mode traps
...
(now passes a lot of the Hazard3 tests)
2023-04-01 08:21:43 +01:00
26d699e18c
rvcpp simulator: fix bad regnum decode for c.slli outside of x8..x15
2023-04-01 06:02:45 +01:00
54f0a593c8
Fix +x permission of riscv-compliance/clean_all script
2023-04-01 04:42:15 +01:00
d8cc132a49
tb_cxxrtl Makefile: make synthesis depend on config headers
2023-04-01 04:41:39 +01:00
86fc4e3f2d
Update embench config and readme
2023-03-31 03:02:06 +01:00
ca40c077be
Capture JTAG bitbang log from most recent SMP debug test.
...
Regarding intermittent failure of SMP debug MemorySampleSingle test:
https://twitter.com/wren6991/status/1640153934445543426
Seems to be an OpenOCD issue, not a Hazard3 issue.
2023-03-31 02:16:23 +01:00
e89ab0d095
tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ
...
(i.e. single-core testbench). Avoids some odd behaviour with wide
assignment to single-bit wire from the CXXRTL harness.
2023-03-31 02:11:52 +01:00
5aee830ac0
Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH
...
(clean up fallout from Zc implementation -- ensure Readme instructions will get you to hello world)
2023-03-31 01:53:28 +01:00
a861a110c1
Update to the latest riscv-arch-test. This uses the new test
...
framework -- scripts are a little janky for now.
Note there is one test failure (cebreak-01) -- analysis shows
this is due to the reference vector expecting mtval to be set
informatively, whereas our implementation (legally) ties it
to zero. Non-mtval-related signature for that test is correct
so I'm saying this is fine.
2023-03-31 01:39:48 +01:00
18d3b03cc8
Fix rm of build directory in tb_cxxrtl/Makefile
2023-03-30 22:43:48 +01:00
97121afa91
Extend testbench to allow dumping/replaying JTAG to text file.
...
This allows debugging of tests that behave differently when VCD dumping
is enabled, due to the difference in execution speed.
(A couple of the SMP debug tests fail intermittently.)
2023-03-27 00:17:11 +01:00
c41fe0609b
Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests.
...
Fix a couple of minor test script issues.
2023-03-26 23:00:18 +01:00
94bd965e4e
Add script for running SMP debug tests
2023-03-24 18:45:11 +00:00
97509f548a
tb_cxxrtl Makefile: better support for building multiple tb configurations
2023-03-24 18:44:37 +00:00
cbb490da6a
Bump riscv-tests for hazard3 SMP debug test config changes
2023-03-24 18:11:08 +00:00
0dd6be181d
Fix up HwbpManual test in riscv-tests fork, and update debug test list
2023-03-24 00:28:02 +00:00
532e27dbc9
Bump riscv-tests for new debug and ISA tests. (Rebase of Hazard3 patches)
2023-03-23 23:32:28 +00:00
56586def8d
List Zcb/Zcmp in docs, and rebuild PDF
2023-03-22 03:04:16 +00:00
95faab6f2c
Add zcmp_irq_kill test
2023-03-22 02:44:03 +00:00
e98d7b41ea
Hook up power control signals on dual-core tb
2023-03-22 00:34:19 +00:00
8f461b63b4
Fix mvsa01/mva01s in rvcpp
2023-03-21 21:54:04 +00:00
410d002372
First pass at adding Zcmp to rvcpp
2023-03-21 21:28:49 +00:00
8e7e8f4008
Extend rvcpp ISA sim to cover RVC. Passes RV32IC compliance.
2023-03-21 19:38:46 +00:00
f702fe5352
Add test covering all pop instructions
2023-03-20 18:26:29 +00:00
d2adc6aad7
Add tests for mva01s/mvsa01
2023-03-20 16:05:07 +00:00
142b3a81ff
Add spike-extracted output to zcmp_push
2023-03-20 15:37:38 +00:00
ee6e03e0e6
Add beginnings of Spike-able zcmp_push test
2023-03-20 14:26:53 +00:00
3b2ddee06b
Fix push/pop frame format, fix source regnums for mvsa01/mva01s
2023-03-20 02:35:18 +00:00
7702c44288
Handle timeout in runtests
2023-03-20 01:32:16 +00:00
e966e832d2
First attempt at Zcmp
2023-03-20 00:19:23 +00:00
78d937e5c8
Yeet Zcb into core
2023-03-16 18:48:15 +00:00
a247c5cfc1
Bump riscv-tests fork: fix breakpoint test not setting tcontrol.mte when it is implemented.
2023-03-16 17:50:52 +00:00
7fbdb69328
Allow reconnecting to the testbench JTAG socket
2022-12-17 11:58:14 +00:00
8e7ffb040c
Comment typo
2022-12-17 11:39:47 +00:00
dff278ea05
Increase DTM idle cycle hint to 8 cycles -- see #6
2022-10-19 21:11:18 +01:00
0b18fae32e
Fix swapped MHARTID/MCONFIGPTR values in tb configs
2022-10-08 08:42:50 +01:00
874cb20910
Add config headers to tb_cxxrtl instead of using defparams in Makefile
2022-10-08 08:09:26 +01:00
a18c3018e1
Bump riscv-formal to head of hazard3 branch, not sure what happened there
2022-10-07 01:35:10 +01:00
624d39669d
Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.
2022-08-29 19:20:09 +01:00
da4097ecd8
Delay pwrup_req->pwrup_ack in tb
2022-08-29 14:55:11 +01:00
954bae5cf1
Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
2022-08-29 14:52:01 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
bf38d93d33
Remove references to AHB-Lite, describe buses as (a subset of) AHB5
2022-08-28 14:15:20 +01:00
a79c857d82
Bump riscv-tests: enable hardware instruction breakpoints in hardware tests
2022-08-27 17:05:02 +01:00
04f138ae0e
Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant
2022-08-23 00:05:30 +01:00
6e2076268c
Update CSR readability/writability tests for new CSRs
2022-08-22 08:50:57 +01:00
6e3799eed0
First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.
2022-08-22 08:47:03 +01:00
8b630d2ac6
Whoops I needed that constant
2022-08-10 01:00:47 +01:00
64dc31244e
Add top/bottom-half IRQ test
2022-08-10 00:09:13 +01:00
a44ff9b6f1
Add test for IRQ force array
2022-08-09 23:38:14 +01:00
5894ddf15c
Fix outdated expected output in irq_set_all_with_pri test
2022-08-08 18:44:58 +01:00
ad5fd24772
- Fix signal named priority, which is a keyword in SV
...
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
2e3d69e98f
Forgot to add expected output for preemption test
2022-08-07 22:08:50 +01:00
5e72ec8941
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test
2022-08-07 22:04:42 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
185194973f
Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
2022-08-06 23:02:08 +01:00
9787c604ad
Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
2022-07-30 17:31:53 +01:00
ee7d8e1947
Bump embench for script fixes/improvements
2022-07-07 18:29:37 +01:00
91be98f2da
Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
2022-07-06 23:53:11 +01:00
5a39d8b7e7
Track minstret and mcycle separately now that the model is cycle-accurate
2022-07-06 13:50:13 +01:00
5dfe5cb62b
Update rvpy to match current fastest config: stage 2 mul, single BTB entry on backward branches
2022-07-06 13:49:51 +01:00
b7d9defcf2
Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
2022-07-05 03:37:19 +01:00
27793b25a1
Rebase riscv-tests against upstream, and pick up new semihosting file io test
2022-07-04 00:45:20 +01:00
e44d2e6f9e
Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed
2022-07-03 23:34:12 +01:00
b1225c386c
Add missing 1port SBA change, and update example soc and bus compliance tb to reflect
2022-07-03 17:57:03 +01:00
9e15cd3485
Add standalone SBA-to-AHB shim, and make SBA off by default in the DM
2022-07-03 15:30:33 +01:00
d5cd3e0681
Add SBA patch-through to 1-core wrapper.
...
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
2022-07-03 15:17:44 +01:00
51bc26f8ac
First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
2022-07-03 00:25:47 +01:00
a7cb214501
Reduce ROM size in instruction_fetch_match: depth is more useful
2022-06-26 19:59:44 +01:00
5193dfe477
Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,
...
and enable it only on the bus compliance model checks. Trying to make
the solver's life easier in instruction_fetch_match.
2022-06-25 20:08:40 +01:00
8ef9d77be8
Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations.
...
Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)
2022-06-25 13:11:40 +01:00
d9389fb23e
Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
2022-06-16 01:42:28 +01:00
f8aad6d2f3
Fix some bugs, too tired to list them, look at the diff
2022-06-15 04:05:31 +01:00
0766ec6f8a
First pass at adding branch prediction
2022-06-15 02:05:46 +01:00
3703b1fc4c
Allow use of cir_flush_behind in frontend_match formal tb
2022-06-13 20:36:15 +01:00
e68d8a6cd6
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
2022-06-13 01:23:32 +01:00
23b4dbe7f3
Redesign fetch queue: 2x32 + 3x16 -> 6x16.
...
Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
2022-06-12 02:44:08 +01:00
d5a202e4a5
Add standalone frontend formal tb
2022-06-11 20:14:24 +01:00
d31b1708db
Make rvpy cycle-accurate enough to get the correct Dhrystone score
2022-06-09 01:34:37 +01:00
02b303b385
Remove stray old expected output file from sw_testcases dir
2022-06-03 17:20:49 +01:00
e2c9901701
Update readme for runtests
2022-05-30 01:12:16 +01:00
2cfe6aa90e
Add test to check MPRV/MPP behaviour when executing an MRET
2022-05-29 19:51:19 +01:00
f96a0ffb75
Add test for MPRV vs PMP
2022-05-29 19:06:04 +01:00
71eff7649d
Add PMP U-mode read/write permission test
2022-05-29 18:42:44 +01:00
c8afcdbb8f
Extend umode_wfi test to check U-mode WFI doesn't stall the processor if TW=0 or PMP X check fails
2022-05-29 17:42:15 +01:00
460fa0bb4a
Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.
2022-05-28 17:22:28 +01:00
66965ac073
Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
2022-05-28 15:36:21 +01:00
4090f4eb24
Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat
2022-05-28 15:01:27 +01:00
9e2f5df00a
Add testbench flag to propagate CPU return code to testbench return
2022-05-28 15:00:28 +01:00
81aec325bb
ecall from U-mode has a different mcause value than ecall from M-mode
2022-05-28 12:07:29 +01:00
632c61daba
Rebase debug tests, pick up two new tests (both pass)
2022-05-28 11:34:41 +01:00
f2876eb51f
Fix bad mepc reported after branching to a branch in a no-X address range
2022-05-27 22:47:04 +01:00
cd3125b6e5
Add new bus signals on instruction_fetch_match/tb.v
2022-05-27 21:48:45 +01:00
b655148148
Bump riscv-tests for better PMP disable fix
2022-05-27 21:36:54 +01:00
e208652ad7
Fix misa value in csr_id test
2022-05-26 00:48:12 +01:00
d7787942e9
Add two new tests to debug test list. Remainder are still non-applicable
2022-05-26 00:47:08 +01:00
Luke Wren
Scott Shawcroft