Luke Wren
|
6ef3503ef5
|
Add A bit to MISA, update docs
|
2021-12-07 05:10:20 +00:00 |
|
Luke Wren
|
93be227d8a
|
Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
|
2021-12-06 20:12:23 +00:00 |
|
Luke Wren
|
ed22d502fd
|
Fix bus stall getting stuck high when a bus fault exception isn't immediately accepted by the frontend
|
2021-12-06 19:28:21 +00:00 |
|
Luke Wren
|
50d3d5d3b3
|
Maintain AMO IRQ holdoff when transitioning from data phase to error phase, to prevent error possibly being flushed
|
2021-12-06 19:27:20 +00:00 |
|
Luke Wren
|
29c5c8ca7f
|
Fix AMO stall falling through when write data phase should proceed to error phase
|
2021-12-06 18:28:56 +00:00 |
|
Luke Wren
|
8bfc089660
|
Slightly more strict holdoff of IRQs on AMO
|
2021-12-06 18:13:43 +00:00 |
|
Luke Wren
|
0b3629564c
|
Don't apply shifter assertions to rotates
|
2021-12-06 18:12:23 +00:00 |
|
Luke Wren
|
ac9285846f
|
Timer struct in IO header
|
2021-12-06 17:16:21 +00:00 |
|
Luke Wren
|
9e7ea4adb6
|
Fix column width
|
2021-12-06 17:14:23 +00:00 |
|
Luke Wren
|
c57a80f358
|
Add AMO + timer testcase
|
2021-12-06 07:47:20 +00:00 |
|
Luke Wren
|
4c532240f8
|
Hold off IRQ when AMO is past the point of no return
|
2021-12-06 07:45:13 +00:00 |
|
Luke Wren
|
260491405a
|
Fix atomic instructions not asserting decode error when A extension is disabled
|
2021-12-06 07:28:50 +00:00 |
|
Luke Wren
|
cc38f46848
|
Fix AMO wdata valid left high when entering trap at just the right time
|
2021-12-06 07:28:50 +00:00 |
|
Luke Wren
|
d86b2849c9
|
Bump to latest version of riscv-arch-test
|
2021-12-06 02:18:48 +00:00 |
|
Luke Wren
|
1fa773c67a
|
Minimal RV32IMA + debug that fits on iCEBreaker. Not sure why area has regressed so much recently.
|
2021-12-05 02:16:54 +00:00 |
|
Luke Wren
|
12c79c0b41
|
Fix feature-flag for Zbs instructions in decoder
|
2021-12-05 02:05:35 +00:00 |
|
Luke Wren
|
9b9120960d
|
Fix missing RAW stall on sc.w succes result. Closing laptop again.
|
2021-12-05 01:05:01 +00:00 |
|
Luke Wren
|
723016a739
|
Update ISA support in Readme
|
2021-12-04 23:50:50 +00:00 |
|
Luke Wren
|
df658d86ff
|
First plausibly working AMOs. Add AMOs to instruction timings list
|
2021-12-04 23:44:22 +00:00 |
|
Luke Wren
|
5c098866f2
|
Sketch in AMO support
|
2021-12-04 20:46:39 +00:00 |
|
Luke Wren
|
34e57f0b14
|
Sketch in an AMO ALU
|
2021-12-04 18:52:41 +00:00 |
|
Luke Wren
|
a8933c332d
|
Fix illegal issue of pipelined exclusives on the bus, and document correct timings
|
2021-12-04 18:23:01 +00:00 |
|
Luke Wren
|
5e17bb805e
|
Add basic support for lr/sc instructions from the A extension
|
2021-12-04 15:02:31 +00:00 |
|
Luke Wren
|
c5d6be24f3
|
Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
|
2021-12-04 14:06:48 +00:00 |
|
Luke Wren
|
607147f280
|
Rewrite byte pick/sign-extend logic, preparing to handle more memops
|
2021-12-04 12:08:54 +00:00 |
|
Luke Wren
|
5db6c68c56
|
Update riscv-tests for correct misa.x value
|
2021-12-04 11:19:43 +00:00 |
|
Luke Wren
|
a988adfec8
|
Add RISC-V opcodes and memory operation codes for atomics
|
2021-12-04 11:16:24 +00:00 |
|
Luke Wren
|
52ba930638
|
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
|
2021-12-04 01:17:57 +00:00 |
|
Luke Wren
|
cd1b391714
|
More docs cleanup
|
2021-12-02 02:29:34 +00:00 |
|
Luke Wren
|
dfb07822ee
|
Remove UART DTM
|
2021-12-02 02:08:16 +00:00 |
|
Luke Wren
|
be6b2f3f76
|
Fix up DTMs to use byte addressing
|
2021-12-02 02:05:23 +00:00 |
|
Luke Wren
|
1ebccb7cce
|
Switch DM to use byte addresses on APB, not word addresses
|
2021-12-02 01:47:30 +00:00 |
|
Luke Wren
|
ebe87dce46
|
Reorganise CSR section of docs
|
2021-12-02 01:35:18 +00:00 |
|
Luke Wren
|
c5e85dea4c
|
Add mconfigptr CSR
|
2021-12-01 03:25:56 +00:00 |
|
Luke Wren
|
fad64bb6c9
|
Bump embench test submodule
|
2021-11-29 18:51:10 +00:00 |
|
Luke Wren
|
ba248c832a
|
init.S: also print out mcause when trapping an unhandled exception
|
2021-11-29 18:49:37 +00:00 |
|
Luke Wren
|
c8afb4ac33
|
Add option for fast high-half multiplies
|
2021-11-29 18:48:02 +00:00 |
|
Luke Wren
|
35c5e213c7
|
Bump embench for working benchmarks (except md5)
|
2021-11-29 00:59:14 +00:00 |
|
Luke Wren
|
d29bb13c4a
|
Replace SSH submodule URLs with HTTPS, oops
|
2021-11-28 22:26:29 +00:00 |
|
Luke Wren
|
94a3d43f27
|
Add Hazard3's registered marchid value to hdl and docs
|
2021-11-28 19:53:49 +00:00 |
|
Luke Wren
|
1aa9dbcddd
|
Fix comment typo in APB clock crossing
|
2021-11-28 17:40:57 +00:00 |
|
Luke Wren
|
0fafae1ab1
|
Regenerate PDF
|
2021-11-28 16:27:54 +00:00 |
|
Luke Wren
|
e7466ae4be
|
Move DM data0 CSR into the M-custom space, and document this
|
2021-11-28 15:52:52 +00:00 |
|
Luke Wren
|
9bf4d5105f
|
Describe possible debug topologies. Update pdf.
|
2021-11-28 09:01:23 +00:00 |
|
Luke Wren
|
4e2686d4ab
|
Finish documenting CSRs. Draw a debug topology diagram.
|
2021-11-28 08:17:23 +00:00 |
|
Luke Wren
|
76172cdade
|
Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
|
2021-11-28 06:33:35 +00:00 |
|
Luke Wren
|
79c29354d2
|
Update docs with bitmanip instructions
|
2021-11-28 03:16:45 +00:00 |
|
Luke Wren
|
800b21d2f5
|
Remove event feedback path (not logical path) in priority encoder
|
2021-11-28 02:19:01 +00:00 |
|
Luke Wren
|
ba27dd838f
|
Bump libfpga for correct bus error response from AHBL splitter in example SoC
|
2021-11-28 01:35:52 +00:00 |
|
Luke Wren
|
47ce2cc8ec
|
Add embench submodule, with configs for hazard3
|
2021-11-28 00:01:18 +00:00 |