a861a110c1
Update to the latest riscv-arch-test. This uses the new test
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framework -- scripts are a little janky for now.
Note there is one test failure (cebreak-01) -- analysis shows
this is due to the reference vector expecting mtval to be set
informatively, whereas our implementation (legally) ties it
to zero. Non-mtval-related signature for that test is correct
so I'm saying this is fine.
2023-03-31 01:39:48 +01:00
18d3b03cc8
Fix rm of build directory in tb_cxxrtl/Makefile
2023-03-30 22:43:48 +01:00
97121afa91
Extend testbench to allow dumping/replaying JTAG to text file.
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This allows debugging of tests that behave differently when VCD dumping
is enabled, due to the difference in execution speed.
(A couple of the SMP debug tests fail intermittently.)
2023-03-27 00:17:11 +01:00
c41fe0609b
Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests.
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Fix a couple of minor test script issues.
2023-03-26 23:00:18 +01:00
94bd965e4e
Add script for running SMP debug tests
2023-03-24 18:45:11 +00:00
97509f548a
tb_cxxrtl Makefile: better support for building multiple tb configurations
2023-03-24 18:44:37 +00:00
cbb490da6a
Bump riscv-tests for hazard3 SMP debug test config changes
2023-03-24 18:11:08 +00:00
0dd6be181d
Fix up HwbpManual test in riscv-tests fork, and update debug test list
2023-03-24 00:28:02 +00:00
43130a16e4
Fix readback of tdata2 and tinfo CSRs
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(Found due to latest riscv-openocd failing to enumerate triggers,
as it now scans tinfo before going for tdata1/mcontrol)
2023-03-23 23:33:39 +00:00
532e27dbc9
Bump riscv-tests for new debug and ISA tests. (Rebase of Hazard3 patches)
2023-03-23 23:32:28 +00:00
afcb6d283c
Missing default assignment
2023-03-23 10:57:50 +00:00
2905c1f820
Revert default for EXTENSION_ZC* to match docs in hazard3_config.vh
2023-03-23 03:07:09 +00:00
4a1d2b5008
Save a cycle on popret/popretz by executing the stack adjust after the jump
2023-03-23 02:50:34 +00:00
b074d370a6
Add Zcb/Zcmp instruction timings to docs
2023-03-23 01:12:38 +00:00
56586def8d
List Zcb/Zcmp in docs, and rebuild PDF
2023-03-22 03:04:16 +00:00
b58cde882a
Add link to Zcb/Zcmp specs
2023-03-22 02:48:56 +00:00
95faab6f2c
Add zcmp_irq_kill test
2023-03-22 02:44:03 +00:00
e98d7b41ea
Hook up power control signals on dual-core tb
2023-03-22 00:34:19 +00:00
fcbc4f6805
Fix regnum predecode of quadrant-2 RVC instructions with 5-bit regnums
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(regression caused by adding Zcb)
2023-03-21 23:04:17 +00:00
8f461b63b4
Fix mvsa01/mva01s in rvcpp
2023-03-21 21:54:04 +00:00
410d002372
First pass at adding Zcmp to rvcpp
2023-03-21 21:28:49 +00:00
8e7e8f4008
Extend rvcpp ISA sim to cover RVC. Passes RV32IC compliance.
2023-03-21 19:38:46 +00:00
670099e461
Fix trap address correction for Zcm instructions never firing
2023-03-20 18:38:28 +00:00
f702fe5352
Add test covering all pop instructions
2023-03-20 18:26:29 +00:00
d2adc6aad7
Add tests for mva01s/mvsa01
2023-03-20 16:05:07 +00:00
142b3a81ff
Add spike-extracted output to zcmp_push
2023-03-20 15:37:38 +00:00
ee6e03e0e6
Add beginnings of Spike-able zcmp_push test
2023-03-20 14:26:53 +00:00
7607dacfc4
Fix incorrect register order within stack frame for push/pop
2023-03-20 06:32:20 +00:00
8b73b1b927
Fix mvsa01 r2s decode, Dhrystone runs with Zcb now
2023-03-20 05:03:39 +00:00
c4e0c15160
Fix hookup of uop_atomic signal
2023-03-20 02:40:49 +00:00
3b2ddee06b
Fix push/pop frame format, fix source regnums for mvsa01/mva01s
2023-03-20 02:35:18 +00:00
7702c44288
Handle timeout in runtests
2023-03-20 01:32:16 +00:00
4aed15540d
Fix destination register for final uop of c.popretz
2023-03-20 01:31:49 +00:00
6b8923a623
Fix bad predecode of a0/a1 in mvsa01/mva01s.
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Fix bad pop load offset when extra sp adjust is nonzero.
2023-03-20 01:03:49 +00:00
e966e832d2
First attempt at Zcmp
2023-03-20 00:19:23 +00:00
99c0660c3e
Fix decompress of c.sb/c.sh
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Can now run CoreMark, Hazard3 sw testcases etc using core-v compiler
with Zcb enabled.
2023-03-16 20:36:36 +00:00
59edb2fc5f
Fix predecode of quadrant-00 compressed instruction rs1,
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to get correct rs1 for new Zbc byte/halfword load/store
2023-03-16 19:10:43 +00:00
78d937e5c8
Yeet Zcb into core
2023-03-16 18:48:15 +00:00
a247c5cfc1
Bump riscv-tests fork: fix breakpoint test not setting tcontrol.mte when it is implemented.
2023-03-16 17:50:52 +00:00
ba3c3138ef
Fix 3 minor Debug Module bugs:
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- sbdata0 should ignore writes when sbbusyerror or sberror is set
- All sbaddress0 writes and sbdata0 accesses should set
sbbusyerror if sbbusy is set
- sbaddress should not increment if access gets bus error
2023-03-03 13:24:31 +00:00
7101cccf3b
Cut through-path on reset halt request from debug module to bus
2023-01-19 13:47:02 +00:00
7fbdb69328
Allow reconnecting to the testbench JTAG socket
2022-12-17 11:58:14 +00:00
4c12f163bd
Add OrangeCrab 25F support ( #7 )
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* Add OrangeCrab 25F support
* Fix whitespace
Co-authored-by: Luke Wren <wren6991@gmail.com>
2022-12-17 11:49:41 +00:00
8e7ffb040c
Comment typo
2022-12-17 11:39:47 +00:00
52e665fb45
Remove unnecessary clear of sleep flags on bus error (which had a
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TODO asking if it should be removed) and add some more properties
in its place.
2022-11-05 18:50:41 +00:00
05cb6e7ee8
Rename confusingly named power control signal for allowing clock gate to shut during WFI/block sleep.
2022-11-05 18:26:56 +00:00
c81666177e
Remove FIXME about considering concurrent load/store and debug entry
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in calculating the privilege of load/stores. This is safe because it
is only the *current* debug mode state which affects load/stores,
and some new properties have been added to ensure load/stores can
not be in aphase at the point debug mode is entered/exited (which
is achieved by delaying the trap). Therefore there is no way for
debug entry to inadvertently boost the privilege of an executing
U-mode load/store.
Also rename a confusingly-named signal for an unsquashable bus
transfer in stage 2 that delays IRQ entry.
2022-11-05 18:19:14 +00:00
97bf2d06f6
Hold off first instruction fetch until pwrup_ack is first seen high
2022-11-05 14:58:47 +00:00
dff278ea05
Increase DTM idle cycle hint to 8 cycles -- see #6
2022-10-19 21:11:18 +01:00
1953773ca5
Don't gate exception into D-mode CSR write, as a valid CSR instruction
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writing to a valid CSR in D-mode is guaranteed not to raise any exception
(particularly the external data0 CSR is of interest)
2022-10-10 22:15:56 +01:00
Luke Wren
Scott Shawcroft