817a1ddfcb
Update src_only_app.mk to make overriding TB executable path easier
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(e.g. for running tests against rvcpp or an external simulator
2023-11-04 12:16:39 +00:00
2f6e98335f
Add two new tests for IRQs-over-Zcmp, and fix a bug they found:
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Interrupting the PC-setting step of a cm.popret (only) can sample the return target
as the exception return PC, which will cause the stack pointer adjust to be skipped
when returning from the IRQ. Fix this by making the PC-setting step uninterruptible
(note the PC-setting step is the instruction we execute first out of the group
of instructions specified in the Zc spec as being atomic wrt interrupts. This
does not itself imply that the PC-setting step is uninterruptible, it just
requires that when the PC-setting step retires, all following steps also retire.
However this is not sufficient given the special case logic that allows the jr
ra PC-setting step to execute before the final stack adjust as an optimisation.)
2023-11-03 21:12:21 +00:00
ef386f43c6
Disable zbs in sw_testcases compilation as a workaround for regression in GCC 12.3
2023-11-03 20:09:27 +00:00
8b301c5692
Silence useless linker rwx warning
2023-11-03 20:09:02 +00:00
31642b6d4a
Add amo_ops testcase
2023-04-01 08:47:29 +01:00
a536e3baa7
rvcpp sim: add A extension and M-mode traps
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(now passes a lot of the Hazard3 tests)
2023-04-01 08:21:43 +01:00
26d699e18c
rvcpp simulator: fix bad regnum decode for c.slli outside of x8..x15
2023-04-01 06:02:45 +01:00
54f0a593c8
Fix +x permission of riscv-compliance/clean_all script
2023-04-01 04:42:15 +01:00
d8cc132a49
tb_cxxrtl Makefile: make synthesis depend on config headers
2023-04-01 04:41:39 +01:00
86fc4e3f2d
Update embench config and readme
2023-03-31 03:02:06 +01:00
ca40c077be
Capture JTAG bitbang log from most recent SMP debug test.
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Regarding intermittent failure of SMP debug MemorySampleSingle test:
https://twitter.com/wren6991/status/1640153934445543426
Seems to be an OpenOCD issue, not a Hazard3 issue.
2023-03-31 02:16:23 +01:00
e89ab0d095
tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ
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(i.e. single-core testbench). Avoids some odd behaviour with wide
assignment to single-bit wire from the CXXRTL harness.
2023-03-31 02:11:52 +01:00
5aee830ac0
Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH
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(clean up fallout from Zc implementation -- ensure Readme instructions will get you to hello world)
2023-03-31 01:53:28 +01:00
a861a110c1
Update to the latest riscv-arch-test. This uses the new test
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framework -- scripts are a little janky for now.
Note there is one test failure (cebreak-01) -- analysis shows
this is due to the reference vector expecting mtval to be set
informatively, whereas our implementation (legally) ties it
to zero. Non-mtval-related signature for that test is correct
so I'm saying this is fine.
2023-03-31 01:39:48 +01:00
18d3b03cc8
Fix rm of build directory in tb_cxxrtl/Makefile
2023-03-30 22:43:48 +01:00
97121afa91
Extend testbench to allow dumping/replaying JTAG to text file.
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This allows debugging of tests that behave differently when VCD dumping
is enabled, due to the difference in execution speed.
(A couple of the SMP debug tests fail intermittently.)
2023-03-27 00:17:11 +01:00
c41fe0609b
Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests.
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Fix a couple of minor test script issues.
2023-03-26 23:00:18 +01:00
94bd965e4e
Add script for running SMP debug tests
2023-03-24 18:45:11 +00:00
97509f548a
tb_cxxrtl Makefile: better support for building multiple tb configurations
2023-03-24 18:44:37 +00:00
cbb490da6a
Bump riscv-tests for hazard3 SMP debug test config changes
2023-03-24 18:11:08 +00:00
0dd6be181d
Fix up HwbpManual test in riscv-tests fork, and update debug test list
2023-03-24 00:28:02 +00:00
43130a16e4
Fix readback of tdata2 and tinfo CSRs
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(Found due to latest riscv-openocd failing to enumerate triggers,
as it now scans tinfo before going for tdata1/mcontrol)
2023-03-23 23:33:39 +00:00
532e27dbc9
Bump riscv-tests for new debug and ISA tests. (Rebase of Hazard3 patches)
2023-03-23 23:32:28 +00:00
afcb6d283c
Missing default assignment
2023-03-23 10:57:50 +00:00
2905c1f820
Revert default for EXTENSION_ZC* to match docs in hazard3_config.vh
2023-03-23 03:07:09 +00:00
4a1d2b5008
Save a cycle on popret/popretz by executing the stack adjust after the jump
2023-03-23 02:50:34 +00:00
b074d370a6
Add Zcb/Zcmp instruction timings to docs
2023-03-23 01:12:38 +00:00
56586def8d
List Zcb/Zcmp in docs, and rebuild PDF
2023-03-22 03:04:16 +00:00
b58cde882a
Add link to Zcb/Zcmp specs
2023-03-22 02:48:56 +00:00
95faab6f2c
Add zcmp_irq_kill test
2023-03-22 02:44:03 +00:00
e98d7b41ea
Hook up power control signals on dual-core tb
2023-03-22 00:34:19 +00:00
fcbc4f6805
Fix regnum predecode of quadrant-2 RVC instructions with 5-bit regnums
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(regression caused by adding Zcb)
2023-03-21 23:04:17 +00:00
8f461b63b4
Fix mvsa01/mva01s in rvcpp
2023-03-21 21:54:04 +00:00
410d002372
First pass at adding Zcmp to rvcpp
2023-03-21 21:28:49 +00:00
8e7e8f4008
Extend rvcpp ISA sim to cover RVC. Passes RV32IC compliance.
2023-03-21 19:38:46 +00:00
670099e461
Fix trap address correction for Zcm instructions never firing
2023-03-20 18:38:28 +00:00
f702fe5352
Add test covering all pop instructions
2023-03-20 18:26:29 +00:00
d2adc6aad7
Add tests for mva01s/mvsa01
2023-03-20 16:05:07 +00:00
142b3a81ff
Add spike-extracted output to zcmp_push
2023-03-20 15:37:38 +00:00
ee6e03e0e6
Add beginnings of Spike-able zcmp_push test
2023-03-20 14:26:53 +00:00
7607dacfc4
Fix incorrect register order within stack frame for push/pop
2023-03-20 06:32:20 +00:00
8b73b1b927
Fix mvsa01 r2s decode, Dhrystone runs with Zcb now
2023-03-20 05:03:39 +00:00
c4e0c15160
Fix hookup of uop_atomic signal
2023-03-20 02:40:49 +00:00
3b2ddee06b
Fix push/pop frame format, fix source regnums for mvsa01/mva01s
2023-03-20 02:35:18 +00:00
7702c44288
Handle timeout in runtests
2023-03-20 01:32:16 +00:00
4aed15540d
Fix destination register for final uop of c.popretz
2023-03-20 01:31:49 +00:00
6b8923a623
Fix bad predecode of a0/a1 in mvsa01/mva01s.
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Fix bad pop load offset when extra sp adjust is nonzero.
2023-03-20 01:03:49 +00:00
e966e832d2
First attempt at Zcmp
2023-03-20 00:19:23 +00:00
99c0660c3e
Fix decompress of c.sb/c.sh
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Can now run CoreMark, Hazard3 sw testcases etc using core-v compiler
with Zcb enabled.
2023-03-16 20:36:36 +00:00
59edb2fc5f
Fix predecode of quadrant-00 compressed instruction rs1,
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to get correct rs1 for new Zbc byte/halfword load/store
2023-03-16 19:10:43 +00:00
Luke Wren