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  • 02b303b385 Remove stray old expected output file from sw_testcases dir Luke Wren 2022-06-03 17:20:49 +0100
  • ae2784d0ea PMP config: separate granularity config from hardwired region config. Give correct read value for G > 1. Luke Wren 2022-06-03 17:09:43 +0100
  • e0a9fb7312 Add option to hardwire PMP regions, or reduce their granularity Luke Wren 2022-06-03 01:18:33 +0100
  • b823132a6e Remove experimental description from U-mode and PMP. Add list of specifications. Luke Wren 2022-05-31 01:17:50 +0100
  • e2c9901701 Update readme for runtests Luke Wren 2022-05-30 01:12:16 +0100
  • 2cfe6aa90e Add test to check MPRV/MPP behaviour when executing an MRET Luke Wren 2022-05-29 19:51:19 +0100
  • f96a0ffb75 Add test for MPRV vs PMP Luke Wren 2022-05-29 19:06:04 +0100
  • 71eff7649d Add PMP U-mode read/write permission test Luke Wren 2022-05-29 18:42:44 +0100
  • c8afcdbb8f Extend umode_wfi test to check U-mode WFI doesn't stall the processor if TW=0 or PMP X check fails Luke Wren 2022-05-29 17:42:15 +0100
  • 460fa0bb4a Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented. Luke Wren 2022-05-28 17:22:28 +0100
  • 66965ac073 Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted Luke Wren 2022-05-28 15:36:21 +0100
  • 4090f4eb24 Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat Luke Wren 2022-05-28 15:01:27 +0100
  • 9e2f5df00a Add testbench flag to propagate CPU return code to testbench return Luke Wren 2022-05-28 15:00:28 +0100
  • 81aec325bb ecall from U-mode has a different mcause value than ecall from M-mode Luke Wren 2022-05-28 12:07:25 +0100
  • 632c61daba Rebase debug tests, pick up two new tests (both pass) Luke Wren 2022-05-28 11:34:41 +0100
  • f2876eb51f Fix bad mepc reported after branching to a branch in a no-X address range Luke Wren 2022-05-27 22:47:04 +0100
  • cd3125b6e5 Add new bus signals on instruction_fetch_match/tb.v Luke Wren 2022-05-27 21:48:45 +0100
  • b655148148 Bump riscv-tests for better PMP disable fix Luke Wren 2022-05-27 21:36:54 +0100
  • 0e462574b2 Move declaration of x_exec_pmp_fail to before its first use Luke Wren 2022-05-27 15:04:43 +0100
  • e208652ad7 Fix misa value in csr_id test Luke Wren 2022-05-26 00:48:12 +0100
  • d7787942e9 Add two new tests to debug test list. Remainder are still non-applicable Luke Wren 2022-05-26 00:46:52 +0100
  • 156fbcd019 Update behaviour of mstatus.mpp and mprv on mret to match priv-1.12 spec Luke Wren 2022-05-26 00:42:50 +0100
  • a17b941e38 Add U bit to misa, and fix some broken debug tests (no hazard3 bugs) Luke Wren 2022-05-25 23:46:23 +0100
  • 37f7588bad Fix hazard3 reset vector check value in debug tests Luke Wren 2022-05-25 21:45:36 +0100
  • 0efcf53fe5 Fix X PMP fail not suppressing load/store address phase. Fix PMP-failed load/store still passing on a data phase tag to stage 3. Fix WFI still pausing the core after a PMP X fail. Luke Wren 2022-05-25 16:18:01 +0100
  • 5be8835365 Add missing output to pmp_write_and_lock test Luke Wren 2022-05-25 15:34:28 +0100
  • 399dcf2cb9 Add test for U-mode X permissions Luke Wren 2022-05-25 13:47:16 +0100
  • e2b9a3b2f9 Fix two PMP-related bugs: 1. Generating PMP load/store exceptions when the instruction is not a load/store 2. Passing a PMP exec permission exception into M whilst the frontend is still starved, causing early taking of the exception and a bad mepc value. Luke Wren 2022-05-25 13:16:27 +0100
  • 7340765699 Add simple test to read, write and lock PMP registers Luke Wren 2022-05-25 02:05:24 +0100
  • 456810b09e Make vcd generation optional in runtests Luke Wren 2022-05-24 22:56:13 +0100
  • 64d9f4a111 Add tests for execution of mret and wfi in U mode Luke Wren 2022-05-24 22:14:20 +0100
  • 51750eb81d Add mstatus.tw to control U-mode WFI, and prevent mret execution in U-mode. Luke Wren 2022-05-24 21:12:44 +0100
  • 10ca3aec80 Add U-mode and PMP to readme Luke Wren 2022-05-24 20:40:00 +0100
  • 20f06c4a02 Build tb with 4 PMP regions by default Luke Wren 2022-05-24 20:06:57 +0100
  • 7cfc976ef2 Set U RWX permission on all of memory in the U CSR readability test Luke Wren 2022-05-24 19:58:12 +0100
  • c93228d13e Integrate PMP, and fix a couple of PMP bugs Luke Wren 2022-05-24 19:57:45 +0100
  • 4878a752d6 Plumb privilege state through to the bus ports Luke Wren 2022-05-24 18:24:34 +0100
  • cfed35b3da Fix the stupid printf warning on x86-64 as well as arm64 Luke Wren 2022-05-24 18:22:25 +0100
  • f033cde874 Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp Luke Wren 2022-05-24 17:30:24 +0100
  • ba81b533d2 Build core with U mode support for tb Luke Wren 2022-05-24 16:44:22 +0100
  • 0199f48087 Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented Luke Wren 2022-05-24 16:44:03 +0100
  • d62861159f First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python. Luke Wren 2022-05-24 16:06:28 +0100
  • 4ba3f7ceb9 Fix format warning in tb.cpp on arm64 Luke Wren 2022-05-24 16:17:30 +0100
  • ef35dc859d Add zicsr to march in makefiles Luke Wren 2022-05-24 16:17:07 +0100
  • 07d4b23a9a Add option to pass test list to runtests Luke Wren 2022-05-24 16:16:12 +0100
  • 2df1179994 Wire privilege through from core to bus masters. Tied off inside core. Luke Wren 2022-05-24 14:05:26 +0100
  • c0b5d73cbd Typo in for loop, surprised Yosys accepted this Luke Wren 2022-05-23 18:15:36 +0100
  • 5466c8131e Sketch in PMP implementation Luke Wren 2022-05-23 17:52:08 +0100
  • 06647b78c6 Fix IALIGN fault to trap on the control flow instruction instead of its target Luke Wren 2022-05-23 16:25:43 +0100
  • da244f54c3 Remove unused FAKE_DUALPORT option from regfile Luke Wren 2022-05-23 16:22:01 +0100
  • f849517202 Split CSR addresses into separate header file Luke Wren 2022-05-23 15:54:37 +0100
  • 5f4127948d Add a parameter to control register file reset, instead of the weird ifdef tree Luke Wren 2022-05-23 13:29:44 +0100
  • df0fd536eb Fix IRQ priority to match the priv spec Luke Wren 2022-05-23 12:56:37 +0100
  • 96a9ee18e1 Add IALIGN exception to non-RVC implementations Luke Wren 2022-05-23 12:47:48 +0100
  • c4e81922da Don't store bit 1 of mepc on non-RVC implementations Luke Wren 2022-05-23 12:27:07 +0100
  • 31061bd472 Add Zbkb to bitmanip tests and regenerate vectors Luke Wren 2022-05-21 17:15:46 +0100
  • 210dbeae64 Correct the name and operation of the brev8 (formerly rev.b) instruction Luke Wren 2022-05-20 15:28:18 +0100
  • a2582976fc Fix opcodes for zip/unzip, which are wrong in the bitmanip copy of the Zbkb spec, but correct in the crypto copy of that spec Luke Wren 2022-05-20 15:15:37 +0100
  • 4ffe007a84 Add zicsr to march in bitmanip tests, so it builds on newer toolchains Luke Wren 2022-05-20 01:32:21 +0100
  • 43e0b1d16a Implement Zbkb (untested) Luke Wren 2022-05-06 17:36:25 +0100
  • 4946248dc4 RVFI monitor: blank out instructions which experienced an instruction fetch fault. (previous monitor logic was ok when fetch faults weren't implemented. If the blanked instruction has side effects, these will break other test properties, which we would detect.) Luke Wren 2022-04-12 13:38:19 +0100
  • 8a61fe5243 Fix RVFI monitor assuming rs2 data is equivalent to store data (this used to be true, but was re-plumbed when optimising A extension implementation) Luke Wren 2022-04-12 13:27:53 +0100
  • 9e27db0884 Connect or tie off missing ports on RVFI wrapper Luke Wren 2022-04-12 13:27:03 +0100
  • 2c8f3974d0 Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i. Luke Wren 2022-04-09 13:49:16 +0100
  • 35651f52a7 Stronger property for correct predecode Luke Wren 2022-04-05 08:14:49 +0100
  • 20cf408632 Add fine (as well as coarse) register predecode, so that predecoded regnum can be used in bypass zeroing. Luke Wren 2022-04-04 20:16:19 +0100
  • 357efac66e Don't decode unnecessary bits in register predecode logic Luke Wren 2022-04-04 17:58:37 +0100
  • be80bd4c18 Radical opinion, we should have good performance by default, not bad Luke Wren 2022-04-02 17:53:22 +0100
  • 7dc5046505 Perf option for dedicated branch comparator Luke Wren 2022-04-02 11:40:47 +0100
  • 3c61fae9ef Remove the halfword fetch thing, was only really useful on RISCBoy Luke Wren 2022-04-02 10:54:16 +0100
  • 7b8fe43c1c Fix bad timing of predecoded regnum register update (thanks BMC) Luke Wren 2022-04-02 10:11:55 +0100
  • b80b09afe5 Typo -- fully encode all 128 possible IRQs Luke Wren 2022-03-15 09:01:55 +0000
  • b0b8703ea4 Support up to 128 IRQs Luke Wren 2022-03-13 09:27:43 +0000
  • 887c93dbf0 Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately) Luke Wren 2022-03-02 18:35:16 +0000
  • 96c69d0bb0 Cut in->out paths on debug halt/resume request Luke Wren 2022-03-01 21:14:49 +0000
  • 5aca1381ac Couple of fixups for rvpy which I forgot to commit at some point Luke Wren 2022-03-01 20:27:18 +0000
  • 8fbffbe133 Assign full width of fifo_valid in non-reset clause (cosmetic fix) Luke Wren 2022-02-24 12:00:27 +0000
  • 9ed99d8695 Use define to guard X-checks, instead of hot comments Luke Wren 2022-02-24 10:35:16 +0000
  • bf15b6c49f Fix forward reference to net Luke Wren 2022-01-18 23:02:26 +0000
  • 0a369efc06 Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus. Luke Wren 2021-12-18 15:41:05 +0000
  • 1b0e205f87 Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami Luke Wren 2021-12-18 14:51:46 +0000
  • d1b5f83b7a Beef up the ULX3S SoC again now that atomics aren't so disastrous for timing Luke Wren 2021-12-18 02:41:50 +0000
  • 6b8d4913ee Remove unnecessary mux of mw_result -> m_result Luke Wren 2021-12-18 01:34:25 +0000
  • 79fec3a2f5 Overload mw_result register for capturing AMO read data. Save some LCs. Luke Wren 2021-12-18 01:24:26 +0000
  • 28b53ef7b5 Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings. Luke Wren 2021-12-18 00:35:13 +0000
  • 7485269ddf Use the branch target adder for load/store addresses. Preparing for AMO ALU deletion Luke Wren 2021-12-17 22:36:40 +0000
  • a35739baf1 Fix AMO failing to loop on global monitor write fail Luke Wren 2021-12-17 17:04:22 +0000
  • a81d129961 Add exclusives monitor to testbench Luke Wren 2021-12-17 17:03:35 +0000
  • 5ab60422ad Add minimal multicore launch code Luke Wren 2021-12-17 01:24:11 +0000
  • 01d9617f9c Add multicore tb integration file Luke Wren 2021-12-17 00:41:23 +0000
  • 207566660d tb: handle both ports identically. Preparing for dual core Luke Wren 2021-12-17 00:04:00 +0000
  • 1fa0d4d442
         Create LICENSE Luke Wren 2021-12-13 23:40:14 +0000
  • b0d28447ab New license headers: DWTFPL -> Apache 2.0 Luke Wren 2021-12-13 23:23:24 +0000
  • f1cda26bcc Oops, try a little harder this time to ensure local monitor is cleared by sc.w errors _always_, even if lined up with trap entry stalls etc Luke Wren 2021-12-12 23:32:01 +0000
  • 25b44d04cf Add more properties wrt AMO. Fix awful bugs in interaction between AMOs and prior lr/sc, prior load/store exception, or IRQ which is asserted then deasserted. Fix sc with HRESP=1 HEXOKAY=1 not clearing the local monitor (not a bug, but unfriendly). Luke Wren 2021-12-12 23:24:25 +0000
  • 1697192c62 Fix cycle timing docs for sc.w: 2 cycles if next instruction is RAW-dependent. Luke Wren 2021-12-12 20:50:26 +0000
  • 88fea7acfa Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs. Luke Wren 2021-12-12 18:28:23 +0000
  • 719c21fec3 Add IRQ tests. Disable waves by default in runtests Luke Wren 2021-12-12 15:53:04 +0000
  • 9fb2af800f Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test Luke Wren 2021-12-12 14:58:50 +0000
  • a232833d81 Add CSR writable test Luke Wren 2021-12-12 14:23:34 +0000