Commit Graph

249 Commits

Author SHA1 Message Date
Luke Wren a9ba69f4dd Better default flags for CoreMark 2024-06-02 10:25:07 +01:00
Luke Wren a38981f989 Enable -Wextra for rvcpp 2024-06-02 10:18:40 +01:00
Luke Wren cbc2172930 rvcpp: Add Zcb support. Also fix -Wparentheses as sometimes it does find things 2024-06-02 10:15:57 +01:00
Luke Wren 3a747e1dde Disable zcmp in multilib-gen-gen for now, as it is still not supported in latest binutils release 2024-06-01 18:24:06 +01:00
Luke Wren b883be3c20 Update multilib-gen-gen for GCC14 extensions: Zicond, Zcmp, Zcb. Hopefully handle the Zca vs C thing gracefully. 2024-06-01 18:01:09 +01:00
Luke Wren 7430523c45 Update .gitignore in riscv-tests to ignore output of debug tests 2024-06-01 15:53:53 +01:00
Luke Wren 6da0e12bbd Merge latest riscv-tests: updates for debug + ISA tests.
Add a list of excluded tests, with reasons, to run-debug-tests.sh
2024-05-29 14:03:17 +01:00
Luke Wren d239de803c Do not rely on environment variables for any intra-project paths
It's no longer necessary to source `sourceme` before running any
of the project Makefiles.
2024-05-27 16:53:06 +01:00
Luke Wren 141da55507 tb: remove the WIDE_TIMER_IRQ flag in favour of always having the same tb interface. Second timer IRQ is ignored in single-core tb. Also, fix hmaster not being connected, which Verilator complains about. 2024-05-27 12:24:54 +01:00
Luke Wren 5b31e26790 tb Makefile: use clang++-16 explicitly, because clang++-18 (now default on Ubuntu 24.04) has a >20x compile time regression 2024-05-27 11:06:50 +01:00
Luke Wren c550d79047 Debug tests: workaround recent GCC requiring Zicsr set for CSR instructions 2024-05-12 13:33:14 +01:00
Luke Wren a6558e554a Set misa.b when all of Zba, Zbb and Zbs are enabled.
(The B extension has now been ratified as this combination of extensions.)
2024-05-11 12:13:35 +01:00
Luke Wren 6db1edc675 Add dummy h3.msleep CSR to rvcpp 2024-05-11 11:02:01 +01:00
Luke Wren a84742abd4 Fix mstatus.mie still being respected when privilege is less than M.
Extend umode_wfi testcase to cover this, and in particular to check
that when entering U-mode with IRQs pending, the IRQs execute before any
exceptions occurring as a result of the U-mode instructions.
2024-05-11 10:49:13 +01:00
Luke Wren 194c9a9052 Implement WFI in rvcpp. The umode_wfi test still does not pass, because it relies on a bug in Hazard3 (mstatus.mie disables IRQs in U-mode as well as M-mode, but is supposed to be ignored in U-mode). 2024-04-27 20:48:30 +01:00
Luke Wren 78260e86e7 rvcpp: parameterise number of PMP regions, and set to match tb default. Fix region locking. Mask pmpaddr to 30 bits, to match Hazard3 32-bit physical address space. 2024-04-27 19:57:18 +01:00
Luke Wren ebe5a44454 rvcpp: fix up PMP address mask for all-ones pmpaddr, and raise instruction fault on instruction stradding two PMP regions, like the hardware 2024-04-27 19:34:17 +01:00
Luke Wren 7d370292b0 Fix transposition of RWX <-> XWR in PMP implementation.
None of upstream tests used for Hazard3 seem to cover X != R. The
Hazard3 tests covered this case, but the header file for the tests has
the same mistake. Fix the header.
2024-04-27 13:52:43 +01:00
Luke Wren fce1c087d4 Add basic PMP implementation to rvcpp. Seems like the RWX vs XWR order might be transposed in both the hardware and the tests 2024-04-27 13:38:10 +01:00
Luke Wren 117c52e7b1 rvcpp: fix handling of CSR instructions which both read and write 2024-04-27 13:30:34 +01:00
Luke Wren a313493371 Add timer and soft IRQ support to rvcpp. Relevant sw_testcases now pass. 2024-03-22 00:52:01 +00:00
Luke Wren b1be56fe94 Clean up rvcpp file structure 2024-03-21 23:27:01 +00:00
Luke Wren b473575b7e rvcpp: correctly model memory access faults. relevant sw_testcases now pass.
Also, grab the special-case core RAM change from the Sv32 fork, for better performance
2024-03-21 00:33:54 +00:00
Luke Wren fd584ea24b Add Xh3bextm instructions to rvcpp, and rename xh3b test to xh3bextm 2024-03-20 23:45:30 +00:00
Luke Wren 8cbf5fceee rvcpp: fix busted RMW CSR logic, fix ordering of CSR write vs update, csr_mcycle testcase now passes 2024-03-20 01:37:04 +00:00
Luke Wren 55504fa8f3 Add support for Zba, Zbb, Zbc, Zbs, Zbkb to rvcpp. Passes tests 2024-03-20 01:06:13 +00:00
Luke Wren e1bb341876 Add support for testcase return code propagation to rvcpp.
Hook up mtvec in bitmanip testcases to exit sim when exception taken.
2024-03-20 01:05:24 +00:00
Luke Wren 32f65fb142 Expand rvcpp counter CSR implementation 2024-03-19 08:44:24 +00:00
Luke Wren 9bb6ed4a3e Update tb for new cxxrtl debug_info API 2024-03-17 05:32:47 +00:00
Luke Wren 404aeead92 Additional assertions for cm.mvsa01/mva01s IRQ testcase 2024-03-17 05:04:59 +00:00
Luke Wren a693cdd632 Fix up cxxrtl include paths for new yosys 2023-12-12 19:00:26 +00:00
Luke Wren d4212f8976 Limit multilib-gen-gen to more-useful ISA combinations 2023-11-30 05:32:39 +00:00
Luke Wren e8b4578b40 Add test for cm.mvsa01/cm.mva01s tearing on IRQs 2023-11-04 14:08:07 +00:00
Luke Wren 10a6c2616a Add utility script for generating long multilib configure lines when building riscv-gnu-toolchain 2023-11-04 12:27:31 +00:00
Luke Wren 514ab0bb32 Typo in zcmp_irq_kill tests 2023-11-04 12:24:45 +00:00
Luke Wren 9955807520 Check in missing xoroshiro header from amo_ops testcase 2023-11-04 12:17:04 +00:00
Luke Wren 817a1ddfcb Update src_only_app.mk to make overriding TB executable path easier
(e.g. for running tests against rvcpp or an external simulator
2023-11-04 12:16:39 +00:00
Luke Wren 2f6e98335f Add two new tests for IRQs-over-Zcmp, and fix a bug they found:
Interrupting the PC-setting step of a cm.popret (only) can sample the return target
as the exception return PC, which will cause the stack pointer adjust to be skipped
when returning from the IRQ. Fix this by making the PC-setting step uninterruptible

(note the PC-setting step is the instruction we execute first out of the group
of instructions specified in the Zc spec as being atomic wrt interrupts. This
does not itself imply that the PC-setting step is uninterruptible, it just
requires that when the PC-setting step retires, all following steps also retire.
However this is not sufficient given the special case logic that allows the jr
ra PC-setting step to execute before the final stack adjust as an optimisation.)
2023-11-03 21:12:21 +00:00
Luke Wren ef386f43c6 Disable zbs in sw_testcases compilation as a workaround for regression in GCC 12.3 2023-11-03 20:09:27 +00:00
Luke Wren 8b301c5692 Silence useless linker rwx warning 2023-11-03 20:09:02 +00:00
Luke Wren 31642b6d4a Add amo_ops testcase 2023-04-01 08:47:29 +01:00
Luke Wren a536e3baa7 rvcpp sim: add A extension and M-mode traps
(now passes a lot of the Hazard3 tests)
2023-04-01 08:21:43 +01:00
Luke Wren 26d699e18c rvcpp simulator: fix bad regnum decode for c.slli outside of x8..x15 2023-04-01 06:02:45 +01:00
Luke Wren 54f0a593c8 Fix +x permission of riscv-compliance/clean_all script 2023-04-01 04:42:15 +01:00
Luke Wren d8cc132a49 tb_cxxrtl Makefile: make synthesis depend on config headers 2023-04-01 04:41:39 +01:00
Luke Wren 86fc4e3f2d Update embench config and readme 2023-03-31 03:02:06 +01:00
Luke Wren ca40c077be Capture JTAG bitbang log from most recent SMP debug test.
Regarding intermittent failure of SMP debug MemorySampleSingle test:
https://twitter.com/wren6991/status/1640153934445543426

Seems to be an OpenOCD issue, not a Hazard3 issue.
2023-03-31 02:16:23 +01:00
Luke Wren e89ab0d095 tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ
(i.e. single-core testbench). Avoids some odd behaviour with wide
assignment to single-bit wire from the CXXRTL harness.
2023-03-31 02:11:52 +01:00
Luke Wren 5aee830ac0 Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH
(clean up fallout from Zc implementation -- ensure Readme instructions will get you to hello world)
2023-03-31 01:53:28 +01:00
Luke Wren a861a110c1 Update to the latest riscv-arch-test. This uses the new test
framework -- scripts are a little janky for now.

Note there is one test failure (cebreak-01) -- analysis shows
this is due to the reference vector expecting mtval to be set
informatively, whereas our implementation (legally) ties it
to zero. Non-mtval-related signature for that test is correct
so I'm saying this is fine.
2023-03-31 01:39:48 +01:00