Luke Wren
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1fa773c67a
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Minimal RV32IMA + debug that fits on iCEBreaker. Not sure why area has regressed so much recently.
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2021-12-05 02:16:54 +00:00 |
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Luke Wren
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12c79c0b41
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Fix feature-flag for Zbs instructions in decoder
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2021-12-05 02:05:35 +00:00 |
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Luke Wren
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9b9120960d
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Fix missing RAW stall on sc.w succes result. Closing laptop again.
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2021-12-05 01:05:01 +00:00 |
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Luke Wren
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723016a739
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Update ISA support in Readme
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2021-12-04 23:50:50 +00:00 |
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Luke Wren
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df658d86ff
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First plausibly working AMOs. Add AMOs to instruction timings list
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2021-12-04 23:44:22 +00:00 |
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Luke Wren
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5c098866f2
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Sketch in AMO support
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2021-12-04 20:46:39 +00:00 |
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Luke Wren
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34e57f0b14
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Sketch in an AMO ALU
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2021-12-04 18:52:41 +00:00 |
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Luke Wren
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a8933c332d
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Fix illegal issue of pipelined exclusives on the bus, and document correct timings
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2021-12-04 18:23:01 +00:00 |
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Luke Wren
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5e17bb805e
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Add basic support for lr/sc instructions from the A extension
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2021-12-04 15:02:31 +00:00 |
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Luke Wren
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c5d6be24f3
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Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
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2021-12-04 14:06:48 +00:00 |
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Luke Wren
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607147f280
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Rewrite byte pick/sign-extend logic, preparing to handle more memops
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2021-12-04 12:08:54 +00:00 |
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Luke Wren
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5db6c68c56
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Update riscv-tests for correct misa.x value
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2021-12-04 11:19:43 +00:00 |
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Luke Wren
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a988adfec8
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Add RISC-V opcodes and memory operation codes for atomics
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2021-12-04 11:16:24 +00:00 |
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Luke Wren
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52ba930638
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Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
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2021-12-04 01:17:57 +00:00 |
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Luke Wren
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cd1b391714
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More docs cleanup
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2021-12-02 02:29:34 +00:00 |
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Luke Wren
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dfb07822ee
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Remove UART DTM
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2021-12-02 02:08:16 +00:00 |
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Luke Wren
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be6b2f3f76
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Fix up DTMs to use byte addressing
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2021-12-02 02:05:23 +00:00 |
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Luke Wren
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1ebccb7cce
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Switch DM to use byte addresses on APB, not word addresses
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2021-12-02 01:47:30 +00:00 |
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Luke Wren
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ebe87dce46
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Reorganise CSR section of docs
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2021-12-02 01:35:18 +00:00 |
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Luke Wren
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c5e85dea4c
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Add mconfigptr CSR
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2021-12-01 03:25:56 +00:00 |
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Luke Wren
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fad64bb6c9
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Bump embench test submodule
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2021-11-29 18:51:10 +00:00 |
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Luke Wren
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ba248c832a
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init.S: also print out mcause when trapping an unhandled exception
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2021-11-29 18:49:37 +00:00 |
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Luke Wren
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c8afb4ac33
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Add option for fast high-half multiplies
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2021-11-29 18:48:02 +00:00 |
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Luke Wren
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35c5e213c7
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Bump embench for working benchmarks (except md5)
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2021-11-29 00:59:14 +00:00 |
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Luke Wren
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d29bb13c4a
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Replace SSH submodule URLs with HTTPS, oops
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2021-11-28 22:26:29 +00:00 |
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Luke Wren
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94a3d43f27
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Add Hazard3's registered marchid value to hdl and docs
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2021-11-28 19:53:49 +00:00 |
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Luke Wren
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1aa9dbcddd
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Fix comment typo in APB clock crossing
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2021-11-28 17:40:57 +00:00 |
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Luke Wren
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0fafae1ab1
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Regenerate PDF
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2021-11-28 16:27:54 +00:00 |
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Luke Wren
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e7466ae4be
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Move DM data0 CSR into the M-custom space, and document this
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2021-11-28 15:52:52 +00:00 |
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Luke Wren
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9bf4d5105f
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Describe possible debug topologies. Update pdf.
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2021-11-28 09:01:23 +00:00 |
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Luke Wren
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4e2686d4ab
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Finish documenting CSRs. Draw a debug topology diagram.
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2021-11-28 08:17:23 +00:00 |
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Luke Wren
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76172cdade
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Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
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2021-11-28 06:33:35 +00:00 |
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Luke Wren
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79c29354d2
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Update docs with bitmanip instructions
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2021-11-28 03:16:45 +00:00 |
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Luke Wren
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800b21d2f5
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Remove event feedback path (not logical path) in priority encoder
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2021-11-28 02:19:01 +00:00 |
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Luke Wren
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ba27dd838f
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Bump libfpga for correct bus error response from AHBL splitter in example SoC
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2021-11-28 01:35:52 +00:00 |
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Luke Wren
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47ce2cc8ec
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Add embench submodule, with configs for hazard3
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2021-11-28 00:01:18 +00:00 |
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Luke Wren
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14a4f1a281
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Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
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2021-11-27 17:19:41 +00:00 |
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Luke Wren
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6f1a10724b
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Add bitmanip test vector generation script
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2021-11-26 23:34:06 +00:00 |
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Luke Wren
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5d093487b7
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Update README
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2021-11-26 23:33:46 +00:00 |
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Luke Wren
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1bb7e33b69
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Fix alignment of heap_ptr in init.S. Small ALU cleanup
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2021-11-26 02:59:50 +00:00 |
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Luke Wren
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7410c52aac
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Update readme
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2021-11-26 02:09:39 +00:00 |
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Luke Wren
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8398d7ecb6
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Hook up Zb* extension params on iCEBreaker FPGA
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2021-11-26 01:44:57 +00:00 |
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Luke Wren
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8bcec11c80
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Couple more silly mistakes
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2021-11-26 01:30:13 +00:00 |
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Luke Wren
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41eeb90c7d
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Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
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2021-11-26 01:29:47 +00:00 |
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Luke Wren
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998f3fdeb7
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Clean up silly mistakes
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2021-11-26 00:55:57 +00:00 |
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Luke Wren
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58c20a39d0
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First pass at implementing bitmanip. Breaks CXXRTL. Ooop
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2021-11-25 23:30:35 +00:00 |
Luke Wren
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ed6b6a3660
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Cleanup order of declaration/use of a couple of wires
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2021-11-25 15:16:59 +00:00 |
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Luke Wren
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2aac3d4f91
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Add attempt at CPU backend diagram
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2021-11-23 22:14:55 +00:00 |
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Luke Wren
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e352715fdf
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Fix IO decode in openocd/tb.cpp
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2021-11-23 22:12:51 +00:00 |
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Luke Wren
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49462a8642
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Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh
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2021-11-23 22:11:50 +00:00 |