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356 Commits

Author SHA1 Message Date
Sven ed47c5c24c
Update internal to 1.1.37_preview (#254) 
* update internal to V1.1.37

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

* Update VSimulator V6.4.9 for linux x86_64

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2022-01-10 01:56:00 +08:00
liyuenan 7c63ba621e
Map OneHot & unit test (#258) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2022-01-05 22:04:49 +08:00
Goose Bomb 8e4ab68213
Fix warnings relating to inheritance (#256) 
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test

* Fix warnings relating to inheritance
 2022-01-04 14:35:17 +08:00
chxin66 eecbe264b6
Add a unit_test for div_uint8 (#251) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-30 13:31:30 +08:00
liyuenan 6275f84575
Fix the conflict for previous two commits (#253) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-29 15:38:42 +08:00
chxin66 cea11422b8
Added RNNCell & unit test (#249) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-29 11:08:24 +08:00
liyuenan 75d39e2cfd
Support layout inference for transpose (#250) 
Added interface GetProdeucerOp(tensor) in Graph


Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-29 11:06:28 +08:00
Zongwu.Yang aed3a48248
Add layout inference and unit test for BatchNorm (#243) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-12-22 09:47:57 +08:00
Sven e42faad710
Fix build issue if 40BIT_VA enabled (#240) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-12-17 15:00:14 +08:00
Sven 321a53fd2a
Support single static-library for libtim-vx.a (#237) 
Fix external ovxlib build failure, and change install dir to CMAKE_INSTALL_LIBDIR

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-15 22:23:32 +08:00
liyuenan 2c38f89d06
Catch the correct output when output has consumer (#239) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-12-15 09:54:54 +08:00
chxin66 1f85d21558
mapped signal frame & unit test (#234) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-09 10:33:40 +08:00
chxin66 dc31091db5
mapped groupedconv1d & unit test (#233) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-12-06 19:20:13 +08:00
Zongwu.Yang bd496219c8
Add quantize, dequantize, requantize test (#232) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-12-02 15:40:41 +08:00
Antkillerfarm b38bd41933
add DataLayout::IcOcWH for TVM usage (#231) 2021-11-30 21:33:14 +08:00
Sven 62a33ecfde
Install libtim-vx.so to lib64 if build for aarch64 (#225) 
* Install libtim-vx.so to lib64 if build for aarch64

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-11-24 15:18:29 +08:00
Sven bc42f7987c
Fix build if lowlevel driver doesn't support DMABuffer fd (#224) 
* Fix build if lowlevel driver doesn't support DMABuffer fd

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-11-23 11:34:03 +08:00
chxin66 8b1ec74f07
support DMAbuffer (#214) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-11-21 22:46:20 +08:00
Zongwu.Yang c90efe70c5
Refine Lite API (#221) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-11-19 20:30:26 +08:00
Sven 81e28e8b0d
Update license for nbg_parser.c (#215) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-11-11 14:07:10 +08:00
chxin66 516a914c73
Mapped Erf operation & unit tests (#211) 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>

Co-authored-by: Chen Xin <jack.chen@verisilicon.com>
 2021-11-10 20:07:06 +08:00
Zongwu.Yang d019a76db5
Add function for lite driver handle (#209) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-11-10 20:05:31 +08:00
Antkillerfarm 214cbe5874
add Global Pool2d & Adaptive Pool2d (#210) 2021-11-09 20:25:02 +08:00
Sven 23ec5e9da5
Refine op status (#208) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-11-09 13:10:09 +08:00
Zhouheng Zheng 68b5acbe7c
Fix layout inference bug for resize layer(#205) 
Co-authored-by: zhouheng.zheng <zhouheng.zheng@ouotlook.com>
 2021-11-04 19:13:21 +08:00
Kee c9086e0afe
Update Div OP - add scale param (#203) 
Update Div OP - add scale param
 2021-11-04 10:44:52 +08:00
chxin66 e4cc133d36
Add SVDF support - only FLOAT32 supported 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-10-29 16:19:15 +08:00
Sven f8846e701e
Update CMakeLists.txt (#187) 
Enable build tim-vx as dynamic-library by default will be more friendly for other repo such as tflite-vx-delegate.
 2021-10-12 19:50:55 +08:00
Goose Bomb 914e280209
Refactor CMake build system (#184) 
* Remove unnecessary compiler flags

* Refactor CMakeLists.txt

* Tweak CMakeLists.txt for libtim_internal

* Tweak CMakeLists.txt for libtim-vx

* Make TIM_VX_ENABLE_TEST defaults to OFF

* Eliminate usage of include_directories

* Fix CI unit test
 2021-10-12 10:44:49 +08:00
Kainan Cha d7900b9de4 Add sample to run NBG 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-09-27 17:21:04 +08:00
Kainan Cha 404817db1f Remove unused directories from CMake 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-09-24 22:02:11 +08:00
Kainan Cha 81cc868b6c Update internal to 1.1.34 
SHA: 67f1e

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-09-24 21:36:18 +08:00
xiang.zhang 994f8a9c2a Fixed layout inference crash(assert) if node have multiply output 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-09-16 10:55:29 +08:00
xiang.zhang 374841cbd9 Fix build error with Android NDK 
Verified with android ndk r22b

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-09-09 12:56:01 +08:00
Chen Xin 633075f689 delete Non-approximate option, recommend to use 
the approximate option

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-09-07 22:44:57 +08:00
Chen Xin 6f2e92ffa6 Add shuffle_channel support & test for tim::vx 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-09-07 22:44:57 +08:00
xiang.zhang b226777ad3 Fix average_pool unit test failure: precesion issue 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-08-30 19:53:01 +08:00
Chen Xin eb28f8b3ed move ArraysMatch function into src/tim/vx/test_utils.h 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-08-26 16:28:08 +08:00
Chen Xin 3d64cfc4ef add avgpool test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-08-26 16:28:08 +08:00
chxin66 5e09e98c1a
Add Gelu support for tim::vx (#153) 
* Add map for Gelu

Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-08-17 20:37:12 +08:00
jing.tang a364c3eafb add Swish op 2021-08-16 19:30:14 +08:00
Jing.Deng 4d53e042c8 add the customer case.(only include wrong case) 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-08-13 11:57:57 +08:00
xiang.zhang e27e15925c Add unidirectional sequence lstm support 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-08-09 13:43:33 +08:00
xiang.zhang d4a13e18a9 Minor refinement: use tensor pointer after check 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-08-04 11:31:26 +08:00
jing.tang f0d4118f87 Update ops doc for internal 1.1.32.1 2021-08-04 11:30:45 +08:00
Kainan Cha 6a949bb315 Add align_corners support for SpatialTransformer 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-08-03 10:52:51 +08:00
Kainan Cha 4d4bc08d6a Update internal to 1.1.32.1 
SHA: 215204

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-08-02 16:19:21 +08:00
zhao.xia 8fb3a7e6fb Remove customer test 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-07-30 11:19:32 +08:00
Your Name 70c427256d Fix groupconv2d pad parameter 2021-07-29 17:23:45 +08:00
Chen Xin a09ffe8b98 addn unit test 
Signed-off-by: Chen Xin <jack.chen@verisilicon.com>
 2021-07-22 10:41:25 +08:00
Jing.Deng 3a0bc515a1 add unit test for customer use case 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-07-22 09:55:48 +08:00
Jing.Deng f9cb2dbe45 fix the axis issue about perchannel quantized conv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-07-09 14:56:39 +08:00
yuenan.li 2f8f87d1cb Add Clone API for SpatialTrasformer 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 17:34:57 +08:00
zhao.xia 8aa11f5f29 Support SpatialTransformer 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-07-06 12:56:28 +08:00
yuenan.li 29f1efc492 add API 'Clone' to tim_vx op and support default layout inference 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-07-06 12:29:18 +08:00
zhao.xia 21ecf5262e Add map for Matmul 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-29 16:06:35 +08:00
zhao.xia 3fa2bf519a Add map for moments 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-29 15:58:51 +08:00
Kainan Cha 3c59694025 Update internal to 1.1.32 
SHA: 9aa0b0f

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-29 11:25:36 +08:00
yuenan.li 98b9759663 Refine arg in layout inference 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-29 11:24:28 +08:00
Jing.Deng be066fb9bd add float32, uint8 and int8 unit_tests for transposeConv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-24 21:27:16 +08:00
yuenan.li 1e42cfd668 Support layout inference for nbg 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-24 17:28:02 +08:00
yuenan.li f8f2c6d519 Fix layout inference for traspose convolution 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-21 17:14:16 +08:00
Jing.Deng 1672ef99ed add uint8 and int8 unit_test for depthwise convolution. modify the api of 'conv2d' constructor 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-18 14:10:11 +08:00
xiang.zhang 574c036a69 Fix FullyConnect layer crash 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-06-16 16:05:16 +08:00
Robert Kalmar 64989c6b4a Added option to use extenal OVXLIB library 
Signed-off-by: Robert Kalmar <robert.kalmar@nxp.com>
 2021-06-16 15:00:35 +08:00
Jing.Deng c77217745f add float32 unit_test for depthwise convolution 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-13 12:03:13 +08:00
Jing.Deng e2c52d2d8a add int8 quantized unit_test for conv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-10 11:38:26 +08:00
Kainan Cha a7d962ac5c Minor fixup for unit test case naming 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-09 10:51:26 +08:00
zhao.xia 0ed1e8947f Add new APIs for conv, deconv and fc 
The new apis remvoe weights, oc_count and ksize.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-07 21:48:13 +08:00
Jing.Deng 8d35c4dd7a add uint8 quantized unit_test for conv2d 
Signed-off-by: Jing.Deng <Jing.Deng@verisilicon.com>
 2021-06-07 13:30:43 +08:00
Kainan Cha 9e10d88fc7 Update OP ReadMe 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-07 12:39:42 +08:00
zhao.xia f59f26412b Add GroupedConv2d 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-04 16:53:25 +08:00
zhao.xia 353feca56a Add tile 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 18:29:32 +08:00
zhao.xia bd9c5df70a Add pad parameter to pool2d 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 16:28:42 +08:00
zhao.xia 748658e47d Add Unstack 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 16:24:31 +08:00
Kainan Cha 89c7b27693 Update README 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-03 12:10:24 +08:00
zhao.xia 8a15abf12b Add ScatterND 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-06-03 11:22:58 +08:00
Kainan Cha 39bd5ddd32 Add support for Linear Activation 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-02 17:10:57 +08:00
Kainan Cha 94fe57489b Update OP readme 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-06-02 01:03:20 +08:00
yuenan.li 1f08618403 Supprt layout inference for Operations 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-06-02 00:53:11 +08:00
zhao.xia 26948d6646 Rename Unmaxpool2d to MaxUnpool2d 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-31 12:48:51 +08:00
Nightingale 9c60671031
Add map for UnMaxpool2d (#83) 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-28 17:09:26 +08:00
Kainan Cha 18a928ee69 Add Op MaxpoolWithArgmax 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-27 18:59:35 +08:00
liyuenan fae5cede7a
Support layout inference for ops (#77) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-27 10:33:44 +08:00
zhao.xia a1ba85691a Add map for LogSoftmax 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-26 11:37:16 +08:00
zhao.xia 37f686c34d Remove DownScaleSizeRounding type 
Use RoundType instead of DownScaleSizeRounding.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-25 16:48:50 +08:00
zhao.xia 260b0c3f2d Update Resize1d cases 
Fix resize1d uint8 bilinear case to float.
Add new uint8 resize nearest case.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-25 13:55:30 +08:00
Kainan Cha 2ff1f5fed1 Update operation README 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-25 13:52:56 +08:00
Sven df77848c34
Refine unit test case name (#70) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-25 11:19:42 +08:00
Nightingale f90f3eedfd
Add map for Resize1d (#69) 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-25 10:27:23 +08:00
Kainan Cha d0dadbc0fb Add support for FloorDiv 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-25 01:20:43 +08:00
Kainan Cha 804e068374 Move conv2d_test.cc to ops/ directory 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-25 00:39:41 +08:00
Nightingale 33fd1f0c58
Add map for DeConv1d (#62) 
Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-24 23:41:15 +08:00
Sven 410cd8e516
Refine the cmake build (#63) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-24 13:40:37 +08:00
jing.tang 3339135c82 add docs for ops 2021-05-21 18:39:59 +08:00
Jing.Deng 3f6d697cb8 add float unit_test for conv2d 
Signed-off-by: jing.deng <Jing.Deng@verisilicon.com>
 2021-05-21 18:13:02 +08:00
zhao.xia be0a566042 Add map for Conv1D 
Convolution 1D operation, support float32, int8, int16, uint8.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-21 12:46:56 +08:00
zhao.xia 88f7141cfe Support LayerNormalization 
Layer normalization only support float32 data type.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-21 12:46:19 +08:00
Sven c3858af4fc
Fix bazel build by warning as error (#58) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-20 16:23:04 +08:00
zhao.xia b4b6a369a7 Add map for InstanceNormalization 
Currently instance normalization only support float32 data type.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-20 12:41:25 +08:00
Sven e3b127df50
Add group parameter for deconv API (#51) 
* Add group parameter for deconv API

Limitation: only support depthwise deconvolution

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>

* Add single channel case and fix build warning

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-20 10:56:52 +08:00
Kainan Cha 7c0d2f59bb Update op README 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-20 06:15:46 +08:00
xiang.zhang b1b7eadefc Add group parameter for deconv API 
Limitation: only support depthwise deconvolution

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-20 06:15:28 +08:00
Kainan Cha baea9b827f Add ANEURALNETWORKS API reference 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-18 14:24:17 +08:00
Kainan Cha 7770a8fd91 Update Op README 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-18 02:07:52 +08:00
Kainan Cha e05b6f7404 Update operation README with reference 
These links are for reference only, actually implementation
may vary in terms of dimensions and parameters supported.

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-18 01:58:08 +08:00
Nightingale 90e451749f
Update tim lite api (#48) 
* Add lenet sample with TIM-LITE

A lenet sample with TIM-LITE executable.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>

* Update TIM-LITE API

Update handle usage.
Use Execution::Trigger instead of Execution::Exec

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>

* Update lenet lite case to use new api

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-17 22:08:10 +08:00
Sven 66dd29703e
Refine cmake build: add gtest (#47) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-17 13:04:45 +08:00
liyuenan cc3b8c1fe0
Support layout inference for FC and Resize (#45) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-15 22:42:11 +08:00
liyuenan 55ef50385e
Change back the inferface name (#44) 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-14 20:08:53 +08:00
zhao.xia 0a034252c6 Support tim-lite 
Lite module for vip lite driver.

Signed-off-by: zhao.xia <zhao.xia@verisilicon.com>
 2021-05-14 17:37:35 +08:00
Sven fd15d507f2
remove unit test file with regex (#42) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-14 14:00:22 +08:00
Zongwu.Yang b38cad9f1d
Add data layout for kernel to support TVM conv2d (#40) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-14 14:00:02 +08:00
liyuenan 748274143b
support layout inference for operations (#39) 
Add layout inference support for space2depth, depth2space, space2batch, batch2space, pad and
reduce.

Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>

Co-authored-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-05-13 22:27:23 +08:00
Kainan Cha d645494dcc Refine support for data copy operation 
* Properly support tensor handle for both input and output
* Fix UT to use size_in_bytes instead of size in elements

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-12 22:59:36 +08:00
Kainan Cha ef69e466c7 Move all UT to tim/vx/ut directory 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-12 16:32:40 +08:00
Kainan Cha 52401b52a5 Minor update to graph_test 
Update graph_test to demonstrate that CompileToBinary
does not require input data.

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-12 13:31:19 +08:00
Kainan Cha 301d88a5a6 Add support for relational ops 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 23:39:22 +08:00
Kainan Cha 40139e31dd Remove unit_test from CMake 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 19:58:37 +08:00
Kainan Cha d92e08e502 Add support for Cast and Floor operation 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 18:45:28 +08:00
Kainan Cha 22fd359ab2 Fix CMake build error 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 13:44:32 +08:00
Kainan Cha 2b29d5d41c Fix file permission 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 11:01:21 +08:00
Kainan Cha c2e10efb50 Add support for Reorg 
The Reorg implementation is that of YOLOv2.

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-11 10:57:56 +08:00
Sven a42517fdce
Align directory name to namespace for layout inference (#38) 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-11 09:46:46 +08:00
Zongwu.Yang 22d423714f
Optimize permute op for constant tensor (#37) 
Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-10 23:06:04 +08:00
Sven 5cfa7a2c40
Cmake build improvement (#36) 
Added "make install" support for cmake
Fixed symbol removed during link because no reference

Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-05-08 23:02:04 +08:00
Zongwu.Yang 77b801a590
Add layout inference feature (#34) 
* mobilenet_v1_1.0_224_quant.tflite pass
* inception_v1_224_quant.tflite pass
* ssd_mobilenet_v2_fpnlite_320x320_coco17_quant.tflite pass

Signed-off-by: Zongwu Yang <zongwu.yang@verisilicon.com>
 2021-05-08 09:29:47 +08:00
Kainan Cha 31969a7326 Add support for Android make 
This change adds support for building TIM-VX under a
Android AOSP environment.

Instructions below based on Khadas VIMS system

* Add TIM-VX git repository to Android AOSP

  # cd vendor/amlogic/common/npu
  # git clone git@github.com:VeriSilicon/TIM-VX.git tim-vx

* Include tim-vx/Android.mk to AOSP build

  Edit vendor/amlogic/common/npu/Android.mak

    +TMP_PATH := $(LOCAL_PATH)
    +VIVANTE_SDK_DIR := $(LOCAL_PATH)/service/ovx_inc
    +include $(LOCAL_PATH)/tim-vx/Android.mk
    +LOCAL_PATH := $(TMP_PATH)

    ifeq ($(BOARD_NPU_SERVICE_ENABLE), true)

  Note VIVANTE_SDK_DIR needs to point to SDK header
  inclusion path

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-05-06 18:53:51 +08:00
Kainan Cha 88f83019a8 Use RTNE as default rounding policy 
RTNE, Round To Nearest Even is a better rounding policy
which aligns with implementation of Tensorflow Lite.

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-04-27 15:30:15 +08:00
zhengzhouheng eff71c38bf add argmin and argmax op 2021-04-16 00:34:29 +08:00
yuenan.li c9d3416c6b Add the Squeeze op 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-04-15 11:22:48 +08:00
zhengzhouheng dc67e9ac63 add the Stack op 2021-04-07 19:57:28 +08:00
Kainan Cha 165b3fcf8f Minor clean up 
Fix typos and move functions into appropriate files

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-04-07 13:03:56 +08:00
zhengzhouheng 07fc3b9914 add the clip, dropout, batchnorm op 2021-04-07 13:00:41 +08:00
Kainan Cha 90a52ea6c9 Add support for Mish, SoftRelu and HardSigmoid 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-31 12:00:02 +08:00
Kainan Cha f92a5de68b Set Graph Version during in Compile() 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-03-29 17:11:06 +08:00
Kainan Cha c569555f1f Use FCL2 instead of FCL which supports axis 
Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-03-29 17:08:22 +08:00
Kainan Cha c141416238 Update internal to REL/v1.1.30.2 
SHA: 2e64046f

Signed-off-by: Kainan Cha <kainan.zha@verisilicon.com>
 2021-03-29 16:25:12 +08:00
yuenan.li b5f2666e92 Map Select 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-03-25 17:27:04 +08:00
Kainan Cha 0d7afd9d51 Minor cleanup 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-19 11:12:12 +08:00
Kainan Cha cfc70c48df Use auto shape for virtual tensors 
Use auto shape for virtual tensors so that TIM-VX can
perform its internal shape inference and graph
optimizations.

Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-18 14:24:10 +08:00
Kainan Cha b6f0ffaef6 Fix Mutliply API 
Internal ops require a scale parameter to be initialized
to 1.0f.

Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-17 17:56:11 +08:00
yuenan.li f79aac314c Fix bug in tensor attribute setting 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-03-17 16:50:45 +08:00
yuenan.li 8f1c33ea83 add README.md for op support 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-03-16 11:46:57 +08:00
Jiang Bo def53f4b5c Update internal to REL/v1.1.30 
Commit: 6ccb425e
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-02-26 17:05:14 +08:00
Kainan Cha c46904c339 Add op support for Deconv2d 
Signed-off-by: Kainan Cha <kainan.cha@verisilicon.com>
 2021-02-26 09:54:01 +08:00
Jiang Bo 0dbaae19c5 Link whole archive of tim_internal 
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-02-25 15:45:35 +08:00
Zongwu.Yang 8082c43317 Fix cmake build error 
Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
 2021-02-24 19:06:54 +08:00
xiang.zhang 9d44b4477b Added NBG support 
Signed-off-by: xiang.zhang <xiang.zhang@verisilicon.com>
 2021-02-22 11:38:21 +08:00
Zongwu.Yang c5e16157a6 Update linking style as static linking for sample 
Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
 2021-02-08 14:47:37 +08:00
Zongwu.Yang 5108598fd5 Add Cmake build for tim-vx 
Signed-off-by: Zongwu.Yang <Zongwu.Yang@verisilicon.com>
 2021-02-02 10:04:47 +08:00
yuenan.li bd4d277ac1 Support multiply attribute for tensor spec 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-02-01 14:10:03 +08:00
yuenan.li 44af63b9e9 [NNRT-811]Map Slice 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-01-22 14:32:43 +08:00
yuenan.li 0e422b1e6a Map [NNRT-824]LeakyRelu/[NNRT-817]LogicalOr/And/[NNRT-831]GatherNd 
Signed-off-by: yuenan.li <yuenan.li@verisilicon.com>
 2021-01-19 16:44:43 +08:00
Jiang Bo 90b7a6fc32 Rename Op 'Permute' to 'Transpose' 
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-01-12 11:21:51 +08:00
Jiang Bo 7972af0697 Initial Commit for VERSION 1.1.28 
Signed-off-by: Jiang Bo <bo.jiang@verisilicon.com>
 2021-01-11 18:27:48 +08:00