Luke Wren
|
ee7d8e1947
|
Bump embench for script fixes/improvements
|
2022-07-07 18:29:37 +01:00 |
|
Luke Wren
|
91be98f2da
|
Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
|
2022-07-06 23:53:11 +01:00 |
|
Luke Wren
|
5a39d8b7e7
|
Track minstret and mcycle separately now that the model is cycle-accurate
|
2022-07-06 13:50:13 +01:00 |
|
Luke Wren
|
5dfe5cb62b
|
Update rvpy to match current fastest config: stage 2 mul, single BTB entry on backward branches
|
2022-07-06 13:49:51 +01:00 |
|
Luke Wren
|
b7d9defcf2
|
Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
|
2022-07-05 03:37:19 +01:00 |
|
Luke Wren
|
27793b25a1
|
Rebase riscv-tests against upstream, and pick up new semihosting file io test
|
2022-07-04 00:45:20 +01:00 |
|
Luke Wren
|
e44d2e6f9e
|
Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed
|
2022-07-03 23:34:12 +01:00 |
|
Luke Wren
|
9e15cd3485
|
Add standalone SBA-to-AHB shim, and make SBA off by default in the DM
|
2022-07-03 15:30:33 +01:00 |
|
Luke Wren
|
d5cd3e0681
|
Add SBA patch-through to 1-core wrapper.
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
|
2022-07-03 15:17:44 +01:00 |
|
Luke Wren
|
51bc26f8ac
|
First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
|
2022-07-03 00:25:47 +01:00 |
|
Luke Wren
|
8ef9d77be8
|
Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations.
Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)
|
2022-06-25 13:11:40 +01:00 |
|
Luke Wren
|
d9389fb23e
|
Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
|
2022-06-16 01:42:28 +01:00 |
|
Luke Wren
|
d31b1708db
|
Make rvpy cycle-accurate enough to get the correct Dhrystone score
|
2022-06-09 01:34:37 +01:00 |
|
Luke Wren
|
02b303b385
|
Remove stray old expected output file from sw_testcases dir
|
2022-06-03 17:20:49 +01:00 |
|
Luke Wren
|
e2c9901701
|
Update readme for runtests
|
2022-05-30 01:12:16 +01:00 |
|
Luke Wren
|
2cfe6aa90e
|
Add test to check MPRV/MPP behaviour when executing an MRET
|
2022-05-29 19:51:19 +01:00 |
|
Luke Wren
|
f96a0ffb75
|
Add test for MPRV vs PMP
|
2022-05-29 19:06:04 +01:00 |
|
Luke Wren
|
71eff7649d
|
Add PMP U-mode read/write permission test
|
2022-05-29 18:42:44 +01:00 |
|
Luke Wren
|
c8afcdbb8f
|
Extend umode_wfi test to check U-mode WFI doesn't stall the processor if TW=0 or PMP X check fails
|
2022-05-29 17:42:15 +01:00 |
|
Luke Wren
|
460fa0bb4a
|
Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.
|
2022-05-28 17:22:28 +01:00 |
|
Luke Wren
|
66965ac073
|
Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
|
2022-05-28 15:36:21 +01:00 |
|
Luke Wren
|
4090f4eb24
|
Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat
|
2022-05-28 15:01:27 +01:00 |
|
Luke Wren
|
9e2f5df00a
|
Add testbench flag to propagate CPU return code to testbench return
|
2022-05-28 15:00:28 +01:00 |
|
Luke Wren
|
81aec325bb
|
ecall from U-mode has a different mcause value than ecall from M-mode
|
2022-05-28 12:07:29 +01:00 |
|
Luke Wren
|
632c61daba
|
Rebase debug tests, pick up two new tests (both pass)
|
2022-05-28 11:34:41 +01:00 |
|
Luke Wren
|
f2876eb51f
|
Fix bad mepc reported after branching to a branch in a no-X address range
|
2022-05-27 22:47:04 +01:00 |
|
Luke Wren
|
b655148148
|
Bump riscv-tests for better PMP disable fix
|
2022-05-27 21:36:54 +01:00 |
|
Luke Wren
|
e208652ad7
|
Fix misa value in csr_id test
|
2022-05-26 00:48:12 +01:00 |
|
Luke Wren
|
d7787942e9
|
Add two new tests to debug test list. Remainder are still non-applicable
|
2022-05-26 00:47:08 +01:00 |
|
Luke Wren
|
a17b941e38
|
Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)
|
2022-05-25 23:46:23 +01:00 |
|
Luke Wren
|
37f7588bad
|
Fix hazard3 reset vector check value in debug tests
|
2022-05-25 21:45:36 +01:00 |
|
Luke Wren
|
5be8835365
|
Add missing output to pmp_write_and_lock test
|
2022-05-25 15:34:28 +01:00 |
|
Luke Wren
|
399dcf2cb9
|
Add test for U-mode X permissions
|
2022-05-25 13:47:16 +01:00 |
|
Luke Wren
|
7340765699
|
Add simple test to read, write and lock PMP registers
|
2022-05-25 02:05:24 +01:00 |
|
Luke Wren
|
456810b09e
|
Make vcd generation optional in runtests
|
2022-05-24 22:56:13 +01:00 |
|
Luke Wren
|
64d9f4a111
|
Add tests for execution of mret and wfi in U mode
|
2022-05-24 22:14:20 +01:00 |
|
Luke Wren
|
20f06c4a02
|
Build tb with 4 PMP regions by default
|
2022-05-24 20:06:57 +01:00 |
|
Luke Wren
|
7cfc976ef2
|
Set U RWX permission on all of memory in the U CSR readability test
|
2022-05-24 19:58:12 +01:00 |
|
Luke Wren
|
cfed35b3da
|
Fix the stupid printf warning on x86-64 as well as arm64
|
2022-05-24 18:22:25 +01:00 |
|
Luke Wren
|
f033cde874
|
Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
|
2022-05-24 17:30:24 +01:00 |
|
Luke Wren
|
ba81b533d2
|
Build core with U mode support for tb
|
2022-05-24 16:44:22 +01:00 |
|
Luke Wren
|
0199f48087
|
Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
|
2022-05-24 16:44:03 +01:00 |
|
Luke Wren
|
4ba3f7ceb9
|
Fix format warning in tb.cpp on arm64
|
2022-05-24 16:17:54 +01:00 |
|
Luke Wren
|
ef35dc859d
|
Add zicsr to march in makefiles
|
2022-05-24 16:17:54 +01:00 |
|
Luke Wren
|
07d4b23a9a
|
Add option to pass test list to runtests
|
2022-05-24 16:17:54 +01:00 |
|
Luke Wren
|
31061bd472
|
Add Zbkb to bitmanip tests and regenerate vectors
|
2022-05-21 17:15:46 +01:00 |
|
Luke Wren
|
4ffe007a84
|
Add zicsr to march in bitmanip tests, so it builds on newer toolchains
|
2022-05-20 01:32:21 +01:00 |
|
Luke Wren
|
7dc5046505
|
Perf option for dedicated branch comparator
|
2022-04-02 11:40:47 +01:00 |
|
Luke Wren
|
3c61fae9ef
|
Remove the halfword fetch thing, was only really useful on RISCBoy
|
2022-04-02 10:54:16 +01:00 |
|
Luke Wren
|
5aca1381ac
|
Couple of fixups for rvpy which I forgot to commit at some point
|
2022-03-01 20:27:18 +00:00 |
|
Luke Wren
|
28b53ef7b5
|
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
|
2021-12-18 00:35:13 +00:00 |
|
Luke Wren
|
a81d129961
|
Add exclusives monitor to testbench
|
2021-12-17 17:03:35 +00:00 |
|
Luke Wren
|
5ab60422ad
|
Add minimal multicore launch code
|
2021-12-17 01:24:11 +00:00 |
|
Luke Wren
|
01d9617f9c
|
Add multicore tb integration file
|
2021-12-17 00:41:23 +00:00 |
|
Luke Wren
|
207566660d
|
tb: handle both ports identically. Preparing for dual core
|
2021-12-17 00:04:00 +00:00 |
|
Luke Wren
|
88fea7acfa
|
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
|
2021-12-12 18:28:23 +00:00 |
|
Luke Wren
|
719c21fec3
|
Add IRQ tests. Disable waves by default in runtests
|
2021-12-12 15:53:04 +00:00 |
|
Luke Wren
|
9fb2af800f
|
Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
|
2021-12-12 14:58:50 +00:00 |
|
Luke Wren
|
a232833d81
|
Add CSR writable test
|
2021-12-12 14:23:34 +00:00 |
|
Luke Wren
|
8a003dbbed
|
Make mcycle/minstret inhibited by default
|
2021-12-12 13:55:33 +00:00 |
|
Luke Wren
|
7da67a0600
|
Similarly for minstret
|
2021-12-11 22:25:12 +00:00 |
|
Luke Wren
|
1b722b5f27
|
Add mcycle test, fix incorrect description of mcycle in docs
|
2021-12-11 21:21:31 +00:00 |
|
Luke Wren
|
93eca19aeb
|
Add test for lr/sc RAW stalls
|
2021-12-11 19:16:41 +00:00 |
|
Luke Wren
|
763a5cd364
|
Add test for readability of all implemented CSRs
|
2021-12-11 17:50:12 +00:00 |
|
Luke Wren
|
7b1da32af1
|
Move expected_output into tests inline
|
2021-12-11 16:58:25 +00:00 |
|
Luke Wren
|
9460b3cd04
|
Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
|
2021-12-11 15:52:34 +00:00 |
|
Luke Wren
|
f64f44f7af
|
Add test for identification CSRs vs expected values
|
2021-12-11 13:26:59 +00:00 |
|
Luke Wren
|
4066e941ef
|
Fix sim cmdline in bitmanip-random tests
|
2021-12-11 13:13:21 +00:00 |
|
Luke Wren
|
3fe0d92d41
|
Add load/store alignment testcases
|
2021-12-11 12:53:37 +00:00 |
|
Luke Wren
|
c90727b05a
|
Remove padding after vector table in init.S
|
2021-12-11 12:22:23 +00:00 |
|
Luke Wren
|
6076eba61f
|
Add run_all script under riscv-compliance
|
2021-12-11 12:08:53 +00:00 |
|
Luke Wren
|
6edfbfae8b
|
Add ebreak size/alignment test
|
2021-12-11 11:17:24 +00:00 |
|
Luke Wren
|
abe1769929
|
Add instruction access fault testcase
|
2021-12-11 09:54:00 +00:00 |
|
Luke Wren
|
933f2cd65c
|
Fix remaining fallout from tb args change
|
2021-12-11 09:53:39 +00:00 |
|
Luke Wren
|
6d55cd2d55
|
Consolidate openocd and bin-load testbenches
|
2021-12-11 09:46:38 +00:00 |
|
Luke Wren
|
fadb9601de
|
Illegal instruction test
|
2021-12-10 00:11:18 +00:00 |
|
Luke Wren
|
3d2c912b4f
|
Add test script to make it easier to add software testcases
|
2021-12-09 22:25:18 +00:00 |
|
Luke Wren
|
ac9285846f
|
Timer struct in IO header
|
2021-12-06 17:16:21 +00:00 |
|
Luke Wren
|
c57a80f358
|
Add AMO + timer testcase
|
2021-12-06 07:47:20 +00:00 |
|
Luke Wren
|
d86b2849c9
|
Bump to latest version of riscv-arch-test
|
2021-12-06 02:18:48 +00:00 |
|
Luke Wren
|
df658d86ff
|
First plausibly working AMOs. Add AMOs to instruction timings list
|
2021-12-04 23:44:22 +00:00 |
|
Luke Wren
|
5e17bb805e
|
Add basic support for lr/sc instructions from the A extension
|
2021-12-04 15:02:31 +00:00 |
|
Luke Wren
|
c5d6be24f3
|
Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
|
2021-12-04 14:06:48 +00:00 |
|
Luke Wren
|
5db6c68c56
|
Update riscv-tests for correct misa.x value
|
2021-12-04 11:19:43 +00:00 |
|
Luke Wren
|
52ba930638
|
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
|
2021-12-04 01:17:57 +00:00 |
|
Luke Wren
|
be6b2f3f76
|
Fix up DTMs to use byte addressing
|
2021-12-02 02:05:23 +00:00 |
|
Luke Wren
|
1ebccb7cce
|
Switch DM to use byte addresses on APB, not word addresses
|
2021-12-02 01:47:30 +00:00 |
|
Luke Wren
|
fad64bb6c9
|
Bump embench test submodule
|
2021-11-29 18:51:10 +00:00 |
|
Luke Wren
|
ba248c832a
|
init.S: also print out mcause when trapping an unhandled exception
|
2021-11-29 18:49:37 +00:00 |
|
Luke Wren
|
c8afb4ac33
|
Add option for fast high-half multiplies
|
2021-11-29 18:48:02 +00:00 |
|
Luke Wren
|
35c5e213c7
|
Bump embench for working benchmarks (except md5)
|
2021-11-29 00:59:14 +00:00 |
|
Luke Wren
|
94a3d43f27
|
Add Hazard3's registered marchid value to hdl and docs
|
2021-11-28 19:53:49 +00:00 |
|
Luke Wren
|
e7466ae4be
|
Move DM data0 CSR into the M-custom space, and document this
|
2021-11-28 15:52:52 +00:00 |
|
Luke Wren
|
47ce2cc8ec
|
Add embench submodule, with configs for hazard3
|
2021-11-28 00:01:18 +00:00 |
|
Luke Wren
|
14a4f1a281
|
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
|
2021-11-27 17:19:41 +00:00 |
|
Luke Wren
|
6f1a10724b
|
Add bitmanip test vector generation script
|
2021-11-26 23:34:06 +00:00 |
|
Luke Wren
|
1bb7e33b69
|
Fix alignment of heap_ptr in init.S. Small ALU cleanup
|
2021-11-26 02:59:50 +00:00 |
|
Luke Wren
|
e352715fdf
|
Fix IO decode in openocd/tb.cpp
|
2021-11-23 22:12:51 +00:00 |
|
Luke Wren
|
4d14203586
|
Update riscv-tests fork for crash loop debug test
|
2021-11-23 21:58:39 +00:00 |
|
Luke Wren
|
c1f17b0b23
|
Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
|
2021-11-06 09:59:27 +00:00 |