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  • 8b301c5692 Silence useless linker rwx warning Luke Wren 2023-11-03 20:09:02 +0000
  • 31642b6d4a Add amo_ops testcase Luke Wren 2023-04-01 08:47:29 +0100
  • a536e3baa7 rvcpp sim: add A extension and M-mode traps (now passes a lot of the Hazard3 tests) Luke Wren 2023-04-01 08:19:25 +0100
  • 26d699e18c rvcpp simulator: fix bad regnum decode for c.slli outside of x8..x15 Luke Wren 2023-04-01 06:02:45 +0100
  • 54f0a593c8 Fix +x permission of riscv-compliance/clean_all script Luke Wren 2023-04-01 04:42:10 +0100
  • d8cc132a49 tb_cxxrtl Makefile: make synthesis depend on config headers Luke Wren 2023-04-01 04:41:39 +0100
  • 86fc4e3f2d Update embench config and readme Luke Wren 2023-03-31 03:02:06 +0100
  • ca40c077be Capture JTAG bitbang log from most recent SMP debug test. Luke Wren 2023-03-31 02:14:22 +0100
  • e89ab0d095 tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ (i.e. single-core testbench). Avoids some odd behaviour with wide assignment to single-bit wire from the CXXRTL harness. Luke Wren 2023-03-31 02:11:40 +0100
  • 5aee830ac0 Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH (clean up fallout from Zc implementation -- ensure Readme instructions will get you to hello world) Luke Wren 2023-03-31 01:53:28 +0100
  • a861a110c1 Update to the latest riscv-arch-test. This uses the new test framework -- scripts are a little janky for now. Luke Wren 2023-03-31 01:39:24 +0100
  • 18d3b03cc8 Fix rm of build directory in tb_cxxrtl/Makefile Luke Wren 2023-03-30 22:43:21 +0100
  • 97121afa91 Extend testbench to allow dumping/replaying JTAG to text file. This allows debugging of tests that behave differently when VCD dumping is enabled, due to the difference in execution speed. (A couple of the SMP debug tests fail intermittently.) Luke Wren 2023-03-27 00:17:11 +0100
  • c41fe0609b Add a second mtimecmp comparator to TB IO, for dual-core InterruptTest from RISC-V debug tests. Fix a couple of minor test script issues. Luke Wren 2023-03-26 23:00:18 +0100
  • 94bd965e4e Add script for running SMP debug tests Luke Wren 2023-03-24 18:45:11 +0000
  • 97509f548a tb_cxxrtl Makefile: better support for building multiple tb configurations Luke Wren 2023-03-24 18:44:37 +0000
  • cbb490da6a Bump riscv-tests for hazard3 SMP debug test config changes Luke Wren 2023-03-24 18:11:08 +0000
  • 0dd6be181d Fix up HwbpManual test in riscv-tests fork, and update debug test list Luke Wren 2023-03-24 00:28:02 +0000
  • 43130a16e4 Fix readback of tdata2 and tinfo CSRs (Found due to latest riscv-openocd failing to enumerate triggers, as it now scans tinfo before going for tdata1/mcontrol) Luke Wren 2023-03-23 23:33:29 +0000
  • 532e27dbc9 Bump riscv-tests for new debug and ISA tests. (Rebase of Hazard3 patches) Luke Wren 2023-03-23 23:32:28 +0000
  • afcb6d283c Missing default assignment Luke Wren 2023-03-23 10:57:50 +0000
  • 2905c1f820 Revert default for EXTENSION_ZC* to match docs in hazard3_config.vh Luke Wren 2023-03-23 03:07:09 +0000
  • 4a1d2b5008 Save a cycle on popret/popretz by executing the stack adjust after the jump Luke Wren 2023-03-23 02:50:34 +0000
  • b074d370a6 Add Zcb/Zcmp instruction timings to docs Luke Wren 2023-03-23 01:12:38 +0000
  • 56586def8d List Zcb/Zcmp in docs, and rebuild PDF Luke Wren 2023-03-22 02:55:07 +0000
  • b58cde882a Add link to Zcb/Zcmp specs Luke Wren 2023-03-22 02:48:18 +0000
  • 95faab6f2c Add zcmp_irq_kill test Luke Wren 2023-03-22 02:44:03 +0000
  • e98d7b41ea Hook up power control signals on dual-core tb Luke Wren 2023-03-22 00:34:19 +0000
  • fcbc4f6805 Fix regnum predecode of quadrant-2 RVC instructions with 5-bit regnums (regression caused by adding Zcb) Luke Wren 2023-03-21 23:04:11 +0000
  • 8f461b63b4 Fix mvsa01/mva01s in rvcpp Luke Wren 2023-03-21 21:54:04 +0000
  • 410d002372 First pass at adding Zcmp to rvcpp Luke Wren 2023-03-21 21:28:49 +0000
  • 8e7e8f4008 Extend rvcpp ISA sim to cover RVC. Passes RV32IC compliance. Luke Wren 2023-03-21 19:38:46 +0000
  • 670099e461 Fix trap address correction for Zcm instructions never firing Luke Wren 2023-03-20 18:38:28 +0000
  • f702fe5352 Add test covering all pop instructions Luke Wren 2023-03-20 18:26:29 +0000
  • d2adc6aad7 Add tests for mva01s/mvsa01 Luke Wren 2023-03-20 16:05:07 +0000
  • 142b3a81ff Add spike-extracted output to zcmp_push Luke Wren 2023-03-20 15:37:38 +0000
  • ee6e03e0e6 Add beginnings of Spike-able zcmp_push test Luke Wren 2023-03-20 14:23:56 +0000
  • 7607dacfc4 Fix incorrect register order within stack frame for push/pop Luke Wren 2023-03-20 06:32:20 +0000
  • 8b73b1b927 Fix mvsa01 r2s decode, Dhrystone runs with Zcb now Luke Wren 2023-03-20 05:03:39 +0000
  • c4e0c15160 Fix hookup of uop_atomic signal Luke Wren 2023-03-20 02:40:49 +0000
  • 3b2ddee06b Fix push/pop frame format, fix source regnums for mvsa01/mva01s Luke Wren 2023-03-20 02:35:18 +0000
  • 7702c44288 Handle timeout in runtests Luke Wren 2023-03-20 01:32:16 +0000
  • 4aed15540d Fix destination register for final uop of c.popretz Luke Wren 2023-03-20 01:31:49 +0000
  • 6b8923a623 Fix bad predecode of a0/a1 in mvsa01/mva01s. Fix bad pop load offset when extra sp adjust is nonzero. Luke Wren 2023-03-20 01:03:49 +0000
  • e966e832d2 First attempt at Zcmp Luke Wren 2023-03-20 00:00:51 +0000
  • 99c0660c3e Fix decompress of c.sb/c.sh Can now run CoreMark, Hazard3 sw testcases etc using core-v compiler with Zcb enabled. Luke Wren 2023-03-16 20:27:21 +0000
  • 59edb2fc5f Fix predecode of quadrant-00 compressed instruction rs1, to get correct rs1 for new Zbc byte/halfword load/store Luke Wren 2023-03-16 19:10:43 +0000
  • 78d937e5c8 Yeet Zcb into core Luke Wren 2023-03-16 18:48:15 +0000
  • a247c5cfc1 Bump riscv-tests fork: fix breakpoint test not setting tcontrol.mte when it is implemented. Luke Wren 2023-03-16 17:50:52 +0000
  • ba3c3138ef Fix 3 minor Debug Module bugs: - sbdata0 should ignore writes when sbbusyerror or sberror is set - All sbaddress0 writes and sbdata0 accesses should set sbbusyerror if sbbusy is set - sbaddress should not increment if access gets bus error Luke Wren 2023-03-03 13:24:31 +0000
  • 7101cccf3b Cut through-path on reset halt request from debug module to bus Luke Wren 2023-01-19 13:46:55 +0000
  • 7fbdb69328 Allow reconnecting to the testbench JTAG socket Scott Shawcroft 2022-10-19 12:44:42 -0700
  • 4c12f163bd
         Add OrangeCrab 25F support (#7) Scott Shawcroft 2022-12-17 03:49:41 -0800
  • 8e7ffb040c Comment typo Luke Wren 2022-12-17 11:39:47 +0000
  • 52e665fb45 Remove unnecessary clear of sleep flags on bus error (which had a TODO asking if it should be removed) and add some more properties in its place. Luke Wren 2022-11-05 18:50:36 +0000
  • 05cb6e7ee8 Rename confusingly named power control signal for allowing clock gate to shut during WFI/block sleep. Luke Wren 2022-11-05 18:26:56 +0000
  • c81666177e Remove FIXME about considering concurrent load/store and debug entry in calculating the privilege of load/stores. This is safe because it is only the *current* debug mode state which affects load/stores, and some new properties have been added to ensure load/stores can not be in aphase at the point debug mode is entered/exited (which is achieved by delaying the trap). Therefore there is no way for debug entry to inadvertently boost the privilege of an executing U-mode load/store. Luke Wren 2022-11-05 18:18:33 +0000
  • 97bf2d06f6 Hold off first instruction fetch until pwrup_ack is first seen high Luke Wren 2022-11-05 14:58:47 +0000
  • dff278ea05 Increase DTM idle cycle hint to 8 cycles -- see #6 Luke Wren 2022-10-19 21:11:18 +0100
  • 1953773ca5 Don't gate exception into D-mode CSR write, as a valid CSR instruction writing to a valid CSR in D-mode is guaranteed not to raise any exception (particularly the external data0 CSR is of interest) Luke Wren 2022-10-10 22:14:05 +0100
  • ae4ddf7001 Clean up the old/unused W_COUNTER parameter, and use a cleaner tie-off style for the counter CSRs Luke Wren 2022-10-10 16:33:31 +0100
  • f771a1294d Alias DPC to the real program counter, small savings overall Luke Wren 2022-10-10 00:28:42 +0100
  • aa438fc37c Remove op_b (rs2) register from muldiv_seq for modest LUT/FF savings Luke Wren 2022-10-08 18:22:08 +0100
  • d3667769d2 Arrange for address buses to be 0 when processor is held in reset Luke Wren 2022-10-08 16:50:58 +0100
  • 633a07fef9 Tidy up priority tie-offs in irq_ctrl Luke Wren 2022-10-08 16:25:05 +0100
  • 5e7bf0d604 Don't reset register file by default Luke Wren 2022-10-08 16:24:28 +0100
  • f329d30713 Typo in docs introduction Luke Wren 2022-10-08 15:10:45 +0100
  • 489480dc80 Revise default config values, and update docs with new values Luke Wren 2022-10-08 08:43:25 +0100
  • 0b18fae32e Fix swapped MHARTID/MCONFIGPTR values in tb configs Luke Wren 2022-10-08 08:42:50 +0100
  • 874cb20910 Add config headers to tb_cxxrtl instead of using defparams in Makefile Luke Wren 2022-10-08 08:09:26 +0100
  • 8721bd3deb Add RISC-V timer to example soc, and tweak ULX3S config Luke Wren 2022-10-07 03:11:30 +0100
  • a18c3018e1 Bump riscv-formal to head of hazard3 branch, not sure what happened there Luke Wren 2022-10-07 01:35:10 +0100
  • bf1bca2ca5 Remove FPGA synth netlist checked in by mistake Luke Wren 2022-10-06 16:00:27 +0100
  • 1036d15467 Clean up duplicate declaration of external_irq_pending in hazard3_irq_ctrl Luke Wren 2022-10-06 15:59:54 +0100
  • 4b94c9a2d4 Document new configuration for IRQ and PMPM extensions Luke Wren 2022-10-06 00:19:13 +0100
  • e6aaf4b801 Avoid IRQ to bus through-path when custom IRQs are disabled Luke Wren 2022-10-06 00:16:10 +0100
  • c55d3f0d0b Make custom IRQ and PMP functionality optional. Factor out IRQ controller into separate module. Luke Wren 2022-10-05 23:52:20 +0100
  • d1d70efa60 Fix some width issues introduced by last commit Luke Wren 2022-10-05 22:19:02 +0100
  • 6f8b75c041 Make IRQ vectors right-sized. CXXRTL was spending > 1/3rd of its time in the CSR update. Luke Wren 2022-10-05 22:11:53 +0100
  • 0915cc2834 Doh Luke Wren 2022-09-08 15:11:24 +0100
  • f48177c644 Tie off debug LEDs in ULX3S top level Luke Wren 2022-09-05 00:37:44 +0100
  • 9eb8590858 Add generate to avoid elaborating internals of PMP/triggers with 0 PMP regions or triggers. Luke Wren 2022-09-05 00:36:41 +0100
  • 18c64bd633 Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression Luke Wren 2022-09-04 23:56:14 +0100
  • 787a7ec372 Fix bad preprocessor conditional in ECP5 JTAG DTM Luke Wren 2022-09-04 23:48:58 +0100
  • c594ec42e9 Change style of IRQ register tie-offs as Yosys was not able to trim them for iCE40 synthesis. Luke Wren 2022-09-04 23:43:24 +0100
  • 3ae843034d Example soc: connect up power signals and always-on clock. Set more parameters explicitly. Luke Wren 2022-09-04 23:42:48 +0100
  • 624d39669d Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs. Luke Wren 2022-08-29 19:20:09 +0100
  • 1c2249dbef Typo Luke Wren 2022-08-29 16:25:12 +0100
  • 6abd93eb49 Oops, masked the wakeup-on-halt request path when I masked IRQs on WFI state. Luke Wren 2022-08-29 16:14:42 +0100
  • 099f0467fb Clean up remnants of the 'wfi_is_nop' thing that seemed like a good idea at the time Luke Wren 2022-08-29 15:56:57 +0100
  • da4097ecd8 Delay pwrup_req->pwrup_ack in tb Luke Wren 2022-08-29 14:55:11 +0100
  • 954bae5cf1 Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb. Luke Wren 2022-08-29 14:51:19 +0100
  • b352d3878d Update docs for new power control extension Luke Wren 2022-08-28 19:54:55 +0100
  • 2ae2463b97 First stab at adding wake/sleep state machine Luke Wren 2022-08-28 19:48:50 +0100
  • ce93c45e69 Add docs section for custom extensions Luke Wren 2022-08-28 15:50:26 +0100
  • bf38d93d33 Remove references to AHB-Lite, describe buses as (a subset of) AHB5 Luke Wren 2022-08-28 14:15:20 +0100
  • 7d18a21734 Editing Luke Wren 2022-08-27 20:49:55 +0100
  • d56e217a40 Work on docs. Document config options, expand the intro, move instruction timings and pseudocode to appendices. Luke Wren 2022-08-27 20:13:21 +0100
  • a79c857d82 Bump riscv-tests: enable hardware instruction breakpoints in hardware tests Luke Wren 2022-08-27 17:05:02 +0100
  • 9a60f06c43 Fix trigger enable condition Luke Wren 2022-08-23 01:05:46 +0100