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  • 8a003dbbed Make mcycle/minstret inhibited by default Luke Wren 2021-12-12 13:55:33 +0000
  • 2bbc3637a2 Simplify CSR update logic. Showed promise in block synth but no difference to example soc. Still cleaner RTL. Luke Wren 2021-12-12 00:38:30 +0000
  • 7da67a0600 Similarly for minstret Luke Wren 2021-12-11 22:25:12 +0000
  • 1b722b5f27 Add mcycle test, fix incorrect description of mcycle in docs Luke Wren 2021-12-11 21:10:26 +0000
  • 93eca19aeb Add test for lr/sc RAW stalls Luke Wren 2021-12-11 19:16:41 +0000
  • 763a5cd364 Add test for readability of all implemented CSRs Luke Wren 2021-12-11 17:50:12 +0000
  • 7b1da32af1 Move expected_output into tests inline Luke Wren 2021-12-11 16:58:25 +0000
  • 9460b3cd04 Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1. Luke Wren 2021-12-11 15:52:34 +0000
  • f64f44f7af Add test for identification CSRs vs expected values Luke Wren 2021-12-11 13:26:59 +0000
  • 4066e941ef Fix sim cmdline in bitmanip-random tests Luke Wren 2021-12-11 13:13:21 +0000
  • 3fe0d92d41 Add load/store alignment testcases Luke Wren 2021-12-11 12:53:37 +0000
  • c90727b05a Remove padding after vector table in init.S Luke Wren 2021-12-11 12:22:23 +0000
  • 6076eba61f Add run_all script under riscv-compliance Luke Wren 2021-12-11 12:08:53 +0000
  • 52d58fdee4 Add keep wires for debug port on bus compliance tb Luke Wren 2021-12-11 12:06:10 +0000
  • 6edfbfae8b Add ebreak size/alignment test Luke Wren 2021-12-11 11:17:24 +0000
  • cccc32fe16 Update instructions for running hello world under debugger Luke Wren 2021-12-11 10:09:26 +0000
  • abe1769929 Add instruction access fault testcase Luke Wren 2021-12-11 09:54:00 +0000
  • 933f2cd65c Fix remaining fallout from tb args change Luke Wren 2021-12-11 09:53:39 +0000
  • 6d55cd2d55 Consolidate openocd and bin-load testbenches Luke Wren 2021-12-11 09:46:38 +0000
  • fadb9601de Illegal instruction test Luke Wren 2021-12-10 00:11:18 +0000
  • 3d2c912b4f Add test script to make it easier to add software testcases Luke Wren 2021-12-09 22:25:18 +0000
  • 7d2fa6a049 Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic Luke Wren 2021-12-09 06:26:31 +0000
  • 116e34df49 Fix commented out frontend properties which relied on non-constant past reset values Luke Wren 2021-12-07 20:24:29 +0000
  • 449348f459 Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception. Luke Wren 2021-12-07 19:24:53 +0000
  • dbc331dbb4 Add exclusives bus properties Luke Wren 2021-12-07 05:37:59 +0000
  • 6ef3503ef5 Add A bit to MISA, update docs Luke Wren 2021-12-07 05:10:20 +0000
  • 93be227d8a Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts. Luke Wren 2021-12-06 20:12:23 +0000
  • ed22d502fd Fix bus stall getting stuck high when a bus fault exception isn't immediately accepted by the frontend Luke Wren 2021-12-06 19:28:21 +0000
  • 50d3d5d3b3 Maintain AMO IRQ holdoff when transitioning from data phase to error phase, to prevent error possibly being flushed Luke Wren 2021-12-06 19:27:20 +0000
  • 29c5c8ca7f Fix AMO stall falling through when write data phase should proceed to error phase Luke Wren 2021-12-06 18:28:35 +0000
  • 8bfc089660 Slightly more strict holdoff of IRQs on AMO Luke Wren 2021-12-06 18:13:43 +0000
  • 0b3629564c Don't apply shifter assertions to rotates Luke Wren 2021-12-06 18:12:23 +0000
  • ac9285846f Timer struct in IO header Luke Wren 2021-12-06 17:16:21 +0000
  • 9e7ea4adb6 Fix column width Luke Wren 2021-12-06 17:14:23 +0000
  • c57a80f358 Add AMO + timer testcase Luke Wren 2021-12-06 07:47:20 +0000
  • 4c532240f8 Hold off IRQ when AMO is past the point of no return Luke Wren 2021-12-06 07:45:13 +0000
  • 260491405a Fix atomic instructions not asserting decode error when A extension is disabled Luke Wren 2021-12-06 07:28:23 +0000
  • cc38f46848 Fix AMO wdata valid left high when entering trap at just the right time Luke Wren 2021-12-06 07:27:57 +0000
  • d86b2849c9 Bump to latest version of riscv-arch-test Luke Wren 2021-12-06 02:18:36 +0000
  • 1fa773c67a Minimal RV32IMA + debug that fits on iCEBreaker. Not sure why area has regressed so much recently. Luke Wren 2021-12-05 02:16:54 +0000
  • 12c79c0b41 Fix feature-flag for Zbs instructions in decoder Luke Wren 2021-12-05 02:05:35 +0000
  • 9b9120960d Fix missing RAW stall on sc.w succes result. Closing laptop again. Luke Wren 2021-12-05 00:54:28 +0000
  • 723016a739 Update ISA support in Readme Luke Wren 2021-12-04 23:49:35 +0000
  • df658d86ff First plausibly working AMOs. Add AMOs to instruction timings list Luke Wren 2021-12-04 23:44:22 +0000
  • 5c098866f2 Sketch in AMO support Luke Wren 2021-12-04 20:46:39 +0000
  • 34e57f0b14 Sketch in an AMO ALU Luke Wren 2021-12-04 18:52:41 +0000
  • a8933c332d Fix illegal issue of pipelined exclusives on the bus, and document correct timings Luke Wren 2021-12-04 18:23:01 +0000
  • 5e17bb805e Add basic support for lr/sc instructions from the A extension Luke Wren 2021-12-04 15:02:31 +0000
  • c5d6be24f3 Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed. Luke Wren 2021-12-04 14:06:48 +0000
  • 607147f280 Rewrite byte pick/sign-extend logic, preparing to handle more memops Luke Wren 2021-12-04 12:08:54 +0000
  • 5db6c68c56 Update riscv-tests for correct misa.x value Luke Wren 2021-12-04 11:19:43 +0000
  • a988adfec8 Add RISC-V opcodes and memory operation codes for atomics Luke Wren 2021-12-04 11:16:24 +0000
  • 52ba930638 Remove useless midcr.eivect feature. Make mlei left-shift its value by 2. Luke Wren 2021-12-04 01:17:57 +0000
  • cd1b391714 More docs cleanup Luke Wren 2021-12-02 02:29:34 +0000
  • dfb07822ee Remove UART DTM Luke Wren 2021-12-02 02:08:16 +0000
  • be6b2f3f76 Fix up DTMs to use byte addressing Luke Wren 2021-12-02 02:05:23 +0000
  • 1ebccb7cce Switch DM to use byte addresses on APB, not word addresses Luke Wren 2021-12-02 01:47:30 +0000
  • ebe87dce46 Reorganise CSR section of docs Luke Wren 2021-12-02 01:35:18 +0000
  • c5e85dea4c Add mconfigptr CSR Luke Wren 2021-12-01 03:25:45 +0000
  • fad64bb6c9 Bump embench test submodule Luke Wren 2021-11-29 18:51:10 +0000
  • ba248c832a init.S: also print out mcause when trapping an unhandled exception Luke Wren 2021-11-29 18:49:37 +0000
  • c8afb4ac33 Add option for fast high-half multiplies Luke Wren 2021-11-29 18:48:02 +0000
  • 35c5e213c7 Bump embench for working benchmarks (except md5) Luke Wren 2021-11-29 00:59:11 +0000
  • d29bb13c4a Replace SSH submodule URLs with HTTPS, oops Luke Wren 2021-11-28 22:26:29 +0000
  • 94a3d43f27 Add Hazard3's registered marchid value to hdl and docs Luke Wren 2021-11-28 19:46:08 +0000
  • 1aa9dbcddd Fix comment typo in APB clock crossing Luke Wren 2021-11-28 17:40:57 +0000
  • 0fafae1ab1 Regenerate PDF Luke Wren 2021-11-28 16:27:54 +0000
  • e7466ae4be Move DM data0 CSR into the M-custom space, and document this Luke Wren 2021-11-28 15:52:25 +0000
  • 9bf4d5105f Describe possible debug topologies. Update pdf. Luke Wren 2021-11-28 09:01:23 +0000
  • 4e2686d4ab Finish documenting CSRs. Draw a debug topology diagram. Luke Wren 2021-11-28 08:17:23 +0000
  • 76172cdade Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs. Luke Wren 2021-11-28 06:33:35 +0000
  • 79c29354d2 Update docs with bitmanip instructions Luke Wren 2021-11-28 03:16:45 +0000
  • 800b21d2f5 Remove event feedback path (not logical path) in priority encoder Luke Wren 2021-11-28 02:19:01 +0000
  • ba27dd838f Bump libfpga for correct bus error response from AHBL splitter in example SoC Luke Wren 2021-11-28 01:35:52 +0000
  • 47ce2cc8ec Add embench submodule, with configs for hazard3 Luke Wren 2021-11-28 00:01:18 +0000
  • 14a4f1a281 Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation Luke Wren 2021-11-27 17:19:34 +0000
  • 6f1a10724b Add bitmanip test vector generation script Luke Wren 2021-11-26 23:34:06 +0000
  • 5d093487b7 Update README Luke Wren 2021-11-26 23:33:46 +0000
  • 1bb7e33b69 Fix alignment of heap_ptr in init.S. Small ALU cleanup Luke Wren 2021-11-26 02:59:50 +0000
  • 7410c52aac Update readme Luke Wren 2021-11-26 02:09:39 +0000
  • 8398d7ecb6 Hook up Zb* extension params on iCEBreaker FPGA Luke Wren 2021-11-26 01:44:57 +0000
  • 8bcec11c80 Couple more silly mistakes Luke Wren 2021-11-26 01:30:13 +0000
  • 41eeb90c7d Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more Luke Wren 2021-11-26 01:29:47 +0000
  • 998f3fdeb7 Clean up silly mistakes Luke Wren 2021-11-26 00:55:57 +0000
  • 58c20a39d0 First pass at implementing bitmanip. Breaks CXXRTL. Ooop Luke Wren 2021-11-25 22:58:49 +0000
  • ed6b6a3660 Cleanup order of declaration/use of a couple of wires Luke Wren 2021-11-25 15:16:59 +0000
  • 2aac3d4f91 Add attempt at CPU backend diagram Luke Wren 2021-11-23 22:14:55 +0000
  • e352715fdf Fix IO decode in openocd/tb.cpp Luke Wren 2021-11-23 22:12:51 +0000
  • 49462a8642 Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh Luke Wren 2021-11-23 22:11:50 +0000
  • e05e9a4109 Add default_nettype none at top of every file, and default_nettype wire at bottom Luke Wren 2021-11-23 22:10:39 +0000
  • 0b9b706e81 Safer logic for load/store blocked by preceding WFI Luke Wren 2021-11-23 22:01:14 +0000
  • 4d14203586 Update riscv-tests fork for crash loop debug test Luke Wren 2021-11-23 21:58:31 +0000
  • 60f364e561 Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker Luke Wren 2021-11-21 15:55:52 +0000
  • ba9a7b4a03 Fix broken link in readme Luke Wren 2021-11-21 14:58:07 +0000
  • c1f17b0b23 Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench Luke Wren 2021-11-06 09:59:27 +0000
  • cc6a6c09ba Vaguely implement wfi Luke Wren 2021-11-05 18:48:27 +0000
  • 375a6d60b7 Correct mnemonic when logging unsigned sltiu instruction Richard-Gordon 2021-10-08 09:45:51 +0100
  • cfe16caf41 Remove some old todos Luke Wren 2021-09-05 22:20:40 +0100
  • e9fccffca0 Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC. Luke Wren 2021-09-05 04:45:38 +0100
  • 65bfca5fdf Fix latent bug with asynchronous debug entry during stalled load/store address phase Luke Wren 2021-09-04 07:49:29 +0100