d5cd3e0681
Add SBA patch-through to 1-core wrapper.
...
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
2022-07-03 15:17:44 +01:00
51bc26f8ac
First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
2022-07-03 00:25:47 +01:00
8ef9d77be8
Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations.
...
Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)
2022-06-25 13:11:40 +01:00
d9389fb23e
Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
2022-06-16 01:42:28 +01:00
d31b1708db
Make rvpy cycle-accurate enough to get the correct Dhrystone score
2022-06-09 01:34:37 +01:00
02b303b385
Remove stray old expected output file from sw_testcases dir
2022-06-03 17:20:49 +01:00
e2c9901701
Update readme for runtests
2022-05-30 01:12:16 +01:00
2cfe6aa90e
Add test to check MPRV/MPP behaviour when executing an MRET
2022-05-29 19:51:19 +01:00
f96a0ffb75
Add test for MPRV vs PMP
2022-05-29 19:06:04 +01:00
71eff7649d
Add PMP U-mode read/write permission test
2022-05-29 18:42:44 +01:00
c8afcdbb8f
Extend umode_wfi test to check U-mode WFI doesn't stall the processor if TW=0 or PMP X check fails
2022-05-29 17:42:15 +01:00
460fa0bb4a
Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.
2022-05-28 17:22:28 +01:00
66965ac073
Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
2022-05-28 15:36:21 +01:00
4090f4eb24
Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat
2022-05-28 15:01:27 +01:00
9e2f5df00a
Add testbench flag to propagate CPU return code to testbench return
2022-05-28 15:00:28 +01:00
81aec325bb
ecall from U-mode has a different mcause value than ecall from M-mode
2022-05-28 12:07:29 +01:00
632c61daba
Rebase debug tests, pick up two new tests (both pass)
2022-05-28 11:34:41 +01:00
f2876eb51f
Fix bad mepc reported after branching to a branch in a no-X address range
2022-05-27 22:47:04 +01:00
b655148148
Bump riscv-tests for better PMP disable fix
2022-05-27 21:36:54 +01:00
e208652ad7
Fix misa value in csr_id test
2022-05-26 00:48:12 +01:00
d7787942e9
Add two new tests to debug test list. Remainder are still non-applicable
2022-05-26 00:47:08 +01:00
a17b941e38
Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)
2022-05-25 23:46:23 +01:00
37f7588bad
Fix hazard3 reset vector check value in debug tests
2022-05-25 21:45:36 +01:00
5be8835365
Add missing output to pmp_write_and_lock test
2022-05-25 15:34:28 +01:00
399dcf2cb9
Add test for U-mode X permissions
2022-05-25 13:47:16 +01:00
7340765699
Add simple test to read, write and lock PMP registers
2022-05-25 02:05:24 +01:00
456810b09e
Make vcd generation optional in runtests
2022-05-24 22:56:13 +01:00
64d9f4a111
Add tests for execution of mret and wfi in U mode
2022-05-24 22:14:20 +01:00
20f06c4a02
Build tb with 4 PMP regions by default
2022-05-24 20:06:57 +01:00
7cfc976ef2
Set U RWX permission on all of memory in the U CSR readability test
2022-05-24 19:58:12 +01:00
cfed35b3da
Fix the stupid printf warning on x86-64 as well as arm64
2022-05-24 18:22:25 +01:00
f033cde874
Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
2022-05-24 17:30:24 +01:00
ba81b533d2
Build core with U mode support for tb
2022-05-24 16:44:22 +01:00
0199f48087
Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
2022-05-24 16:44:03 +01:00
4ba3f7ceb9
Fix format warning in tb.cpp on arm64
2022-05-24 16:17:54 +01:00
ef35dc859d
Add zicsr to march in makefiles
2022-05-24 16:17:54 +01:00
07d4b23a9a
Add option to pass test list to runtests
2022-05-24 16:17:54 +01:00
31061bd472
Add Zbkb to bitmanip tests and regenerate vectors
2022-05-21 17:15:46 +01:00
4ffe007a84
Add zicsr to march in bitmanip tests, so it builds on newer toolchains
2022-05-20 01:32:21 +01:00
7dc5046505
Perf option for dedicated branch comparator
2022-04-02 11:40:47 +01:00
3c61fae9ef
Remove the halfword fetch thing, was only really useful on RISCBoy
2022-04-02 10:54:16 +01:00
5aca1381ac
Couple of fixups for rvpy which I forgot to commit at some point
2022-03-01 20:27:18 +00:00
28b53ef7b5
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
2021-12-18 00:35:13 +00:00
a81d129961
Add exclusives monitor to testbench
2021-12-17 17:03:35 +00:00
5ab60422ad
Add minimal multicore launch code
2021-12-17 01:24:11 +00:00
01d9617f9c
Add multicore tb integration file
2021-12-17 00:41:23 +00:00
207566660d
tb: handle both ports identically. Preparing for dual core
2021-12-17 00:04:00 +00:00
88fea7acfa
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
2021-12-12 18:28:23 +00:00
719c21fec3
Add IRQ tests. Disable waves by default in runtests
2021-12-12 15:53:04 +00:00
9fb2af800f
Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
2021-12-12 14:58:50 +00:00
a232833d81
Add CSR writable test
2021-12-12 14:23:34 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
7da67a0600
Similarly for minstret
2021-12-11 22:25:12 +00:00
1b722b5f27
Add mcycle test, fix incorrect description of mcycle in docs
2021-12-11 21:21:31 +00:00
93eca19aeb
Add test for lr/sc RAW stalls
2021-12-11 19:16:41 +00:00
763a5cd364
Add test for readability of all implemented CSRs
2021-12-11 17:50:12 +00:00
7b1da32af1
Move expected_output into tests inline
2021-12-11 16:58:25 +00:00
9460b3cd04
Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
2021-12-11 15:52:34 +00:00
f64f44f7af
Add test for identification CSRs vs expected values
2021-12-11 13:26:59 +00:00
4066e941ef
Fix sim cmdline in bitmanip-random tests
2021-12-11 13:13:21 +00:00
3fe0d92d41
Add load/store alignment testcases
2021-12-11 12:53:37 +00:00
c90727b05a
Remove padding after vector table in init.S
2021-12-11 12:22:23 +00:00
6076eba61f
Add run_all script under riscv-compliance
2021-12-11 12:08:53 +00:00
6edfbfae8b
Add ebreak size/alignment test
2021-12-11 11:17:24 +00:00
abe1769929
Add instruction access fault testcase
2021-12-11 09:54:00 +00:00
933f2cd65c
Fix remaining fallout from tb args change
2021-12-11 09:53:39 +00:00
6d55cd2d55
Consolidate openocd and bin-load testbenches
2021-12-11 09:46:38 +00:00
fadb9601de
Illegal instruction test
2021-12-10 00:11:18 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
ac9285846f
Timer struct in IO header
2021-12-06 17:16:21 +00:00
c57a80f358
Add AMO + timer testcase
2021-12-06 07:47:20 +00:00
d86b2849c9
Bump to latest version of riscv-arch-test
2021-12-06 02:18:48 +00:00
df658d86ff
First plausibly working AMOs. Add AMOs to instruction timings list
2021-12-04 23:44:22 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
c5d6be24f3
Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
2021-12-04 14:06:48 +00:00
5db6c68c56
Update riscv-tests for correct misa.x value
2021-12-04 11:19:43 +00:00
52ba930638
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
2021-12-04 01:17:57 +00:00
be6b2f3f76
Fix up DTMs to use byte addressing
2021-12-02 02:05:23 +00:00
1ebccb7cce
Switch DM to use byte addresses on APB, not word addresses
2021-12-02 01:47:30 +00:00
fad64bb6c9
Bump embench test submodule
2021-11-29 18:51:10 +00:00
ba248c832a
init.S: also print out mcause when trapping an unhandled exception
2021-11-29 18:49:37 +00:00
c8afb4ac33
Add option for fast high-half multiplies
2021-11-29 18:48:02 +00:00
35c5e213c7
Bump embench for working benchmarks (except md5)
2021-11-29 00:59:14 +00:00
94a3d43f27
Add Hazard3's registered marchid value to hdl and docs
2021-11-28 19:53:49 +00:00
e7466ae4be
Move DM data0 CSR into the M-custom space, and document this
2021-11-28 15:52:52 +00:00
47ce2cc8ec
Add embench submodule, with configs for hazard3
2021-11-28 00:01:18 +00:00
14a4f1a281
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
2021-11-27 17:19:41 +00:00
6f1a10724b
Add bitmanip test vector generation script
2021-11-26 23:34:06 +00:00
1bb7e33b69
Fix alignment of heap_ptr in init.S. Small ALU cleanup
2021-11-26 02:59:50 +00:00
e352715fdf
Fix IO decode in openocd/tb.cpp
2021-11-23 22:12:51 +00:00
4d14203586
Update riscv-tests fork for crash loop debug test
2021-11-23 21:58:39 +00:00
c1f17b0b23
Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
2021-11-06 09:59:27 +00:00
375a6d60b7
Correct mnemonic when logging unsigned sltiu instruction
2021-10-08 12:02:37 +01:00
6fcc74a043
Add some instructions to Readme
2021-07-24 11:53:08 +01:00
b0d11c0ab7
Add RISC-V debug tests
2021-07-22 17:50:04 +01:00
c14960ee1b
Add mtime/mtimecmp to openocd testbench
2021-07-22 17:31:26 +01:00
5d2a562f65
Just use read_verilog; write_cxxrtl when building tb_cxxrtl
2021-07-22 17:30:30 +01:00
c56c75e14b
More dicking with yosys cmd for tb_cxxrtl;
...
Removing the prep pass as suggested leads to invalid VCD net names.
Adding a opt_clean (+ prerequisites) fixes that.
Adding splitnets -driver afterward wins back the performance lost by
that last addition. Can you tell I don't know what I'm doing
2021-07-18 16:46:00 +01:00
12bf9bb570
Make CXXRTL testbench ~25% faster
2021-07-18 16:04:19 +01:00
2618ae0c07
Double-step() after clock posedge to workaround CXXRTL port propagation issue
2021-07-18 16:03:53 +01:00
Luke Wren
Richard-Gordon
whitequark