c6d2b351df
Change clock from 12 to 25.
2025-04-06 19:47:55 +08:00
3255e9e952
Pass ECP5 fpga and jlink debug core.
2025-04-02 10:41:27 +08:00
b188194887
Add led output, refine io plan.
2025-04-01 18:11:04 +08:00
bf0e102e90
Add synth support.
2025-03-31 19:10:52 +08:00
2e649e2c86
Add softuart to soc_cxxrtl test.
2025-03-30 18:36:35 +08:00
464bd40440
Add softuart.
2025-03-30 16:23:29 +08:00
d2942fe094
Add uart software lib.
2025-03-30 00:21:49 +08:00
393499537d
Refine tb main.
2025-03-29 16:22:05 +08:00
aaad0d85a5
Enable aph port off soc, and print prints.
2025-03-27 23:48:10 +08:00
5ec810907e
Refine soc_cxxrtl and pass demo.
2025-03-27 16:02:09 +08:00
616da81d63
Add soc_cxxrtl simulation.
2025-03-26 16:28:09 +08:00
5e24d09fda
Fix up embench: use a relative link instead of the old env vars, and fix issues building with the recommended GCC14 configuration
2024-08-07 22:49:00 -07:00
c3913e13ca
Remove unused shell script for old riscv-arch-test
...
(to be picked up again after merging latest riscv-arch-test)
2024-08-07 22:33:15 -07:00
139671613a
Merge down latest riscv-tests. Seems fine, minimal conflicts.
2024-08-07 19:22:02 -07:00
dc21745d16
Hook up hello_multicore to automatically build and use the multicore testbench variant
2024-08-07 19:16:03 -07:00
422c0d32c6
riscv-tests: Update config files for new version of riscv-openocd (currently 5afed58)
2024-08-07 19:02:12 -07:00
42c4ac305b
Fix deprecation warning for tb openocd.cfg, and update example output in Readme.md
2024-08-07 16:44:43 -07:00
1cd5b7fed7
Temporarily disable two riscv-arch-test tests with known issues:
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* jalr-01 uses 'la x0' which is rejected as invalid by recent binutils
* cebreak-01 miscompares due to hardwired mtval (common upstream test issue)
Correct fix is blocked on bringing up the latest riscv-arch-test build
system for hazard3 (seems to have been completely rewritten again)
2024-08-07 16:13:44 -07:00
9c56e669cd
Standardise on a single ISA variant for default test builds, and align this with the lightweight toolchain config in the Readme
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(Automated test builds for multiple ISA variants still yet to be implemented)
2024-08-07 13:34:36 -07:00
0076b408fd
Update readme instructions for Ubuntu 24.04
2024-08-07 07:28:51 -07:00
35745117d9
Fix typo in src_only_app.mk
2024-06-06 08:33:55 +01:00
e34aa5bb45
rvcpp: implement MPRV, and fix up CSR write tracing
2024-06-02 12:46:41 +01:00
877c6aa5ee
Add trace disassembly annotation script for rvcpp, and add runtests support for passing flags to tb, and running post-processing commands on test results.
2024-06-02 11:20:58 +01:00
b026814674
runtests: use argparse for argument parsing, and support passing a different tb executable
2024-06-02 10:36:29 +01:00
a9ba69f4dd
Better default flags for CoreMark
2024-06-02 10:25:07 +01:00
a38981f989
Enable -Wextra for rvcpp
2024-06-02 10:18:40 +01:00
cbc2172930
rvcpp: Add Zcb support. Also fix -Wparentheses as sometimes it does find things
2024-06-02 10:15:57 +01:00
3a747e1dde
Disable zcmp in multilib-gen-gen for now, as it is still not supported in latest binutils release
2024-06-01 18:24:06 +01:00
b883be3c20
Update multilib-gen-gen for GCC14 extensions: Zicond, Zcmp, Zcb. Hopefully handle the Zca vs C thing gracefully.
2024-06-01 18:01:09 +01:00
7430523c45
Update .gitignore in riscv-tests to ignore output of debug tests
2024-06-01 15:53:53 +01:00
6da0e12bbd
Merge latest riscv-tests: updates for debug + ISA tests.
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Add a list of excluded tests, with reasons, to run-debug-tests.sh
2024-05-29 14:03:17 +01:00
d239de803c
Do not rely on environment variables for any intra-project paths
...
It's no longer necessary to source `sourceme` before running any
of the project Makefiles.
2024-05-27 16:53:06 +01:00
141da55507
tb: remove the WIDE_TIMER_IRQ flag in favour of always having the same tb interface. Second timer IRQ is ignored in single-core tb. Also, fix hmaster not being connected, which Verilator complains about.
2024-05-27 12:24:54 +01:00
5b31e26790
tb Makefile: use clang++-16 explicitly, because clang++-18 (now default on Ubuntu 24.04) has a >20x compile time regression
2024-05-27 11:06:50 +01:00
c550d79047
Debug tests: workaround recent GCC requiring Zicsr set for CSR instructions
2024-05-12 13:33:14 +01:00
a6558e554a
Set misa.b when all of Zba, Zbb and Zbs are enabled.
...
(The B extension has now been ratified as this combination of extensions.)
2024-05-11 12:13:35 +01:00
6db1edc675
Add dummy h3.msleep CSR to rvcpp
2024-05-11 11:02:01 +01:00
a84742abd4
Fix mstatus.mie still being respected when privilege is less than M.
...
Extend umode_wfi testcase to cover this, and in particular to check
that when entering U-mode with IRQs pending, the IRQs execute before any
exceptions occurring as a result of the U-mode instructions.
2024-05-11 10:49:13 +01:00
194c9a9052
Implement WFI in rvcpp. The umode_wfi test still does not pass, because it relies on a bug in Hazard3 (mstatus.mie disables IRQs in U-mode as well as M-mode, but is supposed to be ignored in U-mode).
2024-04-27 20:48:30 +01:00
78260e86e7
rvcpp: parameterise number of PMP regions, and set to match tb default. Fix region locking. Mask pmpaddr to 30 bits, to match Hazard3 32-bit physical address space.
2024-04-27 19:57:18 +01:00
ebe5a44454
rvcpp: fix up PMP address mask for all-ones pmpaddr, and raise instruction fault on instruction stradding two PMP regions, like the hardware
2024-04-27 19:34:17 +01:00
7d370292b0
Fix transposition of RWX <-> XWR in PMP implementation.
...
None of upstream tests used for Hazard3 seem to cover X != R. The
Hazard3 tests covered this case, but the header file for the tests has
the same mistake. Fix the header.
2024-04-27 13:52:43 +01:00
fce1c087d4
Add basic PMP implementation to rvcpp. Seems like the RWX vs XWR order might be transposed in both the hardware and the tests
2024-04-27 13:38:10 +01:00
117c52e7b1
rvcpp: fix handling of CSR instructions which both read and write
2024-04-27 13:30:34 +01:00
a313493371
Add timer and soft IRQ support to rvcpp. Relevant sw_testcases now pass.
2024-03-22 00:52:01 +00:00
b1be56fe94
Clean up rvcpp file structure
2024-03-21 23:27:01 +00:00
b473575b7e
rvcpp: correctly model memory access faults. relevant sw_testcases now pass.
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Also, grab the special-case core RAM change from the Sv32 fork, for better performance
2024-03-21 00:33:54 +00:00
fd584ea24b
Add Xh3bextm instructions to rvcpp, and rename xh3b test to xh3bextm
2024-03-20 23:45:30 +00:00
8cbf5fceee
rvcpp: fix busted RMW CSR logic, fix ordering of CSR write vs update, csr_mcycle testcase now passes
2024-03-20 01:37:04 +00:00
55504fa8f3
Add support for Zba, Zbb, Zbc, Zbs, Zbkb to rvcpp. Passes tests
2024-03-20 01:06:13 +00:00
Colin
Luke Wren