0b18fae32e
Fix swapped MHARTID/MCONFIGPTR values in tb configs
2022-10-08 08:42:50 +01:00
874cb20910
Add config headers to tb_cxxrtl instead of using defparams in Makefile
2022-10-08 08:09:26 +01:00
a18c3018e1
Bump riscv-formal to head of hazard3 branch, not sure what happened there
2022-10-07 01:35:10 +01:00
624d39669d
Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.
2022-08-29 19:20:09 +01:00
da4097ecd8
Delay pwrup_req->pwrup_ack in tb
2022-08-29 14:55:11 +01:00
954bae5cf1
Implement block/unblock instructions, and fix questionable partial masking of sleep signals on exceptions. Add simple test for self-block/unblock with loopback in tb.
2022-08-29 14:52:01 +01:00
2ae2463b97
First stab at adding wake/sleep state machine
2022-08-28 19:50:04 +01:00
bf38d93d33
Remove references to AHB-Lite, describe buses as (a subset of) AHB5
2022-08-28 14:15:20 +01:00
a79c857d82
Bump riscv-tests: enable hardware instruction breakpoints in hardware tests
2022-08-27 17:05:02 +01:00
04f138ae0e
Fix mcontrol.execute not being writable. Enable hardware breakpoint debug tests: Hwpb1/2, JumpHBreak, TriggerExecuteInstant
2022-08-23 00:05:30 +01:00
6e2076268c
Update CSR readability/writability tests for new CSRs
2022-08-22 08:50:57 +01:00
6e3799eed0
First attempt at hacking in triggers, at least seems to have not broken other exception logic. Not yet tested.
2022-08-22 08:47:03 +01:00
8b630d2ac6
Whoops I needed that constant
2022-08-10 01:00:47 +01:00
64dc31244e
Add top/bottom-half IRQ test
2022-08-10 00:09:13 +01:00
a44ff9b6f1
Add test for IRQ force array
2022-08-09 23:38:14 +01:00
5894ddf15c
Fix outdated expected output in irq_set_all_with_pri test
2022-08-08 18:44:58 +01:00
ad5fd24772
- Fix signal named priority, which is a keyword in SV
...
- Fix incorrect HIGHEST_WINS behaviour in one-hot selector
- Add test for asserting 32 IRQs at 16 priorities at once
- Add an entry counter to the soft dispatch code so tests can check
the number of times hardware entered the vector
2022-08-07 23:17:03 +01:00
2e3d69e98f
Forgot to add expected output for preemption test
2022-08-07 22:08:50 +01:00
5e72ec8941
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test
2022-08-07 22:04:42 +01:00
15cb21ae43
First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)
2022-08-07 20:51:12 +01:00
185194973f
Add a custom instruction (bextm/bextmi: 1 to 8-bit version of bext/bexti from Zbs) for fooling around with toolchains
2022-08-06 23:02:08 +01:00
9787c604ad
Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)
2022-07-30 17:31:53 +01:00
ee7d8e1947
Bump embench for script fixes/improvements
2022-07-07 18:29:37 +01:00
91be98f2da
Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)
2022-07-06 23:53:11 +01:00
5a39d8b7e7
Track minstret and mcycle separately now that the model is cycle-accurate
2022-07-06 13:50:13 +01:00
5dfe5cb62b
Update rvpy to match current fastest config: stage 2 mul, single BTB entry on backward branches
2022-07-06 13:49:51 +01:00
b7d9defcf2
Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3
2022-07-05 03:37:19 +01:00
27793b25a1
Rebase riscv-tests against upstream, and pick up new semihosting file io test
2022-07-04 00:45:20 +01:00
e44d2e6f9e
Add memory sampling to run-debug-tests. Add run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix for MemorySampleMixed
2022-07-03 23:34:12 +01:00
b1225c386c
Add missing 1port SBA change, and update example soc and bus compliance tb to reflect
2022-07-03 17:57:03 +01:00
9e15cd3485
Add standalone SBA-to-AHB shim, and make SBA off by default in the DM
2022-07-03 15:30:33 +01:00
d5cd3e0681
Add SBA patch-through to 1-core wrapper.
...
Add SBA properties to bus compliance checks.
Hook up SBA in dual-core single-port debug tb.
2022-07-03 15:17:44 +01:00
51bc26f8ac
First pass at adding system bus access to DM. Currently only the 2-port processor supports SBA patchthrough.
2022-07-03 00:25:47 +01:00
a7cb214501
Reduce ROM size in instruction_fetch_match: depth is more useful
2022-06-26 19:59:44 +01:00
5193dfe477
Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,
...
and enable it only on the bus compliance model checks. Trying to make
the solver's life easier in instruction_fetch_match.
2022-06-25 20:08:40 +01:00
8ef9d77be8
Add 'everything but MHARTID' option to config_inst, to allow its reuse in multicore instantiations.
...
Use this to fix the multicore tb not instantiating cores with all parameters correct (e.g. U_MODE)
2022-06-25 13:11:40 +01:00
d9389fb23e
Fix a half-valid valid address phase being left behind when taking a new path with the jump going straight to the bus. If left in place, this causes the next-next fetch to be marked as half valid, corrupting fetch data.
2022-06-16 01:42:28 +01:00
f8aad6d2f3
Fix some bugs, too tired to list them, look at the diff
2022-06-15 04:05:31 +01:00
0766ec6f8a
First pass at adding branch prediction
2022-06-15 02:05:46 +01:00
3703b1fc4c
Allow use of cir_flush_behind in frontend_match formal tb
2022-06-13 20:36:15 +01:00
e68d8a6cd6
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
2022-06-13 01:23:32 +01:00
23b4dbe7f3
Redesign fetch queue: 2x32 + 3x16 -> 6x16.
...
Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
2022-06-12 02:44:08 +01:00
d5a202e4a5
Add standalone frontend formal tb
2022-06-11 20:14:24 +01:00
d31b1708db
Make rvpy cycle-accurate enough to get the correct Dhrystone score
2022-06-09 01:34:37 +01:00
02b303b385
Remove stray old expected output file from sw_testcases dir
2022-06-03 17:20:49 +01:00
e2c9901701
Update readme for runtests
2022-05-30 01:12:16 +01:00
2cfe6aa90e
Add test to check MPRV/MPP behaviour when executing an MRET
2022-05-29 19:51:19 +01:00
f96a0ffb75
Add test for MPRV vs PMP
2022-05-29 19:06:04 +01:00
71eff7649d
Add PMP U-mode read/write permission test
2022-05-29 18:42:44 +01:00
c8afcdbb8f
Extend umode_wfi test to check U-mode WFI doesn't stall the processor if TW=0 or PMP X check fails
2022-05-29 17:42:15 +01:00
460fa0bb4a
Fix run-isa-tests.sh to fail on first failed test. Fix bad environment trap routing causing ecall ISA test to hang. Make breakpoint test instant-pass when triggers aren't implemented.
2022-05-28 17:22:28 +01:00
66965ac073
Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
2022-05-28 15:36:21 +01:00
4090f4eb24
Initial bringup of riscv-tests. Pass 63 out of 66 applicable tests.gstat
2022-05-28 15:01:27 +01:00
9e2f5df00a
Add testbench flag to propagate CPU return code to testbench return
2022-05-28 15:00:28 +01:00
81aec325bb
ecall from U-mode has a different mcause value than ecall from M-mode
2022-05-28 12:07:29 +01:00
632c61daba
Rebase debug tests, pick up two new tests (both pass)
2022-05-28 11:34:41 +01:00
f2876eb51f
Fix bad mepc reported after branching to a branch in a no-X address range
2022-05-27 22:47:04 +01:00
cd3125b6e5
Add new bus signals on instruction_fetch_match/tb.v
2022-05-27 21:48:45 +01:00
b655148148
Bump riscv-tests for better PMP disable fix
2022-05-27 21:36:54 +01:00
e208652ad7
Fix misa value in csr_id test
2022-05-26 00:48:12 +01:00
d7787942e9
Add two new tests to debug test list. Remainder are still non-applicable
2022-05-26 00:47:08 +01:00
a17b941e38
Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)
2022-05-25 23:46:23 +01:00
37f7588bad
Fix hazard3 reset vector check value in debug tests
2022-05-25 21:45:36 +01:00
5be8835365
Add missing output to pmp_write_and_lock test
2022-05-25 15:34:28 +01:00
399dcf2cb9
Add test for U-mode X permissions
2022-05-25 13:47:16 +01:00
7340765699
Add simple test to read, write and lock PMP registers
2022-05-25 02:05:24 +01:00
456810b09e
Make vcd generation optional in runtests
2022-05-24 22:56:13 +01:00
64d9f4a111
Add tests for execution of mret and wfi in U mode
2022-05-24 22:14:20 +01:00
20f06c4a02
Build tb with 4 PMP regions by default
2022-05-24 20:06:57 +01:00
7cfc976ef2
Set U RWX permission on all of memory in the U CSR readability test
2022-05-24 19:58:12 +01:00
cfed35b3da
Fix the stupid printf warning on x86-64 as well as arm64
2022-05-24 18:22:25 +01:00
f033cde874
Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
2022-05-24 17:30:24 +01:00
ba81b533d2
Build core with U mode support for tb
2022-05-24 16:44:22 +01:00
0199f48087
Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
2022-05-24 16:44:03 +01:00
4ba3f7ceb9
Fix format warning in tb.cpp on arm64
2022-05-24 16:17:54 +01:00
ef35dc859d
Add zicsr to march in makefiles
2022-05-24 16:17:54 +01:00
07d4b23a9a
Add option to pass test list to runtests
2022-05-24 16:17:54 +01:00
31061bd472
Add Zbkb to bitmanip tests and regenerate vectors
2022-05-21 17:15:46 +01:00
4ffe007a84
Add zicsr to march in bitmanip tests, so it builds on newer toolchains
2022-05-20 01:32:21 +01:00
4946248dc4
RVFI monitor: blank out instructions which experienced an instruction fetch fault.
...
(previous monitor logic was ok when fetch faults weren't implemented.
If the blanked instruction has side effects, these will break other test
properties, which we would detect.)
2022-04-12 13:38:19 +01:00
8a61fe5243
Fix RVFI monitor assuming rs2 data is equivalent to store data
...
(this used to be true, but was re-plumbed when optimising A extension implementation)
2022-04-12 13:27:53 +01:00
9e27db0884
Connect or tie off missing ports on RVFI wrapper
2022-04-12 13:27:03 +01:00
7dc5046505
Perf option for dedicated branch comparator
2022-04-02 11:40:47 +01:00
3c61fae9ef
Remove the halfword fetch thing, was only really useful on RISCBoy
2022-04-02 10:54:16 +01:00
5aca1381ac
Couple of fixups for rvpy which I forgot to commit at some point
2022-03-01 20:27:18 +00:00
0a369efc06
Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
2021-12-18 15:41:05 +00:00
1b0e205f87
Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami
2021-12-18 14:51:46 +00:00
28b53ef7b5
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
2021-12-18 00:35:13 +00:00
a81d129961
Add exclusives monitor to testbench
2021-12-17 17:03:35 +00:00
5ab60422ad
Add minimal multicore launch code
2021-12-17 01:24:11 +00:00
01d9617f9c
Add multicore tb integration file
2021-12-17 00:41:23 +00:00
207566660d
tb: handle both ports identically. Preparing for dual core
2021-12-17 00:04:00 +00:00
88fea7acfa
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
2021-12-12 18:28:23 +00:00
719c21fec3
Add IRQ tests. Disable waves by default in runtests
2021-12-12 15:53:04 +00:00
9fb2af800f
Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
2021-12-12 14:58:50 +00:00
a232833d81
Add CSR writable test
2021-12-12 14:23:34 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
7da67a0600
Similarly for minstret
2021-12-11 22:25:12 +00:00
1b722b5f27
Add mcycle test, fix incorrect description of mcycle in docs
2021-12-11 21:21:31 +00:00
93eca19aeb
Add test for lr/sc RAW stalls
2021-12-11 19:16:41 +00:00
763a5cd364
Add test for readability of all implemented CSRs
2021-12-11 17:50:12 +00:00
7b1da32af1
Move expected_output into tests inline
2021-12-11 16:58:25 +00:00
9460b3cd04
Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
2021-12-11 15:52:34 +00:00
f64f44f7af
Add test for identification CSRs vs expected values
2021-12-11 13:26:59 +00:00
4066e941ef
Fix sim cmdline in bitmanip-random tests
2021-12-11 13:13:21 +00:00
3fe0d92d41
Add load/store alignment testcases
2021-12-11 12:53:37 +00:00
c90727b05a
Remove padding after vector table in init.S
2021-12-11 12:22:23 +00:00
6076eba61f
Add run_all script under riscv-compliance
2021-12-11 12:08:53 +00:00
52d58fdee4
Add keep wires for debug port on bus compliance tb
2021-12-11 12:06:10 +00:00
6edfbfae8b
Add ebreak size/alignment test
2021-12-11 11:17:24 +00:00
abe1769929
Add instruction access fault testcase
2021-12-11 09:54:00 +00:00
933f2cd65c
Fix remaining fallout from tb args change
2021-12-11 09:53:39 +00:00
6d55cd2d55
Consolidate openocd and bin-load testbenches
2021-12-11 09:46:38 +00:00
fadb9601de
Illegal instruction test
2021-12-10 00:11:18 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
dbc331dbb4
Add exclusives bus properties
2021-12-07 05:47:25 +00:00
93be227d8a
Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
2021-12-06 20:12:23 +00:00
ac9285846f
Timer struct in IO header
2021-12-06 17:16:21 +00:00
c57a80f358
Add AMO + timer testcase
2021-12-06 07:47:20 +00:00
d86b2849c9
Bump to latest version of riscv-arch-test
2021-12-06 02:18:48 +00:00
df658d86ff
First plausibly working AMOs. Add AMOs to instruction timings list
2021-12-04 23:44:22 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
c5d6be24f3
Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
2021-12-04 14:06:48 +00:00
5db6c68c56
Update riscv-tests for correct misa.x value
2021-12-04 11:19:43 +00:00
52ba930638
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
2021-12-04 01:17:57 +00:00
be6b2f3f76
Fix up DTMs to use byte addressing
2021-12-02 02:05:23 +00:00
1ebccb7cce
Switch DM to use byte addresses on APB, not word addresses
2021-12-02 01:47:30 +00:00
fad64bb6c9
Bump embench test submodule
2021-11-29 18:51:10 +00:00
ba248c832a
init.S: also print out mcause when trapping an unhandled exception
2021-11-29 18:49:37 +00:00
c8afb4ac33
Add option for fast high-half multiplies
2021-11-29 18:48:02 +00:00
35c5e213c7
Bump embench for working benchmarks (except md5)
2021-11-29 00:59:14 +00:00
94a3d43f27
Add Hazard3's registered marchid value to hdl and docs
2021-11-28 19:53:49 +00:00
e7466ae4be
Move DM data0 CSR into the M-custom space, and document this
2021-11-28 15:52:52 +00:00
47ce2cc8ec
Add embench submodule, with configs for hazard3
2021-11-28 00:01:18 +00:00
14a4f1a281
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
2021-11-27 17:19:41 +00:00
6f1a10724b
Add bitmanip test vector generation script
2021-11-26 23:34:06 +00:00
1bb7e33b69
Fix alignment of heap_ptr in init.S. Small ALU cleanup
2021-11-26 02:59:50 +00:00
e352715fdf
Fix IO decode in openocd/tb.cpp
2021-11-23 22:12:51 +00:00
4d14203586
Update riscv-tests fork for crash loop debug test
2021-11-23 21:58:39 +00:00
c1f17b0b23
Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
2021-11-06 09:59:27 +00:00
375a6d60b7
Correct mnemonic when logging unsigned sltiu instruction
2021-10-08 12:02:37 +01:00
6fcc74a043
Add some instructions to Readme
2021-07-24 11:53:08 +01:00
b0d11c0ab7
Add RISC-V debug tests
2021-07-22 17:50:04 +01:00
c14960ee1b
Add mtime/mtimecmp to openocd testbench
2021-07-22 17:31:26 +01:00
5d2a562f65
Just use read_verilog; write_cxxrtl when building tb_cxxrtl
2021-07-22 17:30:30 +01:00
c56c75e14b
More dicking with yosys cmd for tb_cxxrtl;
...
Removing the prep pass as suggested leads to invalid VCD net names.
Adding a opt_clean (+ prerequisites) fixes that.
Adding splitnets -driver afterward wins back the performance lost by
that last addition. Can you tell I don't know what I'm doing
2021-07-18 16:46:00 +01:00
12bf9bb570
Make CXXRTL testbench ~25% faster
2021-07-18 16:04:19 +01:00
2618ae0c07
Double-step() after clock posedge to workaround CXXRTL port propagation issue
2021-07-18 16:03:53 +01:00
ce5cc1f150
oops, bounds checking on free-running tb_cxxrtl
2021-07-18 15:20:25 +01:00
Luke Wren
Richard-Gordon
whitequark