456810b09e
Make vcd generation optional in runtests
2022-05-24 22:56:13 +01:00
64d9f4a111
Add tests for execution of mret and wfi in U mode
2022-05-24 22:14:20 +01:00
20f06c4a02
Build tb with 4 PMP regions by default
2022-05-24 20:06:57 +01:00
7cfc976ef2
Set U RWX permission on all of memory in the U CSR readability test
2022-05-24 19:58:12 +01:00
cfed35b3da
Fix the stupid printf warning on x86-64 as well as arm64
2022-05-24 18:22:25 +01:00
f033cde874
Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
2022-05-24 17:30:24 +01:00
ba81b533d2
Build core with U mode support for tb
2022-05-24 16:44:22 +01:00
0199f48087
Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
2022-05-24 16:44:03 +01:00
4ba3f7ceb9
Fix format warning in tb.cpp on arm64
2022-05-24 16:17:54 +01:00
ef35dc859d
Add zicsr to march in makefiles
2022-05-24 16:17:54 +01:00
07d4b23a9a
Add option to pass test list to runtests
2022-05-24 16:17:54 +01:00
31061bd472
Add Zbkb to bitmanip tests and regenerate vectors
2022-05-21 17:15:46 +01:00
4ffe007a84
Add zicsr to march in bitmanip tests, so it builds on newer toolchains
2022-05-20 01:32:21 +01:00
4946248dc4
RVFI monitor: blank out instructions which experienced an instruction fetch fault.
...
(previous monitor logic was ok when fetch faults weren't implemented.
If the blanked instruction has side effects, these will break other test
properties, which we would detect.)
2022-04-12 13:38:19 +01:00
8a61fe5243
Fix RVFI monitor assuming rs2 data is equivalent to store data
...
(this used to be true, but was re-plumbed when optimising A extension implementation)
2022-04-12 13:27:53 +01:00
9e27db0884
Connect or tie off missing ports on RVFI wrapper
2022-04-12 13:27:03 +01:00
7dc5046505
Perf option for dedicated branch comparator
2022-04-02 11:40:47 +01:00
3c61fae9ef
Remove the halfword fetch thing, was only really useful on RISCBoy
2022-04-02 10:54:16 +01:00
5aca1381ac
Couple of fixups for rvpy which I forgot to commit at some point
2022-03-01 20:27:18 +00:00
0a369efc06
Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
2021-12-18 15:41:05 +00:00
1b0e205f87
Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami
2021-12-18 14:51:46 +00:00
28b53ef7b5
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
2021-12-18 00:35:13 +00:00
a81d129961
Add exclusives monitor to testbench
2021-12-17 17:03:35 +00:00
5ab60422ad
Add minimal multicore launch code
2021-12-17 01:24:11 +00:00
01d9617f9c
Add multicore tb integration file
2021-12-17 00:41:23 +00:00
207566660d
tb: handle both ports identically. Preparing for dual core
2021-12-17 00:04:00 +00:00
88fea7acfa
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
2021-12-12 18:28:23 +00:00
719c21fec3
Add IRQ tests. Disable waves by default in runtests
2021-12-12 15:53:04 +00:00
9fb2af800f
Allow IRQs to be set/cleared by sw in tb. Add soft IRQ test
2021-12-12 14:58:50 +00:00
a232833d81
Add CSR writable test
2021-12-12 14:23:34 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
7da67a0600
Similarly for minstret
2021-12-11 22:25:12 +00:00
1b722b5f27
Add mcycle test, fix incorrect description of mcycle in docs
2021-12-11 21:21:31 +00:00
93eca19aeb
Add test for lr/sc RAW stalls
2021-12-11 19:16:41 +00:00
763a5cd364
Add test for readability of all implemented CSRs
2021-12-11 17:50:12 +00:00
7b1da32af1
Move expected_output into tests inline
2021-12-11 16:58:25 +00:00
9460b3cd04
Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
2021-12-11 15:52:34 +00:00
f64f44f7af
Add test for identification CSRs vs expected values
2021-12-11 13:26:59 +00:00
4066e941ef
Fix sim cmdline in bitmanip-random tests
2021-12-11 13:13:21 +00:00
3fe0d92d41
Add load/store alignment testcases
2021-12-11 12:53:37 +00:00
c90727b05a
Remove padding after vector table in init.S
2021-12-11 12:22:23 +00:00
6076eba61f
Add run_all script under riscv-compliance
2021-12-11 12:08:53 +00:00
52d58fdee4
Add keep wires for debug port on bus compliance tb
2021-12-11 12:06:10 +00:00
6edfbfae8b
Add ebreak size/alignment test
2021-12-11 11:17:24 +00:00
abe1769929
Add instruction access fault testcase
2021-12-11 09:54:00 +00:00
933f2cd65c
Fix remaining fallout from tb args change
2021-12-11 09:53:39 +00:00
6d55cd2d55
Consolidate openocd and bin-load testbenches
2021-12-11 09:46:38 +00:00
fadb9601de
Illegal instruction test
2021-12-10 00:11:18 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
dbc331dbb4
Add exclusives bus properties
2021-12-07 05:47:25 +00:00
93be227d8a
Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
2021-12-06 20:12:23 +00:00
ac9285846f
Timer struct in IO header
2021-12-06 17:16:21 +00:00
c57a80f358
Add AMO + timer testcase
2021-12-06 07:47:20 +00:00
d86b2849c9
Bump to latest version of riscv-arch-test
2021-12-06 02:18:48 +00:00
df658d86ff
First plausibly working AMOs. Add AMOs to instruction timings list
2021-12-04 23:44:22 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
c5d6be24f3
Remove external IRQ vectors from init.S which are unreachable now that midcr.eivect has been removed.
2021-12-04 14:06:48 +00:00
5db6c68c56
Update riscv-tests for correct misa.x value
2021-12-04 11:19:43 +00:00
52ba930638
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
2021-12-04 01:17:57 +00:00
be6b2f3f76
Fix up DTMs to use byte addressing
2021-12-02 02:05:23 +00:00
1ebccb7cce
Switch DM to use byte addresses on APB, not word addresses
2021-12-02 01:47:30 +00:00
fad64bb6c9
Bump embench test submodule
2021-11-29 18:51:10 +00:00
ba248c832a
init.S: also print out mcause when trapping an unhandled exception
2021-11-29 18:49:37 +00:00
c8afb4ac33
Add option for fast high-half multiplies
2021-11-29 18:48:02 +00:00
35c5e213c7
Bump embench for working benchmarks (except md5)
2021-11-29 00:59:14 +00:00
94a3d43f27
Add Hazard3's registered marchid value to hdl and docs
2021-11-28 19:53:49 +00:00
e7466ae4be
Move DM data0 CSR into the M-custom space, and document this
2021-11-28 15:52:52 +00:00
47ce2cc8ec
Add embench submodule, with configs for hazard3
2021-11-28 00:01:18 +00:00
14a4f1a281
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
2021-11-27 17:19:41 +00:00
6f1a10724b
Add bitmanip test vector generation script
2021-11-26 23:34:06 +00:00
1bb7e33b69
Fix alignment of heap_ptr in init.S. Small ALU cleanup
2021-11-26 02:59:50 +00:00
e352715fdf
Fix IO decode in openocd/tb.cpp
2021-11-23 22:12:51 +00:00
4d14203586
Update riscv-tests fork for crash loop debug test
2021-11-23 21:58:39 +00:00
c1f17b0b23
Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench
2021-11-06 09:59:27 +00:00
375a6d60b7
Correct mnemonic when logging unsigned sltiu instruction
2021-10-08 12:02:37 +01:00
6fcc74a043
Add some instructions to Readme
2021-07-24 11:53:08 +01:00
b0d11c0ab7
Add RISC-V debug tests
2021-07-22 17:50:04 +01:00
c14960ee1b
Add mtime/mtimecmp to openocd testbench
2021-07-22 17:31:26 +01:00
5d2a562f65
Just use read_verilog; write_cxxrtl when building tb_cxxrtl
2021-07-22 17:30:30 +01:00
c56c75e14b
More dicking with yosys cmd for tb_cxxrtl;
...
Removing the prep pass as suggested leads to invalid VCD net names.
Adding a opt_clean (+ prerequisites) fixes that.
Adding splitnets -driver afterward wins back the performance lost by
that last addition. Can you tell I don't know what I'm doing
2021-07-18 16:46:00 +01:00
12bf9bb570
Make CXXRTL testbench ~25% faster
2021-07-18 16:04:19 +01:00
2618ae0c07
Double-step() after clock posedge to workaround CXXRTL port propagation issue
2021-07-18 16:03:53 +01:00
ce5cc1f150
oops, bounds checking on free-running tb_cxxrtl
2021-07-18 15:20:25 +01:00
8014239d47
openocd tb: report AHB error response when processor accesses outside of RAM/IO
2021-07-17 19:26:05 +01:00
ab0b4a04f0
Also support progbuf in abstractauto.
2021-07-17 15:08:00 +01:00
62822b2e1d
Couple of usability improvements for openocd testbench
2021-07-15 19:42:49 +01:00
9643a57ba9
Slightly less braindead TCP interactions for openocd JTAG bitbang testbench, much more interactive now
2021-07-14 19:20:27 +01:00
307955c810
Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
2021-07-13 01:10:55 +01:00
42632e325a
Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core
2021-07-12 21:21:16 +01:00
f7b3097ad6
Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works
2021-07-11 16:20:39 +01:00
5cc483898d
Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
2021-07-10 21:02:18 +01:00
58a6b8b4c8
Add 32IM testlist
2021-06-05 12:03:05 +01:00
be79a611e1
Increasing p2align on vectors from 8 to 12 (as it was originally) makes coremark go back up from 2.91 to 2.92. Still mystified as to why.
2021-06-04 09:19:18 +01:00
c03bc2efb5
Update init.S for new IRQ functionality
2021-06-04 08:16:54 +01:00
12851d3742
Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
2021-05-30 19:52:46 +01:00
12205f12c7
Add instruction fetch match check
2021-05-30 11:22:36 +01:00
16dc905dce
Add simple formal bus properties check
2021-05-30 10:19:42 +01:00
2330b84b73
Use .f for riscv-formal tb dependencies, small reshuffling of directories
2021-05-30 09:44:57 +01:00
089bcc7c43
Typo
2021-05-29 23:24:18 +01:00
1b252d4bda
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
2021-05-23 11:59:46 +01:00
90acfdcbe8
Organise test directory into formal and sim
2021-05-23 07:42:35 +01:00
08e986912c
Also fix RAW stall on JALR instructions, oops. Runs CoreMark and Dhrystone now
2021-05-22 11:18:56 +01:00
cc6f590f2e
Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still
2021-05-22 10:16:02 +01:00
692abbad8b
Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
2021-05-22 07:55:13 +01:00
844fa8f97f
Rename hazard5 -> hazard3
2021-05-21 03:46:29 +01:00
6dad4e20bb
Import from hazard5 9743a1b
2021-05-21 02:34:16 +01:00
Luke Wren
Richard-Gordon
whitequark