0766ec6f8a
First pass at adding branch prediction
2022-06-15 02:05:46 +01:00
3703b1fc4c
Allow use of cir_flush_behind in frontend_match formal tb
2022-06-13 20:36:15 +01:00
e68d8a6cd6
Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.
2022-06-13 01:23:32 +01:00
26d54d0023
Re-rewrite frontend to track the halfword-validity of in-flight transfers, and clean up the old cir_lock mechanism to be a modified flush
2022-06-12 21:01:39 +01:00
e3da922f8b
Revert previous frontend changes. Seemed promising but is a dead end for area.
...
The original frontend design can probably be tweaked to support predictions.
2022-06-12 16:25:42 +01:00
940b7e4009
Actually still need 7 halfwords for full throughput in the case of sequential word-sized halfword-aligned instructions
2022-06-12 16:21:56 +01:00
8458dff083
Fix bus errors not being applied in frontend
2022-06-12 05:28:21 +01:00
23b4dbe7f3
Redesign fetch queue: 2x32 + 3x16 -> 6x16.
...
Should make it easier to support finer-grained flushing,
and handle predicted branches cleanly.
2022-06-12 02:44:08 +01:00
d5a202e4a5
Add standalone frontend formal tb
2022-06-11 20:14:24 +01:00
3b5879da66
Small code cleanup in frontend. The address phase alignment state no longer needs to be tracked, since we just generate word accesses always, for simplicity.
2022-06-11 14:27:59 +01:00
de9b51b787
Remove default zeroing of fetch address when no fetch is asserted -- this puts LUTs on a critical path and arguably causes more toggling than asserting the sequentially next address by default.
2022-06-11 14:26:40 +01:00
11596a5bd7
Remove unused/untested RISC-V timer implementation
2022-06-09 00:12:26 +01:00
ea2b8888a4
Update copyright years
2022-06-09 00:12:01 +01:00
ae2784d0ea
PMP config: separate granularity config from hardwired region config. Give correct read value for G > 1.
2022-06-03 17:09:43 +01:00
e0a9fb7312
Add option to hardwire PMP regions, or reduce their granularity
2022-06-03 01:19:03 +01:00
66965ac073
Fix inverted sc return code (argh) and lr/sc tests which also assumed the sc code was inverted
2022-05-28 15:36:21 +01:00
81aec325bb
ecall from U-mode has a different mcause value than ecall from M-mode
2022-05-28 12:07:29 +01:00
f2876eb51f
Fix bad mepc reported after branching to a branch in a no-X address range
2022-05-27 22:47:04 +01:00
0e462574b2
Move declaration of x_exec_pmp_fail to before its first use
2022-05-27 15:04:43 +01:00
156fbcd019
Update behaviour of mstatus.mpp and mprv on mret to match priv-1.12 spec
2022-05-26 00:42:50 +01:00
a17b941e38
Add U bit to misa, and fix some broken debug tests (no hazard3 bugs)
2022-05-25 23:46:23 +01:00
0efcf53fe5
Fix X PMP fail not suppressing load/store address phase.
...
Fix PMP-failed load/store still passing on a data phase tag to stage 3.
Fix WFI still pausing the core after a PMP X fail.
2022-05-25 16:18:03 +01:00
e2b9a3b2f9
Fix two PMP-related bugs:
...
1. Generating PMP load/store exceptions when the instruction is not a load/store
2. Passing a PMP exec permission exception into M whilst the frontend is still
starved, causing early taking of the exception and a bad mepc value.
2022-05-25 13:23:44 +01:00
51750eb81d
Add mstatus.tw to control U-mode WFI, and prevent mret execution in U-mode.
2022-05-24 21:12:44 +01:00
c93228d13e
Integrate PMP, and fix a couple of PMP bugs
2022-05-24 19:57:45 +01:00
4878a752d6
Plumb privilege state through to the bus ports
2022-05-24 18:24:34 +01:00
f033cde874
Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
2022-05-24 17:30:24 +01:00
0199f48087
Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
2022-05-24 16:44:03 +01:00
d62861159f
First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
2022-05-24 16:17:54 +01:00
2df1179994
Wire privilege through from core to bus masters. Tied off inside core.
2022-05-24 14:05:26 +01:00
c0b5d73cbd
Typo in for loop, surprised Yosys accepted this
2022-05-23 18:15:36 +01:00
5466c8131e
Sketch in PMP implementation
2022-05-23 18:06:23 +01:00
06647b78c6
Fix IALIGN fault to trap on the control flow instruction instead of its target
2022-05-23 16:25:43 +01:00
da244f54c3
Remove unused FAKE_DUALPORT option from regfile
2022-05-23 16:22:01 +01:00
f849517202
Split CSR addresses into separate header file
2022-05-23 15:54:37 +01:00
5f4127948d
Add a parameter to control register file reset, instead of the weird ifdef tree
2022-05-23 13:29:44 +01:00
df0fd536eb
Fix IRQ priority to match the priv spec
2022-05-23 12:56:37 +01:00
96a9ee18e1
Add IALIGN exception to non-RVC implementations
2022-05-23 12:47:48 +01:00
c4e81922da
Don't store bit 1 of mepc on non-RVC implementations
2022-05-23 12:27:07 +01:00
210dbeae64
Correct the name and operation of the brev8 (formerly rev.b) instruction
2022-05-20 15:28:18 +01:00
a2582976fc
Fix opcodes for zip/unzip, which are wrong in the bitmanip copy of the Zbkb spec, but correct in the crypto copy of that spec
2022-05-20 15:15:37 +01:00
43e0b1d16a
Implement Zbkb (untested)
2022-05-06 17:36:25 +01:00
2c8f3974d0
Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i.
2022-04-09 13:49:16 +01:00
35651f52a7
Stronger property for correct predecode
2022-04-05 08:18:00 +01:00
20cf408632
Add fine (as well as coarse) register predecode, so that predecoded regnum can be used in bypass zeroing.
2022-04-04 20:16:19 +01:00
357efac66e
Don't decode unnecessary bits in register predecode logic
2022-04-04 18:22:09 +01:00
be80bd4c18
Radical opinion, we should have good performance by default, not bad
2022-04-02 17:53:22 +01:00
7dc5046505
Perf option for dedicated branch comparator
2022-04-02 11:40:47 +01:00
3c61fae9ef
Remove the halfword fetch thing, was only really useful on RISCBoy
2022-04-02 10:54:16 +01:00
7b8fe43c1c
Fix bad timing of predecoded regnum register update (thanks BMC)
2022-04-02 10:11:55 +01:00
b80b09afe5
Typo -- fully encode all 128 possible IRQs
2022-03-15 09:01:55 +00:00
b0b8703ea4
Support up to 128 IRQs
2022-03-13 09:27:43 +00:00
887c93dbf0
Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
2022-03-02 18:35:16 +00:00
96c69d0bb0
Cut in->out paths on debug halt/resume request
...
Should be harmless, because in practice these should always be driven from a register
in the DM, but still better to cut the path
2022-03-01 21:14:49 +00:00
8fbffbe133
Assign full width of fifo_valid in non-reset clause (cosmetic fix)
2022-02-24 12:00:27 +00:00
9ed99d8695
Use define to guard X-checks, instead of hot comments
2022-02-24 10:35:16 +00:00
bf15b6c49f
Fix forward reference to net
2022-01-18 23:02:39 +00:00
0a369efc06
Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
2021-12-18 15:41:05 +00:00
1b0e205f87
Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami
2021-12-18 14:51:46 +00:00
6b8d4913ee
Remove unnecessary mux of mw_result -> m_result
2021-12-18 01:34:25 +00:00
79fec3a2f5
Overload mw_result register for capturing AMO read data. Save some LCs.
2021-12-18 01:24:26 +00:00
28b53ef7b5
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
2021-12-18 00:35:13 +00:00
7485269ddf
Use the branch target adder for load/store addresses. Preparing for AMO ALU deletion
2021-12-17 22:36:40 +00:00
a35739baf1
Fix AMO failing to loop on global monitor write fail
2021-12-17 17:04:22 +00:00
b0d28447ab
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
f1cda26bcc
Oops, try a little harder this time to ensure local monitor is cleared by sc.w errors _always_, even if lined up with trap entry stalls etc
2021-12-12 23:32:01 +00:00
25b44d04cf
Add more properties wrt AMO. Fix awful bugs in interaction between AMOs and prior lr/sc, prior load/store exception, or IRQ which is asserted then deasserted. Fix sc with HRESP=1 HEXOKAY=1 not clearing the local monitor (not a bug, but unfriendly).
2021-12-12 23:24:25 +00:00
88fea7acfa
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
2021-12-12 18:28:23 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
2bbc3637a2
Simplify CSR update logic. Showed promise in block synth but no difference to example soc. Still cleaner RTL.
2021-12-12 00:38:30 +00:00
9460b3cd04
Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
2021-12-11 15:52:34 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
7d2fa6a049
Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic
2021-12-09 06:26:31 +00:00
116e34df49
Fix commented out frontend properties which relied on non-constant past reset values
2021-12-07 20:24:29 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
6ef3503ef5
Add A bit to MISA, update docs
2021-12-07 05:10:20 +00:00
93be227d8a
Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
2021-12-06 20:12:23 +00:00
ed22d502fd
Fix bus stall getting stuck high when a bus fault exception isn't immediately accepted by the frontend
2021-12-06 19:28:21 +00:00
50d3d5d3b3
Maintain AMO IRQ holdoff when transitioning from data phase to error phase, to prevent error possibly being flushed
2021-12-06 19:27:20 +00:00
29c5c8ca7f
Fix AMO stall falling through when write data phase should proceed to error phase
2021-12-06 18:28:56 +00:00
8bfc089660
Slightly more strict holdoff of IRQs on AMO
2021-12-06 18:13:43 +00:00
0b3629564c
Don't apply shifter assertions to rotates
2021-12-06 18:12:23 +00:00
4c532240f8
Hold off IRQ when AMO is past the point of no return
2021-12-06 07:45:13 +00:00
260491405a
Fix atomic instructions not asserting decode error when A extension is disabled
2021-12-06 07:28:50 +00:00
cc38f46848
Fix AMO wdata valid left high when entering trap at just the right time
2021-12-06 07:28:50 +00:00
12c79c0b41
Fix feature-flag for Zbs instructions in decoder
2021-12-05 02:05:35 +00:00
9b9120960d
Fix missing RAW stall on sc.w succes result. Closing laptop again.
2021-12-05 01:05:01 +00:00
df658d86ff
First plausibly working AMOs. Add AMOs to instruction timings list
2021-12-04 23:44:22 +00:00
5c098866f2
Sketch in AMO support
2021-12-04 20:46:39 +00:00
34e57f0b14
Sketch in an AMO ALU
2021-12-04 18:52:41 +00:00
a8933c332d
Fix illegal issue of pipelined exclusives on the bus, and document correct timings
2021-12-04 18:23:01 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
607147f280
Rewrite byte pick/sign-extend logic, preparing to handle more memops
2021-12-04 12:08:54 +00:00
a988adfec8
Add RISC-V opcodes and memory operation codes for atomics
2021-12-04 11:16:24 +00:00
52ba930638
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
2021-12-04 01:17:57 +00:00
dfb07822ee
Remove UART DTM
2021-12-02 02:08:16 +00:00
be6b2f3f76
Fix up DTMs to use byte addressing
2021-12-02 02:05:23 +00:00
1ebccb7cce
Switch DM to use byte addresses on APB, not word addresses
2021-12-02 01:47:30 +00:00
c5e85dea4c
Add mconfigptr CSR
2021-12-01 03:25:56 +00:00
c8afb4ac33
Add option for fast high-half multiplies
2021-11-29 18:48:02 +00:00
94a3d43f27
Add Hazard3's registered marchid value to hdl and docs
2021-11-28 19:53:49 +00:00
1aa9dbcddd
Fix comment typo in APB clock crossing
2021-11-28 17:40:57 +00:00
e7466ae4be
Move DM data0 CSR into the M-custom space, and document this
2021-11-28 15:52:52 +00:00
76172cdade
Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
2021-11-28 06:33:35 +00:00
800b21d2f5
Remove event feedback path (not logical path) in priority encoder
2021-11-28 02:19:01 +00:00
14a4f1a281
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
2021-11-27 17:19:41 +00:00
5d093487b7
Update README
2021-11-26 23:33:46 +00:00
1bb7e33b69
Fix alignment of heap_ptr in init.S. Small ALU cleanup
2021-11-26 02:59:50 +00:00
8bcec11c80
Couple more silly mistakes
2021-11-26 01:30:13 +00:00
41eeb90c7d
Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
2021-11-26 01:29:47 +00:00
998f3fdeb7
Clean up silly mistakes
2021-11-26 00:55:57 +00:00
58c20a39d0
First pass at implementing bitmanip. Breaks CXXRTL. Ooop
2021-11-25 23:30:35 +00:00
ed6b6a3660
Cleanup order of declaration/use of a couple of wires
2021-11-25 15:16:59 +00:00
49462a8642
Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh
2021-11-23 22:11:50 +00:00
e05e9a4109
Add default_nettype none at top of every file, and default_nettype wire at bottom
2021-11-23 22:10:39 +00:00
0b9b706e81
Safer logic for load/store blocked by preceding WFI
2021-11-23 22:01:14 +00:00
cc6a6c09ba
Vaguely implement wfi
2021-11-05 18:48:42 +00:00
cfe16caf41
Remove some old todos
2021-09-05 22:20:40 +01:00
e9fccffca0
Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
2021-09-05 04:45:38 +01:00
65bfca5fdf
Fix latent bug with asynchronous debug entry during stalled load/store address phase
2021-09-04 07:49:29 +01:00
d03a82a826
Add instruction fetch faults
2021-09-04 02:57:39 +01:00
e16ae06cb5
Clean up timer
2021-08-21 17:03:32 +01:00
9dd091b7b5
Doh typo
2021-08-21 09:06:20 +01:00
b99e5b8a67
Convert timer to serial for smaller area. Rather untested
2021-08-20 22:27:15 +01:00
4aba165166
First pass at a 64-bit system timer
2021-08-20 21:49:05 +01:00
8263ee3a5d
Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception
2021-07-24 15:31:33 +01:00
70a44d9681
Small code cleanup
2021-07-24 10:08:27 +01:00
155d3ba554
Tie off 1 or 2 LSBs of DPC depending on IALIGN
2021-07-23 23:09:03 +01:00
115cb2c50f
Tweaks to example soc configuration
2021-07-23 23:08:23 +01:00
279e4b4f29
Implement mstatush as hardwired-0, as required by priv-1.12
2021-07-23 21:52:01 +01:00
2ae30183aa
Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
2021-07-23 18:32:47 +01:00
8ceae7e9e6
Start hacking on ECP5 JTAG DTM
2021-07-23 00:36:55 +01:00
41477ce479
Extract DTM bus/control logic from the JTAG-related parts
2021-07-22 19:26:25 +01:00
8cdde82248
Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends
2021-07-20 00:13:26 +01:00
7d24f42da9
Oops, properly fix platform IRQ mcause numbers
2021-07-19 09:32:59 +01:00
65fb62901e
Mask off trap entry assertion from IRQs when in debug mode. Because the IRQ is level-sensitive, this caused trap entry to be held asserted when an IRQ fired in debug mode. This was exposed by the last bug fix -- it is only seen now that MIE+MPIE shuffling is correctly disabled in debug mode.
2021-07-19 00:19:56 +01:00
70443fa557
Disable shifting of MIE/MPIE stack when in or entering debug mode
2021-07-18 21:14:11 +01:00
d30fc46f5b
Fix IRQ mcause not being set correctly when vectoring is disabled
2021-07-18 20:44:39 +01:00
e95b465e26
Typo in address of mcountinhibit!
2021-07-17 19:27:01 +01:00
d9300ee127
Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry
2021-07-17 19:26:45 +01:00
5deff12f95
DM: don't report as running/halted in dmstatus if unavailable.
2021-07-17 16:46:39 +01:00
ab0b4a04f0
Also support progbuf in abstractauto.
2021-07-17 15:08:00 +01:00
8e3dc62b97
Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions
2021-07-16 20:43:24 +01:00
5aca6be572
Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.
2021-07-16 18:28:30 +01:00
ce5152a4f4
Implement HALTSUM0 and HALTSUM1 registers
2021-07-16 17:58:28 +01:00
011008efd1
Fix detection of exception-like vs IRQ-like halt/trap entries
2021-07-15 19:41:35 +01:00
71ec9fa283
Fix exception entry not counting as a step point for dcsr.step, and mask off IRQs in step mode (we tie dcsr.stepie = 0)
2021-07-14 20:39:51 +01:00
f4952ab66d
Add simple example SoC, hangs nextpnr for some reason!
2021-07-13 03:40:06 +01:00
307955c810
Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
2021-07-13 01:10:55 +01:00
93c7039ea1
Sync doc updates
2021-07-12 22:13:31 +01:00
Luke Wren
Luke Wren