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263 Commits
v1.0 ... master

Author SHA1 Message Date
colin 5721e092bb Refine build.sbt. ignore no use middle files of scala. 2022-03-26 17:51:42 +00:00
colin d61bc07515 Split RAM and ROM to 8 banks. 2022-03-23 14:33:06 +00:00
colin fd6791eb26 Refine ahb mem to 8 banks.To avoid Synth error. 2022-03-22 06:08:34 +00:00
colin b6a916aca4 Modify RAM and ROM to WIDTH=12 4K Byte. 2022-03-20 09:04:32 +00:00
colin cdd2f57902 Add jlink config. 2022-03-20 09:04:10 +00:00
colin 68653daa2c Add clk out for fpga. 2022-03-15 11:38:18 +00:00
colin 85b5ac0f8b Add clk output for led. 2022-03-11 03:05:36 +00:00
colin 0948bc9cfa Enable quasar fpga genaration. 2022-03-11 02:49:57 +00:00
colin 2780c08c6a Enable demo of jtag. 2022-03-10 13:12:28 +00:00
colin 400cf6450a Update ignore files,and delete no use file 2022-03-10 08:42:03 +00:00
colin 896011449d Add demo for veilator and fpga. 2022-03-10 04:53:38 +00:00
Laraib Khan 2bc0985afd
Update README.md 2021-04-13 12:31:33 +05:00
Laraib Khan 59968dce28
Update README.md 2021-04-13 11:54:10 +05:00
Laraib Khan 53c4c9e87a
Update README.md 2021-04-13 11:53:05 +05:00
Laraib Khan 3457bf3e82
Update README.md 2021-04-13 10:42:27 +05:00
komaljaved-lm 9f20ea977f
Update README.md 2021-04-13 10:32:06 +05:00
Laraib Khan 21cd2024bb QUASAR 2.0 Final 2021-04-12 09:40:17 +05:00
​Laraib Khan 0255c7fa9d QUASAR 2.0 Final 2021-04-09 16:01:26 +05:00
​Laraib Khan 5dd747e1a8 QUASAR 2.0 Final 2021-04-09 14:30:45 +05:00
​Laraib Khan a263903e7e QUASAR 2.0 Final 2021-04-09 14:27:44 +05:00
Laraib Khan 0e91028b8d
Update dec.scala 2021-04-08 21:40:09 +05:00
komaljaved-lm 902f4046fc Updated LEC scripts 2021-04-02 12:46:39 +05:00
komaljaved-lm 46a5cc2d86 Updated for running LEC 2021-04-01 18:21:21 +05:00
komaljaved-lm d533ec413e modified Makefile(all tests verified) 2021-03-31 10:23:11 +05:00
komaljaved-lm e6e6ad233a Readme added 2021-03-30 11:09:40 +05:00
komaljaved-lm a180a336ba
Update README.md 2021-03-30 11:01:49 +05:00
komaljaved-lm 545ffa223b
Update README.md 2021-03-30 10:57:10 +05:00
komaljaved-lm 4f7ce52d89
Update README.md 2021-03-29 18:36:27 +05:00
komaljaved-lm 1a79af7965
Update README.md 2021-03-29 18:36:12 +05:00
komaljaved-lm a90fe1c613 Updated Makefile to run LEC 2021-03-29 18:34:16 +05:00
komaljaved-lm 9619596488
Update Makefile 2021-03-29 10:15:57 +05:00
komaljaved-lm 1358754e8d updated makefile and tb_top 2021-03-29 10:09:22 +05:00
laraibkhan-lm 6357b8d0cd
Update ifu_ic_mem.sv 2021-03-05 11:11:28 +05:00
​Laraib Khan 2d9eda1e2e QUASAR added 2021-03-03 16:11:42 +05:00
Laraib Khan d0a9d54b91 QUASAR added 2021-03-03 15:17:53 +05:00
Laraib Khan 6ad23a0226 QUASAR 2.0 Final 2021-03-03 11:35:11 +05:00
​Laraib Khan b40ab3459c Memory connection updated 2021-02-24 16:55:17 +05:00
​Laraib Khan 11695f3916 Memory connection updated 2021-02-24 16:13:28 +05:00
​Laraib Khan 5d42a80edf dma buf depth corrected 2021-02-23 10:11:22 +05:00
​Laraib Khan 5509edc39d mem reset corrected 2021-02-22 14:05:35 +05:00
​Laraib Khan 904ac0263f Quasar Wrapper updated 2021-02-17 09:51:40 +05:00
​Laraib Khan 21b5cc23f7 Quasar lec cleaned 2021-02-16 16:49:34 +05:00
​Laraib Khan 46e545e733 Quasar lec cleaned 2021-02-16 14:36:59 +05:00
​Laraib Khan 3b9f229475 Quasar updated 2021-02-09 12:12:03 +05:00
​Laraib Khan 11c09dc85b Debug rvoclk corrected 2021-02-04 18:00:41 +05:00
​Laraib Khan df4b1058f1 QUASAR added 2021-02-04 15:09:33 +05:00
​Laraib Khan 2f42344e29 QUASAR added 2021-02-03 13:05:34 +05:00
​Laraib Khan 95a4cc20df ifu added 2021-02-03 11:51:02 +05:00
​Laraib Khan 7ae7c4687f ifu added 2021-02-03 09:37:48 +05:00
​Laraib Khan 33a4c11f1c obuf_timer corrected 2021-02-02 15:34:19 +05:00
​Laraib Khan 3de7adb50f clock enable updated 2021-02-02 15:10:04 +05:00
​Laraib Khan 2b0f57e6bf aligner added 2021-02-02 11:35:16 +05:00
​Laraib Khan 4fa5ee274d lsu updated 2021-02-02 10:25:17 +05:00
​Laraib Khan d19b173907 lsu updated 2021-02-02 10:22:27 +05:00
​Laraib Khan b013d2cd7f LSU Top updated 2021-02-01 17:03:36 +05:00
​Laraib Khan 8143bb1772 LSU Top updated 2021-01-29 16:38:05 +05:00
​Laraib Khan 92b7b00a3a obuf_timer corrected 2021-01-29 15:18:45 +05:00
​Laraib Khan 9da7df3623 LSU Added 2021-01-28 17:36:33 +05:00
​Laraib Khan 60faa36fe5 debug_valid_d corrected 2021-01-28 12:40:20 +05:00
​Laraib Khan 630c544fb1 i0 legal corrected 2021-01-28 12:16:34 +05:00
​Laraib Khan 80ac7ee439 pcio clk override updated 2021-01-27 18:01:24 +05:00
​Laraib Khan b9cdbac350 Dec added 2021-01-27 13:04:31 +05:00
​Laraib Khan f23f878f60 Dec added 2021-01-27 11:46:11 +05:00
​Laraib Khan 6479386424 EXU final 2021-01-26 16:42:01 +05:00
​Laraib Khan 9d2075de64 Multiplier updated 2021-01-26 16:06:50 +05:00
​Laraib Khan a0f383cb2d Multiplier rvdffe updated 2021-01-26 15:03:26 +05:00
​Laraib Khan b17f70b674 EXU Top updated 2021-01-26 09:43:24 +05:00
​Laraib Khan fd4ab0599d EXU Top updated 2021-01-25 17:58:38 +05:00
​Laraib Khan 208045e9c3 BP updated 2021-01-25 11:46:37 +05:00
​Laraib Khan a57b0aa45f BP updated 2021-01-25 11:42:42 +05:00
​Laraib Khan 80802390ad bht_bank_wr_data corrected 2021-01-25 11:28:39 +05:00
​Laraib Khan 91635292c6 ifu_bp_btb_target_f corrected 2021-01-25 10:44:37 +05:00
​Laraib Khan a5be674839 btb_vbank0_rd_data_f := Mux1H(Seq(!io.ifc_fetch_addr_f(0) -> btb_bank0e_rd_data_f, 2021-01-22 16:41:53 +05:00
​Laraib Khan a25ee3cf0e vwayhit corrected 2021-01-22 15:59:15 +05:00
​Laraib Khan ef2f0bbbb2 vwayhit corrected 2021-01-22 14:59:02 +05:00
​Laraib Khan 5ec570e847 vwayhit corrected 2021-01-22 12:38:12 +05:00
​Laraib Khan f2bbfb2e20 vwayhit corrected 2021-01-22 11:44:00 +05:00
​Laraib Khan c228964d6a BTB size small 2021-01-22 11:07:44 +05:00
​Laraib Khan c68cb08744 BTB size small 2021-01-22 10:59:31 +05:00
​Laraib Khan f8874723a6 BP corrected 2021-01-21 16:12:12 +05:00
​Laraib Khan ed92fad092 BP added 2021-01-20 15:46:13 +05:00
​Laraib Khan 5ac08982de IFC updated 2021-01-18 11:10:24 +05:00
​Laraib Khan ce64b77952 AHB/AXI updated 2021-01-15 11:01:11 +05:00
​Laraib Khan 81f85d455b AHB/AXI updated 2021-01-15 10:32:49 +05:00
​Laraib Khan 43cddfd8b7 rvdffsc corrected 2021-01-14 12:36:40 +05:00
​Laraib Khan 43402819b0 slv_error corrected 2021-01-14 10:12:56 +05:00
​Laraib Khan 9479360020 ahb_size corrected in AHB/AXI 2021-01-13 12:29:47 +05:00
​Laraib Khan d13d0efa85 Bridges added 2021-01-13 11:28:03 +05:00
​Laraib Khan d9dc8848f9 AHB/AXI added 2021-01-13 10:07:59 +05:00
​Laraib Khan be9a487ba1 LSU Top added 2021-01-08 16:13:00 +05:00
​Laraib Khan 7881351a25 Extra modules deleted 2021-01-08 09:21:34 +05:00
​Laraib Khan 1c84acbbfc All 5 dividers added with LEC 2021-01-08 09:09:54 +05:00
​Laraib Khan bf4de4dc91 All 5 dividers added with LEC 2021-01-07 16:28:05 +05:00
​Laraib Khan dbe63e1ae6 Quotient new corrected 2021-01-07 16:18:42 +05:00
​Laraib Khan c874128938 Divider 5 added 2021-01-07 12:53:47 +05:00
​Laraib Khan 6b63669e0c adder_sel func added 2021-01-07 10:53:27 +05:00
​Laraib Khan a1acaaa217 quotient new corrected 2021-01-07 10:11:23 +05:00
​Laraib Khan 4e2d0d75c2 adder added 2021-01-06 17:30:00 +05:00
​Laraib Khan f85272ce0a shiftq_ff corrected 2021-01-06 16:43:25 +05:00
​Laraib Khan 675d53d37f divider 4 added 2021-01-06 15:43:04 +05:00
​Laraib Khan 92cf822089 divider 4 added 2021-01-06 15:04:21 +05:00
​Laraib Khan 967cfe3819 small numcase corrected 2021-01-06 10:22:58 +05:00
​Laraib Khan 042ddf10b4 adder out 2 corrected 2021-01-06 10:13:06 +05:00
​Laraib Khan 64be0093cb quotient new changed 2021-01-06 10:05:37 +05:00
​Laraib Khan 65d5369d1e 2 bit divider 2021-01-06 09:32:46 +05:00
​Laraib Khan a4474e1299 bus_rst updated 2020-12-30 11:06:59 +05:00
​Laraib Khan 2527f455ca bus_rst updated 2020-12-30 09:50:45 +05:00
​Laraib Khan 722fb8bdc0 bus_intf added 2020-12-29 11:47:28 +05:00
​Laraib Khan 119a9ad388 buf_error corrected 2020-12-29 11:26:56 +05:00
​Laraib Khan 45fac8e01d buf_error corrected 2020-12-29 10:47:27 +05:00
​Laraib Khan 1119469d76 buf_rst corrected 2020-12-29 10:36:06 +05:00
​Laraib Khan adce90c0e9 buf_rst corrected 2020-12-29 10:02:46 +05:00
​Laraib Khan c52c6324d9 buf_rst corrected 2020-12-28 18:01:06 +05:00
​Laraib Khan e5b9988491 buf_rst corrected 2020-12-28 17:08:01 +05:00
​Laraib Khan e1c566dae9 rvdffe registers updated 2020-12-28 16:41:59 +05:00
​Laraib Khan bb89af4b68 fpga registers updated 2020-12-28 14:17:13 +05:00
​Laraib Khan 57f1b66c15 bus buffer with buf_nextstate in resp updated 2020-12-28 12:49:43 +05:00
​Laraib Khan 0cd4180d83 bus buffer with buf_nextstate in resp updated 2020-12-28 11:51:11 +05:00
​Laraib Khan 17fe416e15 bus buffer with reg_fpga updated 2020-12-28 10:41:40 +05:00
​Laraib Khan c438fae14a bus buffer added 2020-12-24 16:51:11 +05:00
​Laraib Khan 46ffb7c24f bus buffer added 2020-12-24 16:34:10 +05:00
​Laraib Khan 309087b854 bus buffer added 2020-12-24 15:53:17 +05:00
​Laraib Khan c0504d57a0 end_addr_r updated 2020-12-24 10:49:31 +05:00
​Laraib Khan 8c477719a6 fir_error updated 2020-12-24 10:44:27 +05:00
​Laraib Khan bfeaa72eda lsc_ctl updated 2020-12-24 09:36:17 +05:00
​Laraib Khan 26ff2b4009 lsc_ctl added 2020-12-23 15:36:45 +05:00
​Laraib Khan d8a8c019ed dccm_ctl with lsu_rdata_corr_m corrected 2020-12-23 15:30:59 +05:00
​Laraib Khan a6f2164595 dccm_ctl with lsu_rdata_corr_m corrected 2020-12-23 15:11:59 +05:00
​Laraib Khan 6ce67de95c dccm_ctl with dccm_dma_rdata corrected 2020-12-23 14:38:53 +05:00
​Laraib Khan 1b7a0b47e1 dccm_ctl with rvdffe 2020-12-23 10:56:05 +05:00
​Laraib Khan 248ab0784b stbuf with rvdffe 2020-12-23 09:39:18 +05:00
​Laraib Khan 01d018f555 stbuf with rvdffe 2020-12-22 18:10:15 +05:00
​Laraib Khan b1a6c0bf30 rvclkhdr with scan mode=0 2020-12-22 16:51:17 +05:00
​Laraib Khan e1ce51fdd4 clk domain with rvoclkhdr 2020-12-22 16:44:36 +05:00
​Laraib Khan b8b042faa8 lsu with newer release 2020-12-22 15:24:39 +05:00
​Laraib Khan 9f30e1773b AXI build 2020-12-18 10:53:24 +05:00
​Laraib Khan 07a61a92cf PIC extrinsic updated in quasar 2020-12-18 10:27:40 +05:00
​Laraib Khan 1c41a85c25 Master updated 2020-12-18 10:14:48 +05:00
​Laraib Khan 8892c85b0c Master updated with one object 2020-12-18 10:06:24 +05:00
​Laraib Khan 9d0f8900fc Master updated with one object 2020-12-17 18:30:02 +05:00
​Laraib Khan 15483fd532 Master updated with vsrc 2020-12-17 18:21:54 +05:00
​Laraib Khan 1badd94e5d DEC bug removed 2020-12-17 15:24:04 +05:00
​Laraib Khan d2c1fc52db mimpid=1 2020-12-17 15:03:40 +05:00
​Laraib Khan 6b768acbc7 LSU Decode added 2020-12-17 14:40:41 +05:00
​Laraib Khan 5f5f691ec1 LSU Decode added 2020-12-17 14:17:49 +05:00
​Laraib Khan a19d561a77 DECODE added 2020-12-17 11:01:49 +05:00
​Laraib Khan ff87a1341a DECODE added 2020-12-17 10:54:07 +05:00
​Laraib Khan 4328532fdb vsrc replaced 2020-12-17 10:16:07 +05:00
​Laraib Khan c80dac6075 PIC,param,lib,mem.scala added 2020-12-17 09:38:45 +05:00
​Laraib Khan 3ab9b841d7 PIC,param,lib,mem.scala added 2020-12-17 09:32:59 +05:00
​Laraib Khan 4cf7b083e5 IFU added 2020-12-16 18:06:34 +05:00
​Laraib Khan 9a6d820227 LSU & EXU added 2020-12-16 17:29:40 +05:00
​Laraib Khan 09739661c2 DMA Inserted 2020-12-16 16:48:55 +05:00
​Laraib Khan 168d355e26 Bus Buffer Update 2020-12-16 10:46:14 +05:00
​Laraib Khan 9e1350202d Bus Buffer Update 2020-12-16 10:39:45 +05:00
​Laraib Khan b995258ecd Bus Buffer Update 2020-12-10 13:03:53 +05:00
​Laraib Khan a73ad4942e Bus Buffer Update 2020-12-10 12:29:31 +05:00
​Laraib Khan 8616219c43 Bus Buffer Update 2020-12-10 12:09:34 +05:00
​Laraib Khan 3a1fa4fbd7 LSU with Bundling 2020-12-10 09:50:49 +05:00
​Laraib Khan fd0b01190e Core with Bundles 2020-12-09 17:28:33 +05:00
​Laraib Khan b9c70b1fb5 Core with Bundles 2020-12-09 09:34:03 +05:00
​Laraib Khan d48d2bb461 LSU with Bundling 2020-12-07 12:27:31 +05:00
​Laraib Khan 439c0adebc axi to ahb update 2020-12-03 14:08:12 +05:00
​Laraib Khan 7a1457b2e2 axi to ahb update 2020-12-03 11:39:11 +05:00
​Laraib Khan 5e4f49b6b2 axi to ahb update 2020-12-03 10:44:15 +05:00
​Laraib Khan 86bb3d7c2c axi to ahb update 2020-12-03 10:24:25 +05:00
​Laraib Khan cbff4bad75 axi to ahb update 2020-12-03 09:36:24 +05:00
​Laraib Khan a1772cfe2b axi to ahb update 2020-12-02 18:21:57 +05:00
​Laraib Khan 04eba9f5f5 axi to ahb update 2020-12-02 16:20:44 +05:00
​Laraib Khan c5414d6a20 ahb to axi update 2020-12-02 15:58:23 +05:00
​Laraib Khan 76f0c4f9a9 ahb to axi update 2020-12-02 15:07:54 +05:00
​Laraib Khan cf771bdcf4 ahb to axi update 2020-12-02 14:39:55 +05:00
​Laraib Khan 6976647dc5 axi to ahb update 2020-12-02 14:18:55 +05:00
​Laraib Khan c90004a1d3 axi to ahb update 2020-12-02 13:42:07 +05:00
​Laraib Khan a199293620 axi to ahb update 2020-12-02 12:05:38 +05:00
​Laraib Khan 174b18b84e axi to ahb update 2020-12-02 11:40:06 +05:00
​Laraib Khan 408cd7612b axi to ahb update 2020-12-02 11:06:36 +05:00
​Laraib Khan d1c93cfccb axi to ahb update 2020-12-02 09:07:46 +05:00
​Laraib Khan 9ae43ddb94 axi to ahb update 2020-12-01 18:00:07 +05:00
​Laraib Khan 6c3eda7075 axi to ahb update 2020-12-01 17:02:39 +05:00
​Laraib Khan e816ea5776 axi to ahb update 2020-12-01 17:00:36 +05:00
​Laraib Khan eff5d74c44 axi to ahb update 2020-12-01 16:57:34 +05:00
​Laraib Khan a91a14fd34 axi to ahb update 2020-12-01 16:20:25 +05:00
​Laraib Khan 58343b6532 axi to ahb update 2020-12-01 14:40:57 +05:00
​Laraib Khan 4518880c47 axi to ahb update 2020-12-01 11:56:56 +05:00
​Laraib Khan e6054811cd axi to ahb update 2020-12-01 11:44:51 +05:00
​Laraib Khan 6a0fe72da2 axi to ahb update 2020-12-01 11:34:17 +05:00
​Laraib Khan cd13b88467 axi to ahb update 2020-12-01 10:59:16 +05:00
​Laraib Khan ea912f6dee axi to ahb update 2020-12-01 10:31:04 +05:00
​Laraib Khan d10e4748be axi to ahb update 2020-12-01 09:30:48 +05:00
​Laraib Khan 3694303a8d axi to ahb update 2020-11-30 17:28:11 +05:00
​Laraib Khan 3c00117ccf axi to ahb update 2020-11-30 15:31:49 +05:00
​Laraib Khan ad3359da87 lsu update 2020-11-30 15:08:22 +05:00
​Laraib Khan 1c0d6d492c lsu update 2020-11-30 10:21:58 +05:00
​Laraib Khan 9f7ddbee4c lsu top update 2020-11-27 16:33:17 +05:00
​Laraib Khan ab0b53b11f dec update 2020-11-24 17:21:01 +05:00
​Laraib Khan e4ec02558c dec update 2020-11-24 16:56:00 +05:00
​Laraib Khan 23069873a9 dec update 2020-11-24 16:45:01 +05:00
​Laraib Khan 220b0575c1 dec update 2020-11-24 15:49:49 +05:00
​Laraib Khan 5ed044d54b dec update 2020-11-24 14:28:34 +05:00
​Laraib Khan 964d3960a2 dec update 2020-11-24 13:19:06 +05:00
​Laraib Khan c4d5618ac1 dec update 2020-11-24 13:00:51 +05:00
​Laraib Khan cf122545de Packets updated with Valid 2020-11-23 15:57:46 +05:00
​Laraib Khan 89e70f46c8 Packets updated with Valid 2020-11-23 15:42:08 +05:00
​Laraib Khan 37641a8a14 Packets updated with Valid 2020-11-23 14:53:08 +05:00
​Laraib Khan 7dc1174c9a Bus buffer updated 2020-11-20 11:32:39 +05:00
​Laraib Khan 2b59a630d6 lsu update 2020-11-18 16:14:53 +05:00
​Laraib Khan 2afae08254 lsu updated 2020-11-18 15:42:14 +05:00
​laraibkhan119 4b73eb7a6f lsu updated 2020-11-06 15:05:28 +05:00
​laraibkhan119 4e107cc640 lsu updated 2020-10-22 14:52:47 +05:00
​laraibkhan119 2a2474ca44 trigger update 2020-09-24 12:28:55 +05:00
​laraibkhan119 4a560e881a lib updated 2020-09-24 12:07:12 +05:00
​laraibkhan119 4ab72523c7 trigger donee 2020-09-24 12:04:13 +05:00
Laraib Khan f0544e52ca
Lsu Trigger updated and ready for verification 2020-09-24 09:29:29 +05:00
Laraib Khan f399b91153
Delete el2_lsu_trigger.scala 2020-09-24 09:28:06 +05:00
Junaid Ahmed 6686380981
Update el2_lsu_addrcheck.scala 2020-09-23 18:52:29 +05:00
Junaid Ahmed 2b6bfabc4f
Update beh_lib.scala 2020-09-23 18:51:52 +05:00
Jahanzaib-Rasheed 32abf7c324 Lsu clk Domain ready for verification. 2020-09-23 15:39:00 +05:00
Junaid Ahmed 854445ca27
Update beh_ib_func.scala 2020-09-23 13:56:14 +05:00
Junaid Ahmed 0ef2742e74
Update beh_lib.scala 2020-09-23 13:55:36 +05:00
Junaid Ahmed aacb784805
Update beh_lib.scala 2020-09-23 11:14:01 +05:00
Jahanzaib-Rasheed 264b94b397 Clk domain ready for verification. 2020-09-23 10:28:05 +05:00
Jahanzaib-Rasheed 8fdc50f01e Merge remote-tracking branch 'origin/lsu' into lsu 2020-09-23 09:45:52 +05:00
Jahanzaib-Rasheed 0a95ef12ce LSU Clkdomain Ready for verification. 2020-09-23 09:43:30 +05:00
Junaid Ahmed 51c143b73f
Update beh_ib_func.scala 2020-09-22 17:25:52 +05:00
Junaid Ahmed 90ba79ae2c
Update beh_ib_func.scala 2020-09-22 17:24:07 +05:00
Jahanzaib-Rasheed 080417afc1 Merge remote-tracking branch 'origin/lsu' into lsu 2020-09-22 16:52:09 +05:00
Junaid Ahmed 33a6ca89b3
Update beh_ib_func.scala 2020-09-22 16:15:11 +05:00
Junaid Ahmed ccdab1e35c
Update el2_bundle.scala 2020-09-22 14:39:44 +05:00
Jahanzaib-Rasheed 9e6d3eb36c Merge branch 'master' into lsu 
# Conflicts:
#	src/main/scala/lib/GCD.scala
#	src/main/scala/lib/beh_lib.scala
 2020-09-22 13:03:17 +05:00
Junaid Ahmed 5474c212a2
Update el2_lsu_addrcheck.scala 2020-09-22 12:59:01 +05:00
Junaid Ahmed 39d2f675be
Update el2_lsu_lsc_ctl.scala 2020-09-22 10:36:25 +05:00
Junaid Ahmed ac47375afd
Create TEC_RV_ICG.v 2020-09-22 10:35:24 +05:00
Junaid Ahmed 5cc210e06d
Update el2_lsu_addrcheck.scala 2020-09-22 10:30:01 +05:00
Junaid Ahmed 2da85e1800
Update el2_bundle.scala 2020-09-22 10:29:21 +05:00
Junaid Ahmed faebf955b4
Update el2_param.scala 2020-09-22 10:28:26 +05:00
Junaid Ahmed ce85542554
Rename beh_ib_func to beh_ib_func.scala 2020-09-22 10:27:48 +05:00
Junaid Ahmed df2e8fcd48
Create beh_ib_func 2020-09-22 10:27:16 +05:00
Junaid Ahmed 698c0fc1a1
Update beh_lib.scala 2020-09-22 10:26:16 +05:00
Junaid Ahmed 536c46df44
Update el2_lib.scala 2020-09-10 15:14:43 +05:00
Jahanzaib-Rasheed f60e035eeb LSU clock domain skeleton 2020-09-10 14:45:14 +05:00
Junaid Ahmed aa4da62dd9
Update el2_lsu_addrcheck.scala 2020-09-10 11:23:10 +05:00
Jahanzaib Rasheed 6928b8d554
Bus Buffer Skeleton 2020-09-10 10:52:42 +05:00
Jahanzaib Rasheed 1b50c01e9f
Add files via upload 2020-09-10 03:12:02 +05:00
Jahanzaib Rasheed a63562c44f
Update el2_lsu_bus_intf.scala 2020-09-09 17:13:26 +05:00
Jahanzaib Rasheed 9feb32e9a5
Add files via upload 2020-09-09 12:41:55 +05:00
Jahanzaib Rasheed 816dd73ce3
Update el2_lsu_bus_intf.scala 2020-09-09 12:17:00 +05:00
Jahanzaib Rasheed a54f947419
Update el2_lsu_bus_intf.scala 
Multi IO replaced with IO bundle.
 2020-09-09 11:34:09 +05:00
Jahanzaib Rasheed dffa6e549b
Merge pull request #1 from waleedbinehsan-lm/Jahanzaib-rasheed-patch-1 
Add files via upload
 2020-09-09 11:19:47 +05:00
Jahanzaib Rasheed e4ba61b774
Add files via upload 2020-09-09 11:18:23 +05:00
Laraib Khan 23995c11da
Add files via upload 2020-09-08 18:06:30 +05:00
Laraib Khan 7c29f90e7b
Delete el2_lsu_ecc.scala 2020-09-08 18:05:55 +05:00
Laraib Khan 08ca9a4e96
Delete el2_lsu_trigger.scala 2020-09-08 18:05:39 +05:00
Laraib Khan 11f8703ba3
Add files via upload 2020-09-08 12:11:08 +05:00
Laraib Khan 011463b493
Add files via upload 2020-09-08 12:10:07 +05:00
Junaid Ahmed 3062c9343e
Update el2_param.scala 2020-09-07 12:23:52 +05:00
Junaid Ahmed fa1a39200a
Delete exp.sc 2020-09-07 12:21:04 +05:00
Junaid Ahmed 1fc689d6ad
Add files via upload 2020-09-07 12:20:23 +05:00
Junaid Ahmed 5ddac811dc
Delete RVC.scala 2020-09-07 12:19:52 +05:00
Junaid Ahmed a39dfaabdf
Delete GCD.scala 2020-09-07 12:18:11 +05:00
Junaid Ahmed 5e73c9b102
Create el2_bundle.scala 2020-09-07 12:16:35 +05:00
Junaid Ahmed 5babe11fe8
Delete el2_bundle.scala 2020-09-07 12:12:50 +05:00
Junaid Ahmed 0e4fff42ab
Add files via upload 2020-09-07 12:10:04 +05:00
534 changed files with 71200 additions and 12807 deletions
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.gitignore vendored Normal file
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.metals/
.vscode/
# design/project/target/
# design/project/project/
design/project/
design/.idea/
design/target/
generated_rtl/*.sv
verif/sim/*.log
verif/sim/*.s
verif/sim/*.hex
verif/sim/*.dis
verif/sim/*.tbl
verif/sim/vcs*
verif/sim/simv*
verif/sim/quasar*
verif/sim/*.exe
verif/sim/obj*
verif/sim/*.o
verif/sim/ucli.key
verif/sim/vc_hdrs.h
verif/sim/csrc
verif/sim/*.csv
verif/sim/work
verif/sim/*.dump
verif/sim/*.fsdb
FM_WORK
tracer_logs/*.log
verif/LEC/formality_work/formality_log/*.log
verif/LEC/*.fss
design/snapshots/
design/src/main/scala/lib/param.scala
design/*.v
design/*.sv
design/*.f
design/*.json
design/*.fir
# soc/
# demo/

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# Default ignored files
/shelf/
/workspace.xml

1
.idea/.name
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chisel-module-template

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.idea/codeStyles/Project.xml
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<component name="ProjectCodeStyleConfiguration">
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5
.idea/codeStyles/codeStyleConfig.xml
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.idea/compiler.xml
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13
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13
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13
.idea/libraries/sbt__edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml
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13
.idea/libraries/sbt__edu_berkeley_cs_chisel3_core_2_12_3_3_1_jar.xml
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13
.idea/libraries/sbt__edu_berkeley_cs_chisel3_macros_2_12_3_3_1_jar.xml
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13
.idea/libraries/sbt__edu_berkeley_cs_chisel_iotesters_2_12_1_4_1_jar.xml
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13
.idea/libraries/sbt__edu_berkeley_cs_chiseltest_2_12_0_2_1_jar.xml
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13
.idea/libraries/sbt__edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml
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13
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13
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13
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13
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13
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13
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</CLASSES>
<JAVADOC />
<SOURCES />
</library>
</orderEntry>
</component>
<component name="SbtModule">
<option name="buildForURI" value="file:$MODULE_DIR$/../../" />
<option name="imports" value="_root_.sbt.Keys._, _root_.sbt.ScriptedPlugin.autoImport._, _root_.sbt._, _root_.sbt.nio.Keys._, _root_.sbt.plugins.IvyPlugin, _root_.sbt.plugins.JvmPlugin, _root_.sbt.plugins.CorePlugin, _root_.sbt.ScriptedPlugin, _root_.sbt.plugins.SbtPlugin, _root_.sbt.plugins.SemanticdbPlugin, _root_.sbt.plugins.JUnitXmlReportPlugin, _root_.sbt.plugins.Giter8TemplatePlugin, _root_.scala.xml.{TopScope=&gt;SUB:DOLLARscope}" />
</component>
</module>

51
.idea/modules/chisel-module-template.iml
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@ -1,51 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<module external.linked.project.id="swerv-chislified-master [file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
<component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
<output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
<output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />
<exclude-output />
<content url="file://$MODULE_DIR$/../..">
<sourceFolder url="file://$MODULE_DIR$/../../src/main/scala" isTestSource="false" />
<sourceFolder url="file://$MODULE_DIR$/../../src/test/scala" isTestSource="true" />
<excludeFolder url="file://$MODULE_DIR$/../../target" />
</content>
<orderEntry type="inheritedJdk" />
<orderEntry type="sourceFolder" forTests="false" />
<orderEntry type="library" name="sbt: com.github.nscala-time:nscala-time_2.12:2.22.0:jar" level="project" />
<orderEntry type="library" name="sbt: com.github.scopt:scopt_2.12:3.7.1:jar" level="project" />
<orderEntry type="library" name="sbt: com.google.protobuf:protobuf-java:3.9.0:jar" level="project" />
<orderEntry type="library" name="sbt: com.lihaoyi:utest_2.12:0.6.6:jar" level="project" />
<orderEntry type="library" name="sbt: com.thoughtworks.paranamer:paranamer:2.8:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:chisel-iotesters_2.12:1.4.1:jar" level="project" />
<orderEntry type="library" name="sbt: edu.berkeley.cs:chisel3-core_2.12:3.3.1:jar" level="project" />
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17
.idea/sbt.xml
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@ -1,17 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="ScalaSbtSettings">
<option name="linkedExternalProjectsSettings">
<SbtProjectSettings>
<option name="externalProjectPath" value="$PROJECT_DIR$" />
<option name="modules">
<set>
<option value="$PROJECT_DIR$" />
<option value="$PROJECT_DIR$/project" />
</set>
</option>
<option name="sbtVersion" value="1.3.10" />
</SbtProjectSettings>
</option>
</component>
</project>

14
.idea/scala_compiler.xml
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@ -1,14 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="ScalaCompilerConfiguration">
<profile name="sbt 1" modules="swerv-chislified-master_3681" />
<profile name="sbt 2" modules="chisel-module-template">
<parameters>
<parameter value="-Xsource:2.11" />
</parameters>
<plugins>
<plugin path="$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar" />
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</profile>
</component>
</project>

6
.idea/vcs.xml
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@ -1,6 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<project version="4">
<component name="VcsDirectoryMappings">
<mapping directory="$PROJECT_DIR$" vcs="Git" />
</component>
</project>

18
EL2_IC_DATA.anno.json
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@ -1,18 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"EL2_IC_DATA"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

26
EL2_IC_DATA.fir
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@ -1,26 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit EL2_IC_DATA :
module EL2_IC_DATA :
input clock : Clock
input reset : UInt<1>
output io : {flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<15>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, flip mask : UInt<1>[2][2]}
smem ic_memory : UInt<26>[2][2][512], undefined @[el2_ifu_ic_mem.scala 209:30]
wire data : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 210:48]
data[0][0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 210:48]
data[0][1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 210:48]
data[1][0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 210:48]
data[1][1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 210:48]
wire mem_mask : UInt<1>[2] @[el2_ifu_ic_mem.scala 211:51]
mem_mask[0] <= UInt<1>("h01") @[el2_ifu_ic_mem.scala 211:51]
mem_mask[1] <= UInt<1>("h01") @[el2_ifu_ic_mem.scala 211:51]
wire mem_mask2 : UInt<1>[2][2] @[el2_ifu_ic_mem.scala 212:52]
mem_mask2[0][0] <= mem_mask[0] @[el2_ifu_ic_mem.scala 212:52]
mem_mask2[0][1] <= mem_mask[1] @[el2_ifu_ic_mem.scala 212:52]
mem_mask2[1][0] <= mem_mask[0] @[el2_ifu_ic_mem.scala 212:52]
mem_mask2[1][1] <= mem_mask[1] @[el2_ifu_ic_mem.scala 212:52]
io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 214:23]
io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 215:17]
io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 216:16]
io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 217:16]

34
EL2_IC_DATA.v
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@ -1,34 +0,0 @@
module EL2_IC_DATA(
input clock,
input reset,
input io_rst_l,
input io_clk_override,
input [11:0] io_ic_rw_addr,
input [1:0] io_ic_wr_en,
input io_ic_rd_en,
input [70:0] io_ic_wr_data_0,
input [70:0] io_ic_wr_data_1,
output [63:0] io_ic_rd_data,
input [70:0] io_ic_debug_wr_data,
output [70:0] io_ic_debug_rd_data,
output [1:0] io_ic_parerr,
output [1:0] io_ic_eccerr,
input [14:0] io_ic_debug_addr,
input io_ic_debug_rd_en,
input io_ic_debug_wr_en,
input io_ic_debug_tag_array,
input [1:0] io_ic_debug_way,
input [63:0] io_ic_premux_data,
input io_ic_sel_premux_data,
input [1:0] io_ic_rd_hit,
input io_scan_mode,
input io_mask_0_0,
input io_mask_0_1,
input io_mask_1_0,
input io_mask_1_1
);
assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 215:17]
assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 214:23]
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 217:16]
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 216:16]
endmodule

93
EL2_IC_TAG.anno.json
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@ -1,93 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_out_1",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_0",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_1",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_hit",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_out_0",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_perr",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid",
"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_0",
"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_0",
"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_1",
"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_1",
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_data_out_1",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_0",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_data_out_0",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_1",
"sources":[
"~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"EL2_IC_TAG"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2156
EL2_IC_TAG.fir
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File diff suppressed because it is too large Load Diff

384
EL2_IC_TAG.v
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@ -1,384 +0,0 @@
module rvecc_decode(
input [31:0] io_din,
input [6:0] io_ecc_in,
output [6:0] io_ecc_out,
output [31:0] io_dout,
output io_single_ecc_error
);
wire w0_0 = io_din[0]; // @[beh_lib.scala 239:37]
wire w0_1 = io_din[1]; // @[beh_lib.scala 239:37]
wire w1_1 = io_din[2]; // @[beh_lib.scala 240:37]
wire w0_2 = io_din[3]; // @[beh_lib.scala 239:37]
wire w0_3 = io_din[4]; // @[beh_lib.scala 239:37]
wire w1_3 = io_din[5]; // @[beh_lib.scala 240:37]
wire w0_4 = io_din[6]; // @[beh_lib.scala 239:37]
wire w2_3 = io_din[7]; // @[beh_lib.scala 241:37]
wire w0_5 = io_din[8]; // @[beh_lib.scala 239:37]
wire w1_5 = io_din[9]; // @[beh_lib.scala 240:37]
wire w0_6 = io_din[10]; // @[beh_lib.scala 239:37]
wire w0_7 = io_din[11]; // @[beh_lib.scala 239:37]
wire w1_7 = io_din[12]; // @[beh_lib.scala 240:37]
wire w0_8 = io_din[13]; // @[beh_lib.scala 239:37]
wire w2_7 = io_din[14]; // @[beh_lib.scala 241:37]
wire w0_9 = io_din[15]; // @[beh_lib.scala 239:37]
wire w1_9 = io_din[16]; // @[beh_lib.scala 240:37]
wire w0_10 = io_din[17]; // @[beh_lib.scala 239:37]
wire w3_7 = io_din[18]; // @[beh_lib.scala 242:37]
wire w0_11 = io_din[19]; // @[beh_lib.scala 239:37]
wire w1_11 = io_din[20]; // @[beh_lib.scala 240:37]
wire w0_12 = io_din[21]; // @[beh_lib.scala 239:37]
wire w2_11 = io_din[22]; // @[beh_lib.scala 241:37]
wire w0_13 = io_din[23]; // @[beh_lib.scala 239:37]
wire w1_13 = io_din[24]; // @[beh_lib.scala 240:37]
wire w0_14 = io_din[25]; // @[beh_lib.scala 239:37]
wire w0_15 = io_din[26]; // @[beh_lib.scala 239:37]
wire w1_15 = io_din[27]; // @[beh_lib.scala 240:37]
wire w0_16 = io_din[28]; // @[beh_lib.scala 239:37]
wire w2_15 = io_din[29]; // @[beh_lib.scala 241:37]
wire w0_17 = io_din[30]; // @[beh_lib.scala 239:37]
wire w1_17 = io_din[31]; // @[beh_lib.scala 240:37]
wire [5:0] _T_100 = {w1_17,w0_17,w2_15,w0_16,w1_15,w0_15}; // @[beh_lib.scala 247:86]
wire _T_101 = ^_T_100; // @[beh_lib.scala 247:93]
wire _T_102 = io_ecc_in[5] ^ _T_101; // @[beh_lib.scala 247:81]
wire [6:0] _T_109 = {w0_10,w1_9,w0_9,w2_7,w0_8,w1_7,w0_7}; // @[beh_lib.scala 247:116]
wire [14:0] _T_117 = {w0_14,w1_13,w0_13,w2_11,w0_12,w1_11,w0_11,w3_7,_T_109}; // @[beh_lib.scala 247:116]
wire _T_118 = ^_T_117; // @[beh_lib.scala 247:123]
wire _T_119 = io_ecc_in[4] ^ _T_118; // @[beh_lib.scala 247:111]
wire [6:0] _T_126 = {w0_6,w1_5,w0_5,w2_3,w0_4,w1_3,w0_3}; // @[beh_lib.scala 247:146]
wire [14:0] _T_134 = {w0_14,w1_13,w0_13,w2_11,w0_12,w1_11,w0_11,w3_7,_T_126}; // @[beh_lib.scala 247:146]
wire _T_135 = ^_T_134; // @[beh_lib.scala 247:153]
wire _T_136 = io_ecc_in[3] ^ _T_135; // @[beh_lib.scala 247:141]
wire [8:0] _T_145 = {w0_9,w2_7,w0_6,w1_5,w0_5,w2_3,w0_2,w1_1,w0_1}; // @[beh_lib.scala 247:176]
wire [17:0] _T_154 = {w1_17,w0_17,w2_15,w0_14,w1_13,w0_13,w2_11,w0_10,w1_9,_T_145}; // @[beh_lib.scala 247:176]
wire _T_155 = ^_T_154; // @[beh_lib.scala 247:183]
wire _T_156 = io_ecc_in[2] ^ _T_155; // @[beh_lib.scala 247:171]
wire [8:0] _T_165 = {w0_8,w1_7,w0_6,w1_5,w0_4,w1_3,w0_2,w1_1,w0_0}; // @[beh_lib.scala 247:206]
wire [17:0] _T_174 = {w1_17,w0_16,w1_15,w0_14,w1_13,w0_12,w1_11,w0_10,w1_9,_T_165}; // @[beh_lib.scala 247:206]
wire _T_175 = ^_T_174; // @[beh_lib.scala 247:213]
wire _T_176 = io_ecc_in[1] ^ _T_175; // @[beh_lib.scala 247:201]
wire [8:0] _T_185 = {w0_8,w0_7,w0_6,w0_5,w0_4,w0_3,w0_2,w0_1,w0_0}; // @[beh_lib.scala 247:236]
wire [17:0] _T_194 = {w0_17,w0_16,w0_15,w0_14,w0_13,w0_12,w0_11,w0_10,w0_9,_T_185}; // @[beh_lib.scala 247:236]
wire _T_195 = ^_T_194; // @[beh_lib.scala 247:243]
wire _T_196 = io_ecc_in[0] ^ _T_195; // @[beh_lib.scala 247:231]
wire [6:0] ecc_check = {1'h0,_T_102,_T_119,_T_136,_T_156,_T_176,_T_196}; // @[Cat.scala 29:58]
wire error_mask_0 = ecc_check[5:0] == 6'h1; // @[beh_lib.scala 255:39]
wire error_mask_1 = ecc_check[5:0] == 6'h2; // @[beh_lib.scala 255:39]
wire error_mask_2 = ecc_check[5:0] == 6'h3; // @[beh_lib.scala 255:39]
wire error_mask_3 = ecc_check[5:0] == 6'h4; // @[beh_lib.scala 255:39]
wire error_mask_4 = ecc_check[5:0] == 6'h5; // @[beh_lib.scala 255:39]
wire error_mask_5 = ecc_check[5:0] == 6'h6; // @[beh_lib.scala 255:39]
wire error_mask_6 = ecc_check[5:0] == 6'h7; // @[beh_lib.scala 255:39]
wire error_mask_7 = ecc_check[5:0] == 6'h8; // @[beh_lib.scala 255:39]
wire error_mask_8 = ecc_check[5:0] == 6'h9; // @[beh_lib.scala 255:39]
wire error_mask_9 = ecc_check[5:0] == 6'ha; // @[beh_lib.scala 255:39]
wire error_mask_10 = ecc_check[5:0] == 6'hb; // @[beh_lib.scala 255:39]
wire error_mask_11 = ecc_check[5:0] == 6'hc; // @[beh_lib.scala 255:39]
wire error_mask_12 = ecc_check[5:0] == 6'hd; // @[beh_lib.scala 255:39]
wire error_mask_13 = ecc_check[5:0] == 6'he; // @[beh_lib.scala 255:39]
wire error_mask_14 = ecc_check[5:0] == 6'hf; // @[beh_lib.scala 255:39]
wire error_mask_15 = ecc_check[5:0] == 6'h10; // @[beh_lib.scala 255:39]
wire error_mask_16 = ecc_check[5:0] == 6'h11; // @[beh_lib.scala 255:39]
wire error_mask_17 = ecc_check[5:0] == 6'h12; // @[beh_lib.scala 255:39]
wire error_mask_18 = ecc_check[5:0] == 6'h13; // @[beh_lib.scala 255:39]
wire error_mask_19 = ecc_check[5:0] == 6'h14; // @[beh_lib.scala 255:39]
wire error_mask_20 = ecc_check[5:0] == 6'h15; // @[beh_lib.scala 255:39]
wire error_mask_21 = ecc_check[5:0] == 6'h16; // @[beh_lib.scala 255:39]
wire error_mask_22 = ecc_check[5:0] == 6'h17; // @[beh_lib.scala 255:39]
wire error_mask_23 = ecc_check[5:0] == 6'h18; // @[beh_lib.scala 255:39]
wire error_mask_24 = ecc_check[5:0] == 6'h19; // @[beh_lib.scala 255:39]
wire error_mask_25 = ecc_check[5:0] == 6'h1a; // @[beh_lib.scala 255:39]
wire error_mask_26 = ecc_check[5:0] == 6'h1b; // @[beh_lib.scala 255:39]
wire error_mask_27 = ecc_check[5:0] == 6'h1c; // @[beh_lib.scala 255:39]
wire error_mask_28 = ecc_check[5:0] == 6'h1d; // @[beh_lib.scala 255:39]
wire error_mask_29 = ecc_check[5:0] == 6'h1e; // @[beh_lib.scala 255:39]
wire error_mask_30 = ecc_check[5:0] == 6'h1f; // @[beh_lib.scala 255:39]
wire error_mask_31 = ecc_check[5:0] == 6'h20; // @[beh_lib.scala 255:39]
wire error_mask_32 = ecc_check[5:0] == 6'h21; // @[beh_lib.scala 255:39]
wire error_mask_33 = ecc_check[5:0] == 6'h22; // @[beh_lib.scala 255:39]
wire error_mask_34 = ecc_check[5:0] == 6'h23; // @[beh_lib.scala 255:39]
wire error_mask_35 = ecc_check[5:0] == 6'h24; // @[beh_lib.scala 255:39]
wire error_mask_36 = ecc_check[5:0] == 6'h25; // @[beh_lib.scala 255:39]
wire error_mask_37 = ecc_check[5:0] == 6'h26; // @[beh_lib.scala 255:39]
wire error_mask_38 = ecc_check[5:0] == 6'h27; // @[beh_lib.scala 255:39]
wire [7:0] _T_310 = {io_ecc_in[3],io_din[3:1],io_ecc_in[2],w0_0,io_ecc_in[1:0]}; // @[Cat.scala 29:58]
wire [38:0] din_plus_parity = {io_ecc_in[6],io_din[31:26],io_ecc_in[5],io_din[25:11],io_ecc_in[4],io_din[10:4],_T_310}; // @[Cat.scala 29:58]
wire [9:0] _T_333 = {error_mask_18,error_mask_17,error_mask_16,error_mask_15,error_mask_14,error_mask_13,error_mask_12,error_mask_11,error_mask_10,error_mask_9}; // @[beh_lib.scala 258:70]
wire [18:0] _T_334 = {_T_333,error_mask_8,error_mask_7,error_mask_6,error_mask_5,error_mask_4,error_mask_3,error_mask_2,error_mask_1,error_mask_0}; // @[beh_lib.scala 258:70]
wire [9:0] _T_343 = {error_mask_28,error_mask_27,error_mask_26,error_mask_25,error_mask_24,error_mask_23,error_mask_22,error_mask_21,error_mask_20,error_mask_19}; // @[beh_lib.scala 258:70]
wire [9:0] _T_352 = {error_mask_38,error_mask_37,error_mask_36,error_mask_35,error_mask_34,error_mask_33,error_mask_32,error_mask_31,error_mask_30,error_mask_29}; // @[beh_lib.scala 258:70]
wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[beh_lib.scala 258:70]
wire [38:0] _T_355 = _T_354 ^ din_plus_parity; // @[beh_lib.scala 258:77]
wire [38:0] dout_plus_parity = io_single_ecc_error ? _T_355 : din_plus_parity; // @[beh_lib.scala 258:29]
wire [3:0] _T_361 = {dout_plus_parity[6:4],dout_plus_parity[2]}; // @[Cat.scala 29:58]
wire [27:0] _T_363 = {dout_plus_parity[37:32],dout_plus_parity[30:16],dout_plus_parity[14:8]}; // @[Cat.scala 29:58]
wire _T_367 = ecc_check == 7'h40; // @[beh_lib.scala 261:60]
wire _T_368 = dout_plus_parity[38] ^ _T_367; // @[beh_lib.scala 261:42]
wire [3:0] _T_375 = {dout_plus_parity[7],dout_plus_parity[3],dout_plus_parity[1:0]}; // @[Cat.scala 29:58]
wire [2:0] _T_377 = {_T_368,dout_plus_parity[31],dout_plus_parity[15]}; // @[Cat.scala 29:58]
assign io_ecc_out = {_T_377,_T_375}; // @[beh_lib.scala 248:14 beh_lib.scala 261:14]
assign io_dout = {_T_363,_T_361}; // @[beh_lib.scala 260:11]
assign io_single_ecc_error = 1'h0; // @[beh_lib.scala 250:23]
endmodule
module EL2_IC_TAG(
input clock,
input reset,
input io_clk,
input io_rst_l,
input io_clk_override,
input io_dec_tlu_core_ecc_disable,
input [31:0] io_ic_rw_addr,
input [1:0] io_ic_wr_en,
input [1:0] io_ic_tag_valid,
input io_ic_rd_en,
input [12:0] io_ic_debug_addr,
input io_ic_debug_rd_en,
input io_ic_debug_wr_en,
input io_ic_debug_tag_array,
input [1:0] io_ic_debug_way,
output [25:0] io_ictag_debug_rd_data,
input [70:0] io_ic_debug_wr_data,
output [1:0] io_ic_rd_hit,
output io_ic_tag_perr,
input io_scan_mode,
output [25:0] io_test,
output [31:0] io_test_ecc_data_out_0,
output [31:0] io_test_ecc_data_out_1,
output [6:0] io_test_ecc_out_0,
output [6:0] io_test_ecc_out_1,
output io_test_ecc_sb_out_0,
output io_test_ecc_sb_out_1,
output io_test_ecc_db_out_0,
output io_test_ecc_db_out_1
);
`ifdef RANDOMIZE_MEM_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_1;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
reg [25:0] ic_way_tag_0 [0:127]; // @[el2_ifu_ic_mem.scala 125:46]
wire [25:0] ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 125:46]
wire [6:0] ic_way_tag_0_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 125:46]
wire [25:0] ic_way_tag_0__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
wire [6:0] ic_way_tag_0__T_487_addr; // @[el2_ifu_ic_mem.scala 125:46]
wire ic_way_tag_0__T_487_mask; // @[el2_ifu_ic_mem.scala 125:46]
wire ic_way_tag_0__T_487_en; // @[el2_ifu_ic_mem.scala 125:46]
reg [6:0] ic_way_tag_0_ic_tag_data_raw_addr_pipe_0;
reg [25:0] ic_way_tag_1 [0:127]; // @[el2_ifu_ic_mem.scala 125:46]
wire [25:0] ic_way_tag_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 125:46]
wire [6:0] ic_way_tag_1_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 125:46]
wire [25:0] ic_way_tag_1__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
wire [6:0] ic_way_tag_1__T_487_addr; // @[el2_ifu_ic_mem.scala 125:46]
wire ic_way_tag_1__T_487_mask; // @[el2_ifu_ic_mem.scala 125:46]
wire ic_way_tag_1__T_487_en; // @[el2_ifu_ic_mem.scala 125:46]
reg [6:0] ic_way_tag_1_ic_tag_data_raw_addr_pipe_0;
wire [31:0] rvecc_decode_io_din; // @[el2_ifu_ic_mem.scala 149:27]
wire [6:0] rvecc_decode_io_ecc_in; // @[el2_ifu_ic_mem.scala 149:27]
wire [6:0] rvecc_decode_io_ecc_out; // @[el2_ifu_ic_mem.scala 149:27]
wire [31:0] rvecc_decode_io_dout; // @[el2_ifu_ic_mem.scala 149:27]
wire rvecc_decode_io_single_ecc_error; // @[el2_ifu_ic_mem.scala 149:27]
wire [31:0] rvecc_decode_1_io_din; // @[el2_ifu_ic_mem.scala 149:27]
wire [6:0] rvecc_decode_1_io_ecc_in; // @[el2_ifu_ic_mem.scala 149:27]
wire [6:0] rvecc_decode_1_io_ecc_out; // @[el2_ifu_ic_mem.scala 149:27]
wire [31:0] rvecc_decode_1_io_dout; // @[el2_ifu_ic_mem.scala 149:27]
wire rvecc_decode_1_io_single_ecc_error; // @[el2_ifu_ic_mem.scala 149:27]
wire _T_2 = io_ic_rw_addr[5:4] == 2'h1; // @[el2_ifu_ic_mem.scala 73:93]
wire [1:0] _T_4 = {_T_2,_T_2}; // @[Cat.scala 29:58]
wire [1:0] ic_tag_wren = io_ic_wr_en & _T_4; // @[el2_ifu_ic_mem.scala 73:33]
wire _T_5 = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 75:68]
wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
wire [1:0] ic_debug_rd_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 75:93]
wire _T_8 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 76:68]
wire [1:0] _T_10 = {_T_8,_T_8}; // @[Cat.scala 29:58]
wire [1:0] ic_debug_wr_way_en = _T_10 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 76:93]
wire _T_11 = io_ic_rd_en | io_clk_override; // @[el2_ifu_ic_mem.scala 77:55]
wire [1:0] _T_13 = {_T_11,_T_11}; // @[Cat.scala 29:58]
wire [1:0] _T_14 = _T_13 | io_ic_wr_en; // @[el2_ifu_ic_mem.scala 77:74]
wire [1:0] _T_15 = _T_14 | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 77:88]
wire [1:0] ic_tag_clken = _T_15 | ic_debug_rd_way_en; // @[el2_ifu_ic_mem.scala 77:109]
reg [31:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 80:30]
wire [1:0] ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 82:35]
wire [31:0] _T_30 = {13'h0,io_ic_rw_addr[31:13]}; // @[Cat.scala 29:58]
wire [8:0] _T_134 = {_T_30[16],_T_30[14],_T_30[12],_T_30[10],_T_30[8],_T_30[6],_T_30[5],_T_30[3],_T_30[1]}; // @[el2_lib.scala 211:22]
wire [17:0] _T_143 = {_T_30[31],_T_30[30],_T_30[28],_T_30[27],_T_30[25],_T_30[23],_T_30[21],_T_30[20],_T_30[18],_T_134}; // @[el2_lib.scala 211:22]
wire _T_144 = ^_T_143; // @[el2_lib.scala 211:29]
wire [8:0] _T_152 = {_T_30[15],_T_30[14],_T_30[11],_T_30[10],_T_30[7],_T_30[6],_T_30[4],_T_30[3],_T_30[0]}; // @[el2_lib.scala 211:39]
wire [17:0] _T_161 = {_T_30[31],_T_30[29],_T_30[28],_T_30[26],_T_30[25],_T_30[22],_T_30[21],_T_30[19],_T_30[18],_T_152}; // @[el2_lib.scala 211:39]
wire _T_162 = ^_T_161; // @[el2_lib.scala 211:46]
wire [8:0] _T_170 = {_T_30[15],_T_30[14],_T_30[9],_T_30[8],_T_30[7],_T_30[6],_T_30[2],_T_30[1],_T_30[0]}; // @[el2_lib.scala 211:56]
wire [17:0] _T_179 = {_T_30[30],_T_30[29],_T_30[28],_T_30[24],_T_30[23],_T_30[22],_T_30[21],_T_30[17],_T_30[16],_T_170}; // @[el2_lib.scala 211:56]
wire _T_180 = ^_T_179; // @[el2_lib.scala 211:63]
wire [6:0] _T_186 = {_T_30[12],_T_30[11],_T_30[10],_T_30[9],_T_30[8],_T_30[7],_T_30[6]}; // @[el2_lib.scala 211:73]
wire [14:0] _T_194 = {_T_30[27],_T_30[26],_T_30[25],_T_30[24],_T_30[23],_T_30[22],_T_30[21],_T_30[13],_T_186}; // @[el2_lib.scala 211:73]
wire _T_195 = ^_T_194; // @[el2_lib.scala 211:80]
wire [14:0] _T_209 = {_T_30[20],_T_30[19],_T_30[18],_T_30[17],_T_30[16],_T_30[15],_T_30[14],_T_30[13],_T_186}; // @[el2_lib.scala 211:90]
wire _T_210 = ^_T_209; // @[el2_lib.scala 211:97]
wire [5:0] _T_215 = {_T_30[5],_T_30[4],_T_30[3],_T_30[2],_T_30[1],_T_30[0]}; // @[el2_lib.scala 211:107]
wire _T_216 = ^_T_215; // @[el2_lib.scala 211:114]
wire [5:0] _T_221 = {_T_144,_T_162,_T_180,_T_195,_T_210,_T_216}; // @[Cat.scala 29:58]
wire _T_222 = ^_T_30; // @[el2_lib.scala 212:13]
wire _T_223 = ^_T_221; // @[el2_lib.scala 212:23]
wire _T_224 = _T_222 ^ _T_223; // @[el2_lib.scala 212:18]
wire [6:0] _T_225 = {_T_224,_T_144,_T_162,_T_180,_T_195,_T_210,_T_216}; // @[Cat.scala 29:58]
wire [25:0] _T_229 = {io_ic_debug_wr_data[68:64],io_ic_debug_wr_data[31:11]}; // @[Cat.scala 29:58]
wire [25:0] _T_463 = {_T_225[4:0],2'h0,io_ic_rw_addr[31:13]}; // @[Cat.scala 29:58]
wire _T_478 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 119:44]
reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 123:38]
wire [25:0] _GEN_17 = ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 137:75]
wire [25:0] _GEN_18 = ic_way_tag_0_ic_tag_data_raw_data[0] ? ic_way_tag_1_ic_tag_data_raw_data : _GEN_17; // @[el2_ifu_ic_mem.scala 137:75]
wire [36:0] w_tout_0 = {_GEN_18[25:21],_GEN_18[18:0],13'h0}; // @[Cat.scala 29:58]
wire [25:0] _GEN_22 = ic_way_tag_1_ic_tag_data_raw_data[0] ? ic_way_tag_1_ic_tag_data_raw_data : _GEN_17; // @[el2_ifu_ic_mem.scala 137:75]
wire [36:0] w_tout_1 = {_GEN_22[25:21],_GEN_22[18:0],13'h0}; // @[Cat.scala 29:58]
wire ic_tag_way_perr_0 = io_test_ecc_sb_out_0 | io_test_ecc_db_out_0; // @[el2_ifu_ic_mem.scala 165:54]
wire ic_tag_way_perr_1 = io_test_ecc_sb_out_1 | io_test_ecc_db_out_1; // @[el2_ifu_ic_mem.scala 165:54]
wire [9:0] _T_533 = {ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
wire [18:0] _T_542 = {_T_533,ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
wire [25:0] _T_549 = {_T_542,ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
wire [25:0] _T_550 = _T_549 & ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 168:75]
wire [9:0] _T_561 = {ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
wire [18:0] _T_570 = {_T_561,ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
wire [25:0] _T_577 = {_T_570,ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
wire [25:0] _T_578 = _T_577 & ic_way_tag_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 168:75]
wire [36:0] _T_636 = w_tout_0 & w_tout_1; // @[el2_ifu_ic_mem.scala 176:31]
wire [1:0] _T_637 = {ic_tag_way_perr_0,ic_tag_way_perr_1}; // @[Cat.scala 29:58]
wire [1:0] _T_638 = _T_637 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 177:55]
wire _T_642 = w_tout_0[31:13] == ic_rw_addr_ff[31:13]; // @[el2_ifu_ic_mem.scala 179:88]
wire [1:0] _GEN_25 = {{1'd0}, _T_642}; // @[el2_ifu_ic_mem.scala 179:133]
wire [1:0] _T_643 = _GEN_25 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 179:133]
wire _T_646 = w_tout_1[31:13] == ic_rw_addr_ff[31:13]; // @[el2_ifu_ic_mem.scala 179:88]
wire [1:0] _GEN_26 = {{1'd0}, _T_646}; // @[el2_ifu_ic_mem.scala 179:133]
wire [1:0] _T_647 = _GEN_26 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 179:133]
wire [3:0] _T_649 = {_T_643,_T_647}; // @[Cat.scala 29:58]
rvecc_decode rvecc_decode ( // @[el2_ifu_ic_mem.scala 149:27]
.io_din(rvecc_decode_io_din),
.io_ecc_in(rvecc_decode_io_ecc_in),
.io_ecc_out(rvecc_decode_io_ecc_out),
.io_dout(rvecc_decode_io_dout),
.io_single_ecc_error(rvecc_decode_io_single_ecc_error)
);
rvecc_decode rvecc_decode_1 ( // @[el2_ifu_ic_mem.scala 149:27]
.io_din(rvecc_decode_1_io_din),
.io_ecc_in(rvecc_decode_1_io_ecc_in),
.io_ecc_out(rvecc_decode_1_io_ecc_out),
.io_dout(rvecc_decode_1_io_dout),
.io_single_ecc_error(rvecc_decode_1_io_single_ecc_error)
);
assign ic_way_tag_0_ic_tag_data_raw_addr = ic_way_tag_0_ic_tag_data_raw_addr_pipe_0;
assign ic_way_tag_0_ic_tag_data_raw_data = ic_way_tag_0[ic_way_tag_0_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 125:46]
assign ic_way_tag_0__T_487_data = _T_8 ? _T_229 : _T_463;
assign ic_way_tag_0__T_487_addr = _T_478 ? io_ic_debug_addr[12:6] : io_ic_rw_addr[12:6];
assign ic_way_tag_0__T_487_mask = ic_tag_wren_q[0] & ic_tag_clken[0];
assign ic_way_tag_0__T_487_en = 1'h1;
assign ic_way_tag_1_ic_tag_data_raw_addr = ic_way_tag_1_ic_tag_data_raw_addr_pipe_0;
assign ic_way_tag_1_ic_tag_data_raw_data = ic_way_tag_1[ic_way_tag_1_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 125:46]
assign ic_way_tag_1__T_487_data = _T_8 ? _T_229 : _T_463;
assign ic_way_tag_1__T_487_addr = _T_478 ? io_ic_debug_addr[12:6] : io_ic_rw_addr[12:6];
assign ic_way_tag_1__T_487_mask = ic_tag_wren_q[1] & ic_tag_clken[1];
assign ic_way_tag_1__T_487_en = 1'h1;
assign io_ictag_debug_rd_data = _T_550 | _T_578; // @[el2_ifu_ic_mem.scala 175:26]
assign io_ic_rd_hit = _T_649[1:0]; // @[el2_ifu_ic_mem.scala 179:16]
assign io_ic_tag_perr = |_T_638; // @[el2_ifu_ic_mem.scala 177:18]
assign io_test = _T_636[25:0]; // @[el2_ifu_ic_mem.scala 176:13]
assign io_test_ecc_data_out_0 = rvecc_decode_io_dout; // @[el2_ifu_ic_mem.scala 160:29]
assign io_test_ecc_data_out_1 = rvecc_decode_1_io_dout; // @[el2_ifu_ic_mem.scala 160:29]
assign io_test_ecc_out_0 = rvecc_decode_io_ecc_out; // @[el2_ifu_ic_mem.scala 161:24]
assign io_test_ecc_out_1 = rvecc_decode_1_io_ecc_out; // @[el2_ifu_ic_mem.scala 161:24]
assign io_test_ecc_sb_out_0 = 1'h0; // @[el2_ifu_ic_mem.scala 162:27]
assign io_test_ecc_sb_out_1 = 1'h0; // @[el2_ifu_ic_mem.scala 162:27]
assign io_test_ecc_db_out_0 = 1'h0; // @[el2_ifu_ic_mem.scala 163:27]
assign io_test_ecc_db_out_1 = 1'h0; // @[el2_ifu_ic_mem.scala 163:27]
assign rvecc_decode_io_din = {11'h0,ic_way_tag_0_ic_tag_data_raw_data[20:0]}; // @[el2_ifu_ic_mem.scala 152:26]
assign rvecc_decode_io_ecc_in = {2'h0,ic_way_tag_0_ic_tag_data_raw_data[25:21]}; // @[el2_ifu_ic_mem.scala 153:29]
assign rvecc_decode_1_io_din = {11'h0,ic_way_tag_1_ic_tag_data_raw_data[20:0]}; // @[el2_ifu_ic_mem.scala 152:26]
assign rvecc_decode_1_io_ecc_in = {2'h0,ic_way_tag_1_ic_tag_data_raw_data[25:21]}; // @[el2_ifu_ic_mem.scala 153:29]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_MEM_INIT
_RAND_0 = {1{`RANDOM}};
for (initvar = 0; initvar < 128; initvar = initvar+1)
ic_way_tag_0[initvar] = _RAND_0[25:0];
_RAND_2 = {1{`RANDOM}};
for (initvar = 0; initvar < 128; initvar = initvar+1)
ic_way_tag_1[initvar] = _RAND_2[25:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 = _RAND_1[6:0];
_RAND_3 = {1{`RANDOM}};
ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 = _RAND_3[6:0];
_RAND_4 = {1{`RANDOM}};
ic_rw_addr_ff = _RAND_4[31:0];
_RAND_5 = {1{`RANDOM}};
ic_debug_rd_way_en_ff = _RAND_5[1:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock) begin
if(ic_way_tag_0__T_487_en & ic_way_tag_0__T_487_mask) begin
ic_way_tag_0[ic_way_tag_0__T_487_addr] <= ic_way_tag_0__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
end
if (_T_478) begin
ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 <= io_ic_debug_addr[12:6];
end else begin
ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 <= io_ic_rw_addr[12:6];
end
if(ic_way_tag_1__T_487_en & ic_way_tag_1__T_487_mask) begin
ic_way_tag_1[ic_way_tag_1__T_487_addr] <= ic_way_tag_1__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
end
if (_T_478) begin
ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 <= io_ic_debug_addr[12:6];
end else begin
ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 <= io_ic_rw_addr[12:6];
end
if (reset) begin
ic_rw_addr_ff <= 32'h0;
end else begin
ic_rw_addr_ff <= io_ic_rw_addr;
end
if (reset) begin
ic_debug_rd_way_en_ff <= 2'h0;
end else begin
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
end
end
endmodule

9
InoutPort.v
View File

@ -1,9 +0,0 @@
module InoutPort( inout [15:0] a,
input [15:0] b,
input sel,
output [15:0] c);
assign a = sel ? 'bz : b;
assign c = sel ? a : 'bz;
endmodule

24
MakeInout.anno.json
View File

@ -1,24 +0,0 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxInlineAnno",
"target":"MakeInout.rvdff",
"name":"rvdff.v",
"text":"\nmodule InoutPort( input [15:0] in,\n input clk,\n input reset,\n output [15:0] out);\n always@(posedge clk or negedge reset)\n begin\n if(reset == 0)\n out <= 0;\n else\n out <= in\n end\nendmodule\n "
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"MakeInout"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

26
MakeInout.fir
View File

@ -1,26 +0,0 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit MakeInout :
extmodule rvdff :
input in : UInt<16>
input clk : Clock
input reset : UInt<1>
output out : UInt<16>
defname = rvdff
module MakeInout :
input clock : Clock
input reset : UInt<1>
output io : {flip in : UInt<16>, flip clk : Clock, flip reset : UInt<1>, out : UInt<16>}
inst m of rvdff @[GCD.scala 40:17]
m.out is invalid
m.reset is invalid
m.clk is invalid
m.in is invalid
io.out <= m.out @[GCD.scala 42:8]
m.reset <= io.reset @[GCD.scala 42:8]
m.clk <= io.clk @[GCD.scala 42:8]
m.in <= io.in @[GCD.scala 42:8]

23
MakeInout.v
View File

@ -1,23 +0,0 @@
module MakeInout(
input clock,
input reset,
input [15:0] io_in,
input io_clk,
input io_reset,
output [15:0] io_out
);
wire [15:0] m_in; // @[GCD.scala 40:17]
wire m_clk; // @[GCD.scala 40:17]
wire m_reset; // @[GCD.scala 40:17]
wire [15:0] m_out; // @[GCD.scala 40:17]
rvdff m ( // @[GCD.scala 40:17]
.in(m_in),
.clk(m_clk),
.reset(m_reset),
.out(m_out)
);
assign io_out = m_out; // @[GCD.scala 42:8]
assign m_in = io_in; // @[GCD.scala 42:8]
assign m_clk = io_clk; // @[GCD.scala 42:8]
assign m_reset = io_reset; // @[GCD.scala 42:8]
endmodule

273
README.md
View File

@ -1,27 +1,260 @@
# EL2 SweRV RISC-V Core Chiselified Version from <> LAMPRO MELLON
# Quasar RISC-V Core 2.0 from Lampro Mellon
This repository contains the SweRV EL2 Core design in CHISEL
This repository contains the Quasar Core design in CHISEL.
## Back ground
## License
The project is being made for learning purpose. Copy rights to the SweRV-EL2 belongs to Wrestern Digital
By contributing to this project, you agree that your contribution is governed by [Apache-2.0](LICENSE).
Files under the [tools](tools/) directory may be available under a different license. Please review individual file for details.
## Background
Quasar is a Chiselified version of EL2 SweRV RISC-V Core.
## Directory Structure
├── configs # Configurations Dir
│   └── snapshots # Where generated configuration files are created
├── design # Design root dir
│   ├── dbg # Debugger
│   ├── dec # Decode, Registers and Exceptions
│   ├── dmi # DMI block
│   ├── exu # EXU (ALU/MUL/DIV)
│   ├── ifu # Fetch & Branch Prediction
│   ├── include
│   ├── lib
│   └── lsu # Load/Store
├── docs
├── tools # Scripts/Makefiles
└── testbench # (Very) simple testbench
   ├── asm # Example assembly files
   └── hex # Canned demo hex files
├── configs # Configurations dir
├── design
│ ├── project
│ ├── project
│ └── target
│ ├── snapshots
│ └── default # Where generated configuration files are created
│ ├── src
│ ├── main
│ ├── resources
│ └── vsrc # Blackbox files dir
│ └── scala # Design root dir
│ ├── dbg # Debugger
│ ├── dec # Decode, Registers and Exceptions
│ ├── dmi # DMI block
│ ├── exu # EXU (ALU/MUL/DIV)
│ ├── ifu # Fetch & Branch Prediction
│ ├── include # Bundles file
│ ├── lib # Bridges and Library
│ └── lsu # Load/Store
│ └── test
│ ├── target
│ └── test_run_dir
├── doc # PPA Report
├── generated_rtl # Quasar wrapper
├── testbench
│ ├── asm # Example assembly files
│ ├── hex # Canned demo hex files
│ └── tests # Example tests
├── tools # Scripts/Makefiles
├── tracer_logs # generated log files
└── verif
├── LEC
├── formality_work
└── formality_log # LEC log files
└── setup_files # user_match files
└── sim # Simulation log/dump files
## Dependencies
- Verilator **(4.102 or later)** must be installed on the system if running with verilator.
- Vcs must be installed on the system if running with vcs.
- RISCV tool chain (based on gcc version 8.3 or higher) must be
installed so that it can be used to prepare RISCV binaries to run.
- Sbt **(1.3.13 or later)** must be installed on the system.
## Quickstart guide
1. Clone the repository
2. Setup RV_ROOT to point to the path in your local filesystem
3. Determine your configuration {optional}
4. Run make with $RV_ROOT/tools/Makefile
## Release Notes for this version
Please see [release-notes](release-notes.md) for changes and bug fixes in this version of Quasar.
### Configurations
Quasar can be configured by running the script:
```
$RV_ROOT/configs/quasar.config
```
For detailed help options.
```
$RV_ROOT/configs/quasar.config -h
```
For example, to build with a DCCM of size 64Kb:
```
$RV_ROOT/configs/quasar.config -dccm_size=64
```
This will update the **default** snapshot in `$RV_ROOT/design/snapshots/default/` with parameters for a 64K DCCM.
Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot *dccm64* and refer to it during the build.
There are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via the `-target=name` option to quasar.config.
This script derives the following consistent set of include files :
```
$RV_ROOT/design/snapshots/default
├── common_defines.vh # `defines for testbench or design
├── defines.h # defines for C/assembly headers
├── param.vh # Design parameters
├── pdef.vh # Parameter structure
├── pd_defines.vh # `defines for physical design
├── perl_configs.pl # Perl %configs hash for scripting
├── pic_map_auto.h # PIC memory map based on configure size
├── whisper.json # JSON file for swerv-iss
└── link.ld # default linker control file
```
#### 1. Generate scala parameter
```
make -f $RV_ROOT/tools/Makefile conf
```
This script will run `quasar.config` and derives the include file:
```
$RV_ROOT/design/src/main/scala/lib
└── param.scala # Scala design parameters
```
### Running RTL Simulation
while in a work directory:
#### 1. Set the RV_ROOT environment variable to the root of the Quasar directory structure.
Example for bash shell:
```
export RV_ROOT=$(pwd)
```
Example for csh or its derivatives:
```
setenv RV_ROOT /path/to/QUASAR
```
#### 2. Create your specific configuration
*(Skip if default is sufficient)*
*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)*. For example, if `mybuild` is the name for the snapshot:
set BUILD_PATH environment variable:
```
setenv BUILD_PATH snapshots/mybuild
$RV_ROOT/configs/quasar.config [configuration options..] -snapshot=mybuild
```
Snapshots are placed in `$BUILD_PATH` directory.
#### 3. Run sbt
```
make -f $RV_ROOT/tools/Makefile sbt_
```
This command will generate the Quasar wrapper in system verilog of Quasar chisel, in the `generated_rtl` directory and runs the `reset_script.py`
* In the reset_script we do a post verilog-generation changes, these changes are as follows:
* Replace `posedge reset` with `negedge reset`
* Replace `if (reset)` with `if (~reset)`
#### 4. Running a simple Hello World program (verilator)
```
make -f $RV_ROOT/tools/Makefile
```
This command will build a verilator model of Quasar with AXI bus, and execute a short sequence of instructions that writes out "HELLO WORLD"
to the bus.
The simulation produces output on the screen like:
```
VerilatorTB: Start of sim
----------------------------------
Hello World from QUASAR @LMDC !!
----------------------------------
TEST_PASSED
Finished : minstret = 437, mcycle = 922
See "exec.log" for execution trace with register updates..
```
The simulation generates following files in `$RV_ROOT/verif/sim`:
`console.log` contains what the cpu writes to the console address of 0xd0580000.
`exec.log` shows instruction trace with GPR updates.
`trace_port.csv` contains a log of the trace port.
Other log files are `dec.log`, `exu.log`, `ifu.log`, `lsu.log` and `pic.log`, generates in `$RV_ROOT/tracer_logs`.
When `debug=1` is provided, a vcd file `sim.vcd` is created and can be browsed by gtkwave or similar waveform viewers.
You can re-execute simulation using:
```
make -f $RV_ROOT/tools/Makefile verilator
```
#### 5. Default for VCS/Verilotor
If you want to run default configuration on verilator use the following command
```
make -f $RV_ROOT/tools/Makefile
```
For VCS use
```
make -f $RV_ROOT/tools/Makefile vcs_all
```
The simulation run/build command has following generic form:
```
make -f $RV_ROOT/tools/Makefile [<simulator>] [debug=1] [snapshot=mybuild] [target=<target>] [TEST=<test>] [TEST_DIR=<path_to_test_dir>]
```
where:
```
<simulator> - can be 'verilator' (by default) , 'vcs' - Synopsys VCS, 'riviera'- Aldec Riviera-PRO. If not provided, 'make' cleans work directory, builds verilator executable and runs a test.
debug=1 - allows VCD generation for verilator and VCS and SHM waves for irun option.
<target> - predefined CPU configurations 'default' ( by default), 'default_ahb', 'typical_pd', 'high_perf'.
TEST - allows to run a C (<test>.c) or assembly (<test>.s) test, hello_world is run by default.
TEST_DIR - alternative to test source directory testbench/asm or testbench/tests.
<snapshot> - run and build executable model of custom CPU configuration, remember to provide 'snapshot' argument for runs on custom configurations.
CONF_PARAMS - allows to provide -set options to quasar.conf script to alter predefined targets parameters.
```
Example:
```
make -f $RV_ROOT/tools/Makefile verilator TEST=cmark
```
will build and simulate `testbench/asm/cmark.c` program with verilator.
If you want to compile a test only, you can run:
```
make -f $RV_ROOT/tools/Makefile program.hex TEST=<test> [TEST_DIR=/path/to/dir]
```
The Makefile uses `snapshot/<target>/link.ld` file, generated by quasar.conf script by default to build test executable. User can provide test specific linker file in form `<test_name>.ld` to build the test executable, in the same directory with the test source.
User also can create a test specific makefile in form `<test_name>.makefile`, containing building instructions how to create `program.hex` file used by simulation. The private makefile should be in the same directory as the test source. See examples in `testbench/asm` directory.
*(`program.hex` file is loaded to instruction and LSU bus memory slaves and optionally to DCCM/ICCM at the beginning of simulation)*.
User can build `program.hex` file by any other means and then run simulation with following command:
make -f $RV_ROOT/tools/Makefile <simulator>
Note: You may need to delete `program.hex` file from work directory, when run a new test.
The `$RV_ROOT/testbench/asm` directory contains following tests ready to simulate:
```
hello_world - default test program to run, prints Hello World message to screen and console.log
hello_world_dccm - the same as above, but takes the string from preloaded DCCM.
hello_world_iccm - the same as hello_world, but loads the test code to ICCM via LSU to DMA bridge and then executes it from there. Runs on QUASAR with AXI4 buses only.
cmark - coremark benchmark running with code and data in external memories
cmark_dccm - the same as above, running data and stack from DCCM (faster)
cmark_iccm - the same as above with preloaded code to ICCM.
dhry - Run dhrystone. (Scale by 1757 to get DMIPS/MHZ)
```
The `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISCV SW tools are not installed.
#### 6. Logical Equivalence Checking of Quasar
If you want to perform LEC on quasar, use the following command
```
make -f $RV_ROOT/tools/Makefile lec
```
This command will call the LEC Makefile to clone Quasar along with the SweRV-EL2 and run `sbt` for chisel-generated RTL. Then, this will take file for user-match the ports, blockbox pins, latches, flops and perform the LEC of Quasar.
Following log files are created in `$RV_ROOT/verif/LEC/formality_work/formality_log` :
`fm_shell_command.log` gives the detail of instructions
`formality.log` gives the detail of undriven nets
**Note**: The testbench has a simple synthesizable bridge that allows you to load the ICCM via load/store instructions. This is only supported for AXI4 builds.

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RVCExpander.anno.json
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@ -1,73 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rs2",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rd",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rs1",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_legal",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_bits",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_rvc",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~RVCExpander|RVCExpander>io_out_rs3",
"sources":[
"~RVCExpander|RVCExpander>io_in"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"RVCExpander"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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@ -1,404 +0,0 @@
module RVCExpander(
input clock,
input reset,
input [31:0] io_in,
output [31:0] io_out_bits,
output [4:0] io_out_rd,
output [4:0] io_out_rs1,
output [4:0] io_out_rs2,
output [4:0] io_out_rs3,
output io_rvc,
output io_legal
);
wire _T_3 = |io_in[12:5]; // @[RVC.scala 58:29]
wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[RVC.scala 58:20]
wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58]
wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58]
wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
wire [4:0] _T_30 = {2'h1,io_in[9:7]}; // @[Cat.scala 29:58]
wire [27:0] _T_36 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
wire [6:0] _T_50 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 29:58]
wire [26:0] _T_58 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
wire [26:0] _T_80 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
wire [26:0] _T_111 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58]
wire [27:0] _T_138 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58]
wire [26:0] _T_169 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58]
wire [26:0] _T_200 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h27}; // @[Cat.scala 29:58]
wire [6:0] _T_211 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [11:0] _T_213 = {_T_211,io_in[6:2]}; // @[Cat.scala 29:58]
wire [31:0] _T_219 = {_T_211,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire [9:0] _T_228 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
wire [20:0] _T_243 = {_T_228,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_306 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h1,7'h6f}; // @[Cat.scala 29:58]
wire [31:0] _T_321 = {_T_211,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire _T_332 = |_T_213; // @[RVC.scala 95:29]
wire [6:0] _T_333 = _T_332 ? 7'h37 : 7'h3f; // @[RVC.scala 95:20]
wire [14:0] _T_336 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_339 = {_T_336,io_in[6:2],12'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_343 = {_T_339[31:12],io_in[11:7],_T_333}; // @[Cat.scala 29:58]
wire _T_351 = io_in[11:7] == 5'h0; // @[RVC.scala 97:14]
wire _T_353 = io_in[11:7] == 5'h2; // @[RVC.scala 97:27]
wire _T_354 = _T_351 | _T_353; // @[RVC.scala 97:21]
wire [6:0] _T_361 = _T_332 ? 7'h13 : 7'h1f; // @[RVC.scala 91:20]
wire [2:0] _T_364 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_379 = {_T_364,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_361}; // @[Cat.scala 29:58]
wire [31:0] _T_386_bits = _T_354 ? _T_379 : _T_343; // @[RVC.scala 97:10]
wire [4:0] _T_386_rd = _T_354 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 97:10]
wire [4:0] _T_386_rs2 = _T_354 ? _T_14 : _T_14; // @[RVC.scala 97:10]
wire [4:0] _T_386_rs3 = _T_354 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 97:10]
wire [25:0] _T_397 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
wire [30:0] _GEN_172 = {{5'd0}, _T_397}; // @[RVC.scala 104:23]
wire [30:0] _T_409 = _GEN_172 | 31'h40000000; // @[RVC.scala 104:23]
wire [31:0] _T_422 = {_T_211,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
wire [2:0] _T_426 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58]
wire _T_428 = io_in[6:5] == 2'h0; // @[RVC.scala 108:30]
wire [30:0] _T_429 = _T_428 ? 31'h40000000 : 31'h0; // @[RVC.scala 108:22]
wire [6:0] _T_431 = io_in[12] ? 7'h3b : 7'h33; // @[RVC.scala 109:22]
wire [2:0] _GEN_1 = 3'h1 == _T_426 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
wire [2:0] _GEN_2 = 3'h2 == _T_426 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
wire [2:0] _GEN_3 = 3'h3 == _T_426 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
wire [2:0] _GEN_4 = 3'h4 == _T_426 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
wire [2:0] _GEN_5 = 3'h5 == _T_426 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
wire [2:0] _GEN_6 = 3'h6 == _T_426 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
wire [2:0] _GEN_7 = 3'h7 == _T_426 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
wire [24:0] _T_441 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_431}; // @[Cat.scala 29:58]
wire [30:0] _GEN_173 = {{6'd0}, _T_441}; // @[RVC.scala 110:43]
wire [30:0] _T_442 = _GEN_173 | _T_429; // @[RVC.scala 110:43]
wire [31:0] _T_443_0 = {{6'd0}, _T_397}; // @[RVC.scala 112:19 RVC.scala 112:19]
wire [31:0] _T_443_1 = {{1'd0}, _T_409}; // @[RVC.scala 112:19 RVC.scala 112:19]
wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_443_1 : _T_443_0; // @[RVC.scala 27:14]
wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_422 : _GEN_9; // @[RVC.scala 27:14]
wire [31:0] _T_443_3 = {{1'd0}, _T_442}; // @[RVC.scala 112:19 RVC.scala 112:19]
wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_443_3 : _GEN_10; // @[RVC.scala 27:14]
wire [31:0] _T_533 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
wire [4:0] _T_542 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
wire [12:0] _T_551 = {_T_542,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_600 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
wire [31:0] _T_667 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
wire _T_673 = |io_in[11:7]; // @[RVC.scala 118:27]
wire [6:0] _T_674 = _T_673 ? 7'h3 : 7'h1f; // @[RVC.scala 118:23]
wire [25:0] _T_683 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
wire [28:0] _T_699 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
wire [27:0] _T_714 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_674}; // @[Cat.scala 29:58]
wire [27:0] _T_729 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
wire [24:0] _T_739 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
wire [24:0] _T_750 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
wire [24:0] _T_761 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
wire [24:0] _T_763 = {_T_761[24:7],7'h1f}; // @[Cat.scala 29:58]
wire [24:0] _T_766 = _T_673 ? _T_761 : _T_763; // @[RVC.scala 139:33]
wire _T_772 = |io_in[6:2]; // @[RVC.scala 140:27]
wire [31:0] _T_743_bits = {{7'd0}, _T_739}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _T_770_bits = {{7'd0}, _T_766}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _T_773_bits = _T_772 ? _T_743_bits : _T_770_bits; // @[RVC.scala 140:22]
wire [4:0] _T_773_rd = _T_772 ? io_in[11:7] : 5'h0; // @[RVC.scala 140:22]
wire [4:0] _T_773_rs1 = _T_772 ? 5'h0 : io_in[11:7]; // @[RVC.scala 140:22]
wire [4:0] _T_773_rs2 = _T_772 ? io_in[6:2] : io_in[6:2]; // @[RVC.scala 140:22]
wire [4:0] _T_773_rs3 = _T_772 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 140:22]
wire [24:0] _T_779 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
wire [24:0] _T_781 = {_T_761[24:7],7'h73}; // @[Cat.scala 29:58]
wire [24:0] _T_782 = _T_781 | 25'h100000; // @[RVC.scala 142:46]
wire [24:0] _T_785 = _T_673 ? _T_779 : _T_782; // @[RVC.scala 143:33]
wire [31:0] _T_755_bits = {{7'd0}, _T_750}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _T_789_bits = {{7'd0}, _T_785}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _T_792_bits = _T_772 ? _T_755_bits : _T_789_bits; // @[RVC.scala 144:25]
wire [4:0] _T_792_rd = _T_772 ? io_in[11:7] : 5'h1; // @[RVC.scala 144:25]
wire [4:0] _T_792_rs1 = _T_772 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 144:25]
wire [31:0] _T_794_bits = io_in[12] ? _T_792_bits : _T_773_bits; // @[RVC.scala 145:10]
wire [4:0] _T_794_rd = io_in[12] ? _T_792_rd : _T_773_rd; // @[RVC.scala 145:10]
wire [4:0] _T_794_rs1 = io_in[12] ? _T_792_rs1 : _T_773_rs1; // @[RVC.scala 145:10]
wire [4:0] _T_794_rs2 = io_in[12] ? _T_773_rs2 : _T_773_rs2; // @[RVC.scala 145:10]
wire [4:0] _T_794_rs3 = io_in[12] ? _T_773_rs3 : _T_773_rs3; // @[RVC.scala 145:10]
wire [8:0] _T_798 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
wire [28:0] _T_810 = {_T_798[8:5],io_in[6:2],5'h2,3'h3,_T_798[4:0],7'h27}; // @[Cat.scala 29:58]
wire [7:0] _T_818 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58]
wire [27:0] _T_830 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h23}; // @[Cat.scala 29:58]
wire [27:0] _T_850 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h27}; // @[Cat.scala 29:58]
wire [4:0] _T_898 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58]
wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_17 = 5'h1 == _T_898 ? _T_44_bits : _T_24_bits; // @[RVC.scala 203:12]
wire [4:0] _GEN_18 = 5'h1 == _T_898 ? _T_14 : _T_14; // @[RVC.scala 203:12]
wire [4:0] _GEN_19 = 5'h1 == _T_898 ? _T_30 : 5'h2; // @[RVC.scala 203:12]
wire [4:0] _GEN_21 = 5'h1 == _T_898 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 203:12]
wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_22 = 5'h2 == _T_898 ? _T_66_bits : _GEN_17; // @[RVC.scala 203:12]
wire [4:0] _GEN_23 = 5'h2 == _T_898 ? _T_14 : _GEN_18; // @[RVC.scala 203:12]
wire [4:0] _GEN_24 = 5'h2 == _T_898 ? _T_30 : _GEN_19; // @[RVC.scala 203:12]
wire [4:0] _GEN_26 = 5'h2 == _T_898 ? io_in[31:27] : _GEN_21; // @[RVC.scala 203:12]
wire [31:0] _T_88_bits = {{5'd0}, _T_80}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_27 = 5'h3 == _T_898 ? _T_88_bits : _GEN_22; // @[RVC.scala 203:12]
wire [4:0] _GEN_28 = 5'h3 == _T_898 ? _T_14 : _GEN_23; // @[RVC.scala 203:12]
wire [4:0] _GEN_29 = 5'h3 == _T_898 ? _T_30 : _GEN_24; // @[RVC.scala 203:12]
wire [4:0] _GEN_31 = 5'h3 == _T_898 ? io_in[31:27] : _GEN_26; // @[RVC.scala 203:12]
wire [31:0] _T_119_bits = {{5'd0}, _T_111}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_32 = 5'h4 == _T_898 ? _T_119_bits : _GEN_27; // @[RVC.scala 203:12]
wire [4:0] _GEN_33 = 5'h4 == _T_898 ? _T_14 : _GEN_28; // @[RVC.scala 203:12]
wire [4:0] _GEN_34 = 5'h4 == _T_898 ? _T_30 : _GEN_29; // @[RVC.scala 203:12]
wire [4:0] _GEN_36 = 5'h4 == _T_898 ? io_in[31:27] : _GEN_31; // @[RVC.scala 203:12]
wire [31:0] _T_146_bits = {{4'd0}, _T_138}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_37 = 5'h5 == _T_898 ? _T_146_bits : _GEN_32; // @[RVC.scala 203:12]
wire [4:0] _GEN_38 = 5'h5 == _T_898 ? _T_14 : _GEN_33; // @[RVC.scala 203:12]
wire [4:0] _GEN_39 = 5'h5 == _T_898 ? _T_30 : _GEN_34; // @[RVC.scala 203:12]
wire [4:0] _GEN_41 = 5'h5 == _T_898 ? io_in[31:27] : _GEN_36; // @[RVC.scala 203:12]
wire [31:0] _T_177_bits = {{5'd0}, _T_169}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_42 = 5'h6 == _T_898 ? _T_177_bits : _GEN_37; // @[RVC.scala 203:12]
wire [4:0] _GEN_43 = 5'h6 == _T_898 ? _T_14 : _GEN_38; // @[RVC.scala 203:12]
wire [4:0] _GEN_44 = 5'h6 == _T_898 ? _T_30 : _GEN_39; // @[RVC.scala 203:12]
wire [4:0] _GEN_46 = 5'h6 == _T_898 ? io_in[31:27] : _GEN_41; // @[RVC.scala 203:12]
wire [31:0] _T_208_bits = {{5'd0}, _T_200}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_47 = 5'h7 == _T_898 ? _T_208_bits : _GEN_42; // @[RVC.scala 203:12]
wire [4:0] _GEN_48 = 5'h7 == _T_898 ? _T_14 : _GEN_43; // @[RVC.scala 203:12]
wire [4:0] _GEN_49 = 5'h7 == _T_898 ? _T_30 : _GEN_44; // @[RVC.scala 203:12]
wire [4:0] _GEN_51 = 5'h7 == _T_898 ? io_in[31:27] : _GEN_46; // @[RVC.scala 203:12]
wire [31:0] _GEN_52 = 5'h8 == _T_898 ? _T_219 : _GEN_47; // @[RVC.scala 203:12]
wire [4:0] _GEN_53 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_48; // @[RVC.scala 203:12]
wire [4:0] _GEN_54 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_49; // @[RVC.scala 203:12]
wire [4:0] _GEN_55 = 5'h8 == _T_898 ? _T_14 : _GEN_48; // @[RVC.scala 203:12]
wire [4:0] _GEN_56 = 5'h8 == _T_898 ? io_in[31:27] : _GEN_51; // @[RVC.scala 203:12]
wire [31:0] _GEN_57 = 5'h9 == _T_898 ? _T_306 : _GEN_52; // @[RVC.scala 203:12]
wire [4:0] _GEN_58 = 5'h9 == _T_898 ? 5'h1 : _GEN_53; // @[RVC.scala 203:12]
wire [4:0] _GEN_59 = 5'h9 == _T_898 ? io_in[11:7] : _GEN_54; // @[RVC.scala 203:12]
wire [4:0] _GEN_60 = 5'h9 == _T_898 ? _T_14 : _GEN_55; // @[RVC.scala 203:12]
wire [4:0] _GEN_61 = 5'h9 == _T_898 ? io_in[31:27] : _GEN_56; // @[RVC.scala 203:12]
wire [31:0] _GEN_62 = 5'ha == _T_898 ? _T_321 : _GEN_57; // @[RVC.scala 203:12]
wire [4:0] _GEN_63 = 5'ha == _T_898 ? io_in[11:7] : _GEN_58; // @[RVC.scala 203:12]
wire [4:0] _GEN_64 = 5'ha == _T_898 ? 5'h0 : _GEN_59; // @[RVC.scala 203:12]
wire [4:0] _GEN_65 = 5'ha == _T_898 ? _T_14 : _GEN_60; // @[RVC.scala 203:12]
wire [4:0] _GEN_66 = 5'ha == _T_898 ? io_in[31:27] : _GEN_61; // @[RVC.scala 203:12]
wire [31:0] _GEN_67 = 5'hb == _T_898 ? _T_386_bits : _GEN_62; // @[RVC.scala 203:12]
wire [4:0] _GEN_68 = 5'hb == _T_898 ? _T_386_rd : _GEN_63; // @[RVC.scala 203:12]
wire [4:0] _GEN_69 = 5'hb == _T_898 ? _T_386_rd : _GEN_64; // @[RVC.scala 203:12]
wire [4:0] _GEN_70 = 5'hb == _T_898 ? _T_386_rs2 : _GEN_65; // @[RVC.scala 203:12]
wire [4:0] _GEN_71 = 5'hb == _T_898 ? _T_386_rs3 : _GEN_66; // @[RVC.scala 203:12]
wire [31:0] _GEN_72 = 5'hc == _T_898 ? _GEN_11 : _GEN_67; // @[RVC.scala 203:12]
wire [4:0] _GEN_73 = 5'hc == _T_898 ? _T_30 : _GEN_68; // @[RVC.scala 203:12]
wire [4:0] _GEN_74 = 5'hc == _T_898 ? _T_30 : _GEN_69; // @[RVC.scala 203:12]
wire [4:0] _GEN_75 = 5'hc == _T_898 ? _T_14 : _GEN_70; // @[RVC.scala 203:12]
wire [4:0] _GEN_76 = 5'hc == _T_898 ? io_in[31:27] : _GEN_71; // @[RVC.scala 203:12]
wire [31:0] _GEN_77 = 5'hd == _T_898 ? _T_533 : _GEN_72; // @[RVC.scala 203:12]
wire [4:0] _GEN_78 = 5'hd == _T_898 ? 5'h0 : _GEN_73; // @[RVC.scala 203:12]
wire [4:0] _GEN_79 = 5'hd == _T_898 ? _T_30 : _GEN_74; // @[RVC.scala 203:12]
wire [4:0] _GEN_80 = 5'hd == _T_898 ? _T_14 : _GEN_75; // @[RVC.scala 203:12]
wire [4:0] _GEN_81 = 5'hd == _T_898 ? io_in[31:27] : _GEN_76; // @[RVC.scala 203:12]
wire [31:0] _GEN_82 = 5'he == _T_898 ? _T_600 : _GEN_77; // @[RVC.scala 203:12]
wire [4:0] _GEN_83 = 5'he == _T_898 ? _T_30 : _GEN_78; // @[RVC.scala 203:12]
wire [4:0] _GEN_84 = 5'he == _T_898 ? _T_30 : _GEN_79; // @[RVC.scala 203:12]
wire [4:0] _GEN_85 = 5'he == _T_898 ? 5'h0 : _GEN_80; // @[RVC.scala 203:12]
wire [4:0] _GEN_86 = 5'he == _T_898 ? io_in[31:27] : _GEN_81; // @[RVC.scala 203:12]
wire [31:0] _GEN_87 = 5'hf == _T_898 ? _T_667 : _GEN_82; // @[RVC.scala 203:12]
wire [4:0] _GEN_88 = 5'hf == _T_898 ? 5'h0 : _GEN_83; // @[RVC.scala 203:12]
wire [4:0] _GEN_89 = 5'hf == _T_898 ? _T_30 : _GEN_84; // @[RVC.scala 203:12]
wire [4:0] _GEN_90 = 5'hf == _T_898 ? 5'h0 : _GEN_85; // @[RVC.scala 203:12]
wire [4:0] _GEN_91 = 5'hf == _T_898 ? io_in[31:27] : _GEN_86; // @[RVC.scala 203:12]
wire [31:0] _T_688_bits = {{6'd0}, _T_683}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_92 = 5'h10 == _T_898 ? _T_688_bits : _GEN_87; // @[RVC.scala 203:12]
wire [4:0] _GEN_93 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_88; // @[RVC.scala 203:12]
wire [4:0] _GEN_94 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_89; // @[RVC.scala 203:12]
wire [4:0] _GEN_95 = 5'h10 == _T_898 ? io_in[6:2] : _GEN_90; // @[RVC.scala 203:12]
wire [4:0] _GEN_96 = 5'h10 == _T_898 ? io_in[31:27] : _GEN_91; // @[RVC.scala 203:12]
wire [31:0] _T_703_bits = {{3'd0}, _T_699}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_97 = 5'h11 == _T_898 ? _T_703_bits : _GEN_92; // @[RVC.scala 203:12]
wire [4:0] _GEN_98 = 5'h11 == _T_898 ? io_in[11:7] : _GEN_93; // @[RVC.scala 203:12]
wire [4:0] _GEN_99 = 5'h11 == _T_898 ? 5'h2 : _GEN_94; // @[RVC.scala 203:12]
wire [4:0] _GEN_100 = 5'h11 == _T_898 ? io_in[6:2] : _GEN_95; // @[RVC.scala 203:12]
wire [4:0] _GEN_101 = 5'h11 == _T_898 ? io_in[31:27] : _GEN_96; // @[RVC.scala 203:12]
wire [31:0] _T_718_bits = {{4'd0}, _T_714}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_102 = 5'h12 == _T_898 ? _T_718_bits : _GEN_97; // @[RVC.scala 203:12]
wire [4:0] _GEN_103 = 5'h12 == _T_898 ? io_in[11:7] : _GEN_98; // @[RVC.scala 203:12]
wire [4:0] _GEN_104 = 5'h12 == _T_898 ? 5'h2 : _GEN_99; // @[RVC.scala 203:12]
wire [4:0] _GEN_105 = 5'h12 == _T_898 ? io_in[6:2] : _GEN_100; // @[RVC.scala 203:12]
wire [4:0] _GEN_106 = 5'h12 == _T_898 ? io_in[31:27] : _GEN_101; // @[RVC.scala 203:12]
wire [31:0] _T_733_bits = {{4'd0}, _T_729}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_107 = 5'h13 == _T_898 ? _T_733_bits : _GEN_102; // @[RVC.scala 203:12]
wire [4:0] _GEN_108 = 5'h13 == _T_898 ? io_in[11:7] : _GEN_103; // @[RVC.scala 203:12]
wire [4:0] _GEN_109 = 5'h13 == _T_898 ? 5'h2 : _GEN_104; // @[RVC.scala 203:12]
wire [4:0] _GEN_110 = 5'h13 == _T_898 ? io_in[6:2] : _GEN_105; // @[RVC.scala 203:12]
wire [4:0] _GEN_111 = 5'h13 == _T_898 ? io_in[31:27] : _GEN_106; // @[RVC.scala 203:12]
wire [31:0] _GEN_112 = 5'h14 == _T_898 ? _T_794_bits : _GEN_107; // @[RVC.scala 203:12]
wire [4:0] _GEN_113 = 5'h14 == _T_898 ? _T_794_rd : _GEN_108; // @[RVC.scala 203:12]
wire [4:0] _GEN_114 = 5'h14 == _T_898 ? _T_794_rs1 : _GEN_109; // @[RVC.scala 203:12]
wire [4:0] _GEN_115 = 5'h14 == _T_898 ? _T_794_rs2 : _GEN_110; // @[RVC.scala 203:12]
wire [4:0] _GEN_116 = 5'h14 == _T_898 ? _T_794_rs3 : _GEN_111; // @[RVC.scala 203:12]
wire [31:0] _T_814_bits = {{3'd0}, _T_810}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_117 = 5'h15 == _T_898 ? _T_814_bits : _GEN_112; // @[RVC.scala 203:12]
wire [4:0] _GEN_118 = 5'h15 == _T_898 ? io_in[11:7] : _GEN_113; // @[RVC.scala 203:12]
wire [4:0] _GEN_119 = 5'h15 == _T_898 ? 5'h2 : _GEN_114; // @[RVC.scala 203:12]
wire [4:0] _GEN_120 = 5'h15 == _T_898 ? io_in[6:2] : _GEN_115; // @[RVC.scala 203:12]
wire [4:0] _GEN_121 = 5'h15 == _T_898 ? io_in[31:27] : _GEN_116; // @[RVC.scala 203:12]
wire [31:0] _T_834_bits = {{4'd0}, _T_830}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_122 = 5'h16 == _T_898 ? _T_834_bits : _GEN_117; // @[RVC.scala 203:12]
wire [4:0] _GEN_123 = 5'h16 == _T_898 ? io_in[11:7] : _GEN_118; // @[RVC.scala 203:12]
wire [4:0] _GEN_124 = 5'h16 == _T_898 ? 5'h2 : _GEN_119; // @[RVC.scala 203:12]
wire [4:0] _GEN_125 = 5'h16 == _T_898 ? io_in[6:2] : _GEN_120; // @[RVC.scala 203:12]
wire [4:0] _GEN_126 = 5'h16 == _T_898 ? io_in[31:27] : _GEN_121; // @[RVC.scala 203:12]
wire [31:0] _T_854_bits = {{4'd0}, _T_850}; // @[RVC.scala 26:19 RVC.scala 27:14]
wire [31:0] _GEN_127 = 5'h17 == _T_898 ? _T_854_bits : _GEN_122; // @[RVC.scala 203:12]
wire [4:0] _GEN_128 = 5'h17 == _T_898 ? io_in[11:7] : _GEN_123; // @[RVC.scala 203:12]
wire [4:0] _GEN_129 = 5'h17 == _T_898 ? 5'h2 : _GEN_124; // @[RVC.scala 203:12]
wire [4:0] _GEN_130 = 5'h17 == _T_898 ? io_in[6:2] : _GEN_125; // @[RVC.scala 203:12]
wire [4:0] _GEN_131 = 5'h17 == _T_898 ? io_in[31:27] : _GEN_126; // @[RVC.scala 203:12]
wire [31:0] _GEN_132 = 5'h18 == _T_898 ? io_in : _GEN_127; // @[RVC.scala 203:12]
wire [4:0] _GEN_133 = 5'h18 == _T_898 ? io_in[11:7] : _GEN_128; // @[RVC.scala 203:12]
wire [4:0] _GEN_134 = 5'h18 == _T_898 ? io_in[19:15] : _GEN_129; // @[RVC.scala 203:12]
wire [4:0] _GEN_135 = 5'h18 == _T_898 ? io_in[24:20] : _GEN_130; // @[RVC.scala 203:12]
wire [4:0] _GEN_136 = 5'h18 == _T_898 ? io_in[31:27] : _GEN_131; // @[RVC.scala 203:12]
wire [31:0] _GEN_137 = 5'h19 == _T_898 ? io_in : _GEN_132; // @[RVC.scala 203:12]
wire [4:0] _GEN_138 = 5'h19 == _T_898 ? io_in[11:7] : _GEN_133; // @[RVC.scala 203:12]
wire [4:0] _GEN_139 = 5'h19 == _T_898 ? io_in[19:15] : _GEN_134; // @[RVC.scala 203:12]
wire [4:0] _GEN_140 = 5'h19 == _T_898 ? io_in[24:20] : _GEN_135; // @[RVC.scala 203:12]
wire [4:0] _GEN_141 = 5'h19 == _T_898 ? io_in[31:27] : _GEN_136; // @[RVC.scala 203:12]
wire [31:0] _GEN_142 = 5'h1a == _T_898 ? io_in : _GEN_137; // @[RVC.scala 203:12]
wire [4:0] _GEN_143 = 5'h1a == _T_898 ? io_in[11:7] : _GEN_138; // @[RVC.scala 203:12]
wire [4:0] _GEN_144 = 5'h1a == _T_898 ? io_in[19:15] : _GEN_139; // @[RVC.scala 203:12]
wire [4:0] _GEN_145 = 5'h1a == _T_898 ? io_in[24:20] : _GEN_140; // @[RVC.scala 203:12]
wire [4:0] _GEN_146 = 5'h1a == _T_898 ? io_in[31:27] : _GEN_141; // @[RVC.scala 203:12]
wire [31:0] _GEN_147 = 5'h1b == _T_898 ? io_in : _GEN_142; // @[RVC.scala 203:12]
wire [4:0] _GEN_148 = 5'h1b == _T_898 ? io_in[11:7] : _GEN_143; // @[RVC.scala 203:12]
wire [4:0] _GEN_149 = 5'h1b == _T_898 ? io_in[19:15] : _GEN_144; // @[RVC.scala 203:12]
wire [4:0] _GEN_150 = 5'h1b == _T_898 ? io_in[24:20] : _GEN_145; // @[RVC.scala 203:12]
wire [4:0] _GEN_151 = 5'h1b == _T_898 ? io_in[31:27] : _GEN_146; // @[RVC.scala 203:12]
wire [31:0] _GEN_152 = 5'h1c == _T_898 ? io_in : _GEN_147; // @[RVC.scala 203:12]
wire [4:0] _GEN_153 = 5'h1c == _T_898 ? io_in[11:7] : _GEN_148; // @[RVC.scala 203:12]
wire [4:0] _GEN_154 = 5'h1c == _T_898 ? io_in[19:15] : _GEN_149; // @[RVC.scala 203:12]
wire [4:0] _GEN_155 = 5'h1c == _T_898 ? io_in[24:20] : _GEN_150; // @[RVC.scala 203:12]
wire [4:0] _GEN_156 = 5'h1c == _T_898 ? io_in[31:27] : _GEN_151; // @[RVC.scala 203:12]
wire [31:0] _GEN_157 = 5'h1d == _T_898 ? io_in : _GEN_152; // @[RVC.scala 203:12]
wire [4:0] _GEN_158 = 5'h1d == _T_898 ? io_in[11:7] : _GEN_153; // @[RVC.scala 203:12]
wire [4:0] _GEN_159 = 5'h1d == _T_898 ? io_in[19:15] : _GEN_154; // @[RVC.scala 203:12]
wire [4:0] _GEN_160 = 5'h1d == _T_898 ? io_in[24:20] : _GEN_155; // @[RVC.scala 203:12]
wire [4:0] _GEN_161 = 5'h1d == _T_898 ? io_in[31:27] : _GEN_156; // @[RVC.scala 203:12]
wire [31:0] _GEN_162 = 5'h1e == _T_898 ? io_in : _GEN_157; // @[RVC.scala 203:12]
wire [4:0] _GEN_163 = 5'h1e == _T_898 ? io_in[11:7] : _GEN_158; // @[RVC.scala 203:12]
wire [4:0] _GEN_164 = 5'h1e == _T_898 ? io_in[19:15] : _GEN_159; // @[RVC.scala 203:12]
wire [4:0] _GEN_165 = 5'h1e == _T_898 ? io_in[24:20] : _GEN_160; // @[RVC.scala 203:12]
wire [4:0] _GEN_166 = 5'h1e == _T_898 ? io_in[31:27] : _GEN_161; // @[RVC.scala 203:12]
wire _T_900 = ~io_in[13]; // @[RVC.scala 204:18]
wire _T_902 = ~io_in[12]; // @[RVC.scala 204:31]
wire _T_903 = _T_900 & _T_902; // @[RVC.scala 204:29]
wire _T_905 = _T_903 & io_in[11]; // @[RVC.scala 204:42]
wire _T_907 = _T_905 & io_in[1]; // @[RVC.scala 204:54]
wire _T_909 = ~io_in[0]; // @[RVC.scala 204:65]
wire _T_910 = _T_907 & _T_909; // @[RVC.scala 204:63]
wire _T_917 = _T_903 & io_in[6]; // @[RVC.scala 205:32]
wire _T_919 = _T_917 & io_in[1]; // @[RVC.scala 205:43]
wire _T_922 = _T_919 & _T_909; // @[RVC.scala 205:52]
wire _T_923 = _T_910 | _T_922; // @[RVC.scala 204:76]
wire _T_925 = ~io_in[15]; // @[RVC.scala 206:8]
wire _T_928 = _T_925 & _T_900; // @[RVC.scala 206:19]
wire _T_931 = ~io_in[1]; // @[RVC.scala 206:43]
wire _T_932 = io_in[11] >> _T_931; // @[RVC.scala 206:42]
wire _T_934 = _T_928 & _T_932; // @[RVC.scala 206:32]
wire _T_935 = _T_923 | _T_934; // @[RVC.scala 205:65]
wire _T_942 = _T_903 & io_in[5]; // @[RVC.scala 207:32]
wire _T_944 = _T_942 & io_in[1]; // @[RVC.scala 207:41]
wire _T_947 = _T_944 & _T_909; // @[RVC.scala 207:50]
wire _T_948 = _T_935 | _T_947; // @[RVC.scala 206:54]
wire _T_955 = _T_903 & io_in[10]; // @[RVC.scala 208:32]
wire _T_958 = _T_955 & _T_931; // @[RVC.scala 208:42]
wire _T_960 = _T_958 & io_in[0]; // @[RVC.scala 208:54]
wire _T_961 = _T_948 | _T_960; // @[RVC.scala 207:63]
wire _T_968 = _T_928 & io_in[6]; // @[RVC.scala 209:32]
wire _T_971 = _T_968 & _T_931; // @[RVC.scala 209:41]
wire _T_972 = _T_961 | _T_971; // @[RVC.scala 208:64]
wire _T_976 = io_in[15] & _T_902; // @[RVC.scala 209:65]
wire _T_979 = _T_976 & _T_931; // @[RVC.scala 209:78]
wire _T_981 = _T_979 & io_in[0]; // @[RVC.scala 209:90]
wire _T_982 = _T_972 | _T_981; // @[RVC.scala 209:54]
wire _T_989 = _T_903 & io_in[9]; // @[RVC.scala 210:32]
wire _T_991 = _T_989 & io_in[1]; // @[RVC.scala 210:41]
wire _T_994 = _T_991 & _T_909; // @[RVC.scala 210:50]
wire _T_995 = _T_982 | _T_994; // @[RVC.scala 209:100]
wire _T_999 = _T_902 & io_in[6]; // @[RVC.scala 211:19]
wire _T_1002 = _T_999 & _T_931; // @[RVC.scala 211:28]
wire _T_1004 = _T_1002 & io_in[0]; // @[RVC.scala 211:40]
wire _T_1005 = _T_995 | _T_1004; // @[RVC.scala 210:63]
wire _T_1012 = _T_928 & io_in[5]; // @[RVC.scala 212:32]
wire _T_1015 = _T_1012 & _T_931; // @[RVC.scala 212:41]
wire _T_1016 = _T_1005 | _T_1015; // @[RVC.scala 211:50]
wire _T_1023 = _T_903 & io_in[8]; // @[RVC.scala 213:32]
wire _T_1025 = _T_1023 & io_in[1]; // @[RVC.scala 213:41]
wire _T_1028 = _T_1025 & _T_909; // @[RVC.scala 213:50]
wire _T_1029 = _T_1016 | _T_1028; // @[RVC.scala 212:54]
wire _T_1033 = _T_902 & io_in[5]; // @[RVC.scala 214:19]
wire _T_1036 = _T_1033 & _T_931; // @[RVC.scala 214:28]
wire _T_1038 = _T_1036 & io_in[0]; // @[RVC.scala 214:40]
wire _T_1039 = _T_1029 | _T_1038; // @[RVC.scala 213:63]
wire _T_1046 = _T_928 & io_in[10]; // @[RVC.scala 215:32]
wire _T_1049 = _T_1046 & _T_931; // @[RVC.scala 215:42]
wire _T_1050 = _T_1039 | _T_1049; // @[RVC.scala 214:50]
wire _T_1057 = _T_903 & io_in[7]; // @[RVC.scala 215:82]
wire _T_1059 = _T_1057 & io_in[1]; // @[RVC.scala 215:91]
wire _T_1062 = _T_1059 & _T_909; // @[RVC.scala 215:100]
wire _T_1063 = _T_1050 | _T_1062; // @[RVC.scala 215:55]
wire _T_1066 = io_in[12] & io_in[11]; // @[RVC.scala 216:16]
wire _T_1068 = ~io_in[10]; // @[RVC.scala 216:28]
wire _T_1069 = _T_1066 & _T_1068; // @[RVC.scala 216:26]
wire _T_1072 = _T_1069 & _T_931; // @[RVC.scala 216:39]
wire _T_1074 = _T_1072 & io_in[0]; // @[RVC.scala 216:51]
wire _T_1075 = _T_1063 | _T_1074; // @[RVC.scala 215:113]
wire _T_1082 = _T_928 & io_in[9]; // @[RVC.scala 216:88]
wire _T_1085 = _T_1082 & _T_931; // @[RVC.scala 216:97]
wire _T_1086 = _T_1075 | _T_1085; // @[RVC.scala 216:61]
wire _T_1093 = _T_903 & io_in[4]; // @[RVC.scala 217:32]
wire _T_1095 = _T_1093 & io_in[1]; // @[RVC.scala 217:41]
wire _T_1098 = _T_1095 & _T_909; // @[RVC.scala 217:50]
wire _T_1099 = _T_1086 | _T_1098; // @[RVC.scala 216:110]
wire _T_1102 = io_in[13] & io_in[12]; // @[RVC.scala 217:74]
wire _T_1105 = _T_1102 & _T_931; // @[RVC.scala 217:84]
wire _T_1107 = _T_1105 & io_in[0]; // @[RVC.scala 217:96]
wire _T_1108 = _T_1099 | _T_1107; // @[RVC.scala 217:63]
wire _T_1115 = _T_928 & io_in[8]; // @[RVC.scala 218:32]
wire _T_1118 = _T_1115 & _T_931; // @[RVC.scala 218:41]
wire _T_1119 = _T_1108 | _T_1118; // @[RVC.scala 217:106]
wire _T_1126 = _T_903 & io_in[3]; // @[RVC.scala 218:81]
wire _T_1128 = _T_1126 & io_in[1]; // @[RVC.scala 218:90]
wire _T_1131 = _T_1128 & _T_909; // @[RVC.scala 218:99]
wire _T_1132 = _T_1119 | _T_1131; // @[RVC.scala 218:54]
wire _T_1135 = io_in[13] & io_in[4]; // @[RVC.scala 219:16]
wire _T_1138 = _T_1135 & _T_931; // @[RVC.scala 219:25]
wire _T_1140 = _T_1138 & io_in[0]; // @[RVC.scala 219:37]
wire _T_1141 = _T_1132 | _T_1140; // @[RVC.scala 218:112]
wire _T_1148 = _T_903 & io_in[2]; // @[RVC.scala 219:74]
wire _T_1150 = _T_1148 & io_in[1]; // @[RVC.scala 219:83]
wire _T_1153 = _T_1150 & _T_909; // @[RVC.scala 219:92]
wire _T_1154 = _T_1141 | _T_1153; // @[RVC.scala 219:47]
wire _T_1161 = _T_928 & io_in[7]; // @[RVC.scala 220:32]
wire _T_1164 = _T_1161 & _T_931; // @[RVC.scala 220:41]
wire _T_1165 = _T_1154 | _T_1164; // @[RVC.scala 219:105]
wire _T_1168 = io_in[13] & io_in[3]; // @[RVC.scala 220:65]
wire _T_1171 = _T_1168 & _T_931; // @[RVC.scala 220:74]
wire _T_1173 = _T_1171 & io_in[0]; // @[RVC.scala 220:86]
wire _T_1174 = _T_1165 | _T_1173; // @[RVC.scala 220:54]
wire _T_1177 = io_in[13] & io_in[2]; // @[RVC.scala 221:16]
wire _T_1180 = _T_1177 & _T_931; // @[RVC.scala 221:25]
wire _T_1182 = _T_1180 & io_in[0]; // @[RVC.scala 221:37]
wire _T_1183 = _T_1174 | _T_1182; // @[RVC.scala 220:96]
wire _T_1187 = io_in[14] & _T_900; // @[RVC.scala 221:58]
wire _T_1190 = _T_1187 & _T_931; // @[RVC.scala 221:71]
wire _T_1191 = _T_1183 | _T_1190; // @[RVC.scala 221:47]
wire _T_1193 = ~io_in[14]; // @[RVC.scala 222:8]
wire _T_1196 = _T_1193 & _T_902; // @[RVC.scala 222:19]
wire _T_1199 = _T_1196 & _T_931; // @[RVC.scala 222:32]
wire _T_1201 = _T_1199 & io_in[0]; // @[RVC.scala 222:44]
wire _T_1202 = _T_1191 | _T_1201; // @[RVC.scala 221:84]
wire _T_1206 = io_in[15] & _T_900; // @[RVC.scala 222:65]
wire _T_1208 = _T_1206 & io_in[12]; // @[RVC.scala 222:78]
wire _T_1210 = _T_1208 & io_in[1]; // @[RVC.scala 222:88]
wire _T_1213 = _T_1210 & _T_909; // @[RVC.scala 222:97]
wire _T_1214 = _T_1202 | _T_1213; // @[RVC.scala 222:54]
wire _T_1222 = _T_928 & _T_902; // @[RVC.scala 223:32]
wire _T_1224 = _T_1222 & io_in[1]; // @[RVC.scala 223:45]
wire _T_1227 = _T_1224 & _T_909; // @[RVC.scala 223:54]
wire _T_1228 = _T_1214 | _T_1227; // @[RVC.scala 222:110]
wire _T_1235 = _T_928 & io_in[12]; // @[RVC.scala 223:94]
wire _T_1238 = _T_1235 & _T_931; // @[RVC.scala 223:104]
wire _T_1239 = _T_1228 | _T_1238; // @[RVC.scala 223:67]
wire _T_1246 = _T_1187 & _T_909; // @[RVC.scala 224:29]
assign io_out_bits = 5'h1f == _T_898 ? io_in : _GEN_162; // @[RVC.scala 203:12]
assign io_out_rd = 5'h1f == _T_898 ? io_in[11:7] : _GEN_163; // @[RVC.scala 203:12]
assign io_out_rs1 = 5'h1f == _T_898 ? io_in[19:15] : _GEN_164; // @[RVC.scala 203:12]
assign io_out_rs2 = 5'h1f == _T_898 ? io_in[24:20] : _GEN_165; // @[RVC.scala 203:12]
assign io_out_rs3 = 5'h1f == _T_898 ? io_in[31:27] : _GEN_166; // @[RVC.scala 203:12]
assign io_rvc = io_in[1:0] != 2'h3; // @[RVC.scala 201:12]
assign io_legal = _T_1239 | _T_1246; // @[RVC.scala 204:14]
endmodule

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// See README.md for license details.
def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
Seq() ++ {
// If we're building with Scala > 2.11, enable the compile option
// switch to support our anonymous Bundle definitions:
// https://github.com/scala/bug/issues/10047
CrossVersion.partialVersion(scalaVersion) match {
case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq()
case _ => Seq("-Xsource:2.11")
}
}
}
def javacOptionsVersion(scalaVersion: String): Seq[String] = {
Seq() ++ {
// Scala 2.12 requires Java 8. We continue to generate
// Java 7 compatible code for Scala 2.11
// for compatibility with old clients.
CrossVersion.partialVersion(scalaVersion) match {
case Some((2, scalaMajor: Long)) if scalaMajor < 12 =>
Seq("-source", "1.7", "-target", "1.7")
case _ =>
Seq("-source", "1.8", "-target", "1.8")
}
}
}
name := "chisel-module-template"
version := "3.3.0"
scalaVersion := "2.12.10"
crossScalaVersions := Seq("2.12.10", "2.11.12")
resolvers ++= Seq(
Resolver.sonatypeRepo("snapshots"),
Resolver.sonatypeRepo("releases")
)
addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)
// Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
val defaultVersions = Seq(
"chisel-iotesters" -> "1.4.1+",
"chiseltest" -> "0.2.1+"
)
libraryDependencies ++= defaultVersions.map { case (dep, ver) =>
"edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", ver) }
scalacOptions ++= scalacOptionsVersion(scalaVersion.value)
javacOptions ++= javacOptionsVersion(scalaVersion.value)

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caller.anno.json
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~caller|caller>io_out",
"sources":[
"~caller|caller>io_in"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"caller"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

20
caller.fir
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit caller :
module rvdff :
input clock : Clock
input reset : Reset
output io : {flip in : UInt<32>, out : UInt}
io.out <= io.in @[GCD.scala 12:10]
module caller :
input clock : Clock
input reset : UInt<1>
output io : {flip in : UInt<32>, out : UInt}
inst u0 of rvdff @[GCD.scala 21:18]
u0.clock <= clock
u0.reset <= reset
io.out <= u0.io.out @[GCD.scala 22:6]
u0.io.in <= io.in @[GCD.scala 22:6]

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caller.v
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module rvdff(
input [31:0] io_in,
output [31:0] io_out
);
assign io_out = io_in; // @[GCD.scala 12:10]
endmodule
module caller(
input clock,
input reset,
input [31:0] io_in,
output [31:0] io_out
);
wire [31:0] u0_io_in; // @[GCD.scala 21:18]
wire [31:0] u0_io_out; // @[GCD.scala 21:18]
rvdff u0 ( // @[GCD.scala 21:18]
.io_in(u0_io_in),
.io_out(u0_io_out)
);
assign io_out = u0_io_out; // @[GCD.scala 22:6]
assign u0_io_in = io_in; // @[GCD.scala 22:6]
endmodule

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# Quasar RISC-V Core from Lampro Mellon
## Configuration
### Contents
Name | Description
---------------------- | ------------------------------
quasar.config | Configuration script for core
quasar_config_gen.py | Python wrapper to run quasar.config
This script will generate a consistent set of `defines/#defines/parameters` needed for the design and testbench.
A perl hash (*perl_configs.pl*) and a JSON format for SweRV-iss are also generated.
This set of include files :
```
./snapshots/<target>
├── common_defines.vh # `defines for testbench
├── defines.h # #defines for C/assembly headers
├── param.vh # Actual Design parameters
├── pdef.vh # Parameter structure definition
├── pd_defines.vh # `defines for physical design
├── perl_configs.pl # Perl %configs hash for scripting
├── pic_map_auto.h # PIC memory map based on configure size
├── whisper.json # JSON file for swerv-iss
└── link.ld # Default linker file for tests
```
While the defines may be modified by hand, it is recommended that this script be used to generate a consistent set.
### Targets
There are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via the `-target=name` option to quasar.config.
Target | Description
---------------------- | ------------------------------
default | Default configuration. AXI4 bus interface.
default_ahb | Default configuration, AHB-Lite bus interface
typical_pd | No ICCM, AXI4 bus interface
high_perf | Large BTB/BHT, AXI4 interface
`quasar.config` may be edited to add additional target configurations, or new configurations may be created via the command line `-set` or `-unset` options.
**Run `$RV_ROOT/configs/quasar.config -h` for options and settable parameters.**

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#!/usr/bin/env python
from fusesoc.capi2.generator import Generator
import os
import shutil
import subprocess
import sys
import tempfile
if sys.version[0] == '2':
devnull = open(os.devnull, 'w')
else:
from subprocess import DEVNULL as devnull
class SwervConfigGenerator(Generator):
def run(self):
script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..'))
files = [
{"configs/snapshots/default/common_defines.vh" : {
"copyto" : "config/common_defines.vh",
"file_type" : "systemVerilogSource"}},
{"configs/snapshots/default/pdef.vh" : {
"copyto" : "config/pdef.vh",
"file_type" : "systemVerilogSource"}},
{"configs/snapshots/default/param.vh" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}},
{"configs/snapshots/default/pic_map_auto.h" : {
"is_include_file" : True,
"file_type" : "systemVerilogSource"}}]
tmp_dir = os.path.join(tempfile.mkdtemp(), 'core')
shutil.copytree(script_root, tmp_dir)
cwd = tmp_dir
env = os.environ.copy()
env['RV_ROOT'] = tmp_dir
args = ['configs/quasar.config'] + self.config.get('args', [])
rc = subprocess.call(args, cwd=cwd, env=env, stdout=devnull)
if rc:
exit(1)
filenames = []
for f in files:
for k in f:
filenames.append(k)
for f in filenames:
d = os.path.dirname(f)
if d and not os.path.exists(d):
os.makedirs(d)
shutil.copy2(os.path.join(cwd, f),f)
self.add_files(files)
g = SwervConfigGenerator()
g.run()
g.write()

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build/
obj_dir/
gen/

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export RV_ROOT = ${PWD}/..
GCC_PREFIX = /opt/riscv/bin/riscv32-unknown-elf
GDB_PREFIX = /opt/riscv/bin/riscv32-unknown-elf-gdb
ABI = -mabi=ilp32 -march=rv32imc
DEMODIR = ${PWD}
BUILD_DIR = ${DEMODIR}/build
DEFINE_DIR = ${DEMODIR}/../design/snapshots/default
RV_SOC = ${RV_ROOT}/soc
TEST = jtag
ifdef debug
DEBUG_PLUS = +dumpon
VERILATOR_DEBUG = --trace
endif
LINK = $(DEMODIR)/link.ld
LINKPRO = $(DEMODIR)/link_pro.ld
# CFLAGS for verilator generated Makefiles. Without -std=c++11 it complains for `auto` variables
CFLAGS += "-std=c++11"
# Optimization for better performance; alternative is nothing for slower runtime (faster compiles)
# -O2 for faster runtime (slower compiles), or -O for balance.
VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
# Targets
all: clean verilator
clean:
rm -rf build obj_dir
##################### Verilog Builds #####################################
verilator-build:
echo '`undef RV_ASSERT_ON' >> ${DEFINE_DIR}/common_defines.vh
verilator --cc -CFLAGS ${CFLAGS} \
$(DEFINE_DIR)/common_defines.vh \
-I${DEFINE_DIR} \
-Wno-WIDTH \
-Wno-UNOPTFLAT \
-Wno-LATCH \
-F ${RV_SOC}/soc_top.mk \
-F ${RV_SOC}/soc_sim.mk \
$(RV_SOC)/soc_sim.sv \
--top-module soc_sim -exe test_soc_sim.cpp --autoflush $(VERILATOR_DEBUG)
cp ${DEMODIR}/test_soc_sim.cpp obj_dir
$(MAKE) -j -e -C obj_dir/ -f Vsoc_sim.mk $(VERILATOR_MAKE_FLAGS)
##################### Simulation Runs #####################################
verilator: program.hex verilator-build
cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
sim:
cd build && ../obj_dir/Vsoc_sim ${DEBUG_PLUS}
##################### Test hex Build #####################################
program.hex: $(TEST).o $(LINK)
@echo Building $(TEST)
$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINKPRO) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
$(GCC_PREFIX)-objcopy -O verilog $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/program.hex
$(GCC_PREFIX)-gcc $(ABI) -Wl,-Map=$(BUILD_DIR)/$(TEST).map -lgcc -T$(LINK) -o $(BUILD_DIR)/$(TEST).bin $(BUILD_DIR)/$(TEST).o -nostartfiles $(TEST_LIBS)
$(GCC_PREFIX)-objdump -S $(BUILD_DIR)/$(TEST).bin > $(BUILD_DIR)/$(TEST).dis
@echo Completed building $(TEST)
%.o : %.s
@mkdir -p $(BUILD_DIR)
$(GCC_PREFIX)-cpp -g -I${DEFINE_DIR} $< > $(BUILD_DIR)/$*.cpp.s
$(GCC_PREFIX)-as -g $(ABI) $(BUILD_DIR)/$*.cpp.s -o $(BUILD_DIR)/$@
##################### openocd #####################################
openocd:
openocd -f swerv.cfg
jlink:
openocd -f jlink.cfg
gdb:
$(GDB_PREFIX) -x gdbinit ./build/jtag.bin
help:
@echo Possible targets: verilator help clean all verilator-build program.hex
.PHONY: help clean verilator

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# jtag simulation
## gen SweRV module from scala
```bash
cd Quasar
export RV_ROOT=${PWD}
cd tools
make clean
make conf
make -f $RV_ROOT/tools/Makefile sbt_
# Quasar/generated_rtl/quasar_wrapper.sv
```
## start openocd
`openocd -d -f swerv.cfg`
## start gdb
`/opt/riscv/bin/riscv32-unknown-elf-gdb -ex "target extended-remote :3333"`
## quick start
At demo/jtag/
1. `make all`
2. `make openocd`
3. `make gdb`

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# set debug remote 1
target extended-remote :3333
set remotetimeout 2000

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#
# SEGGER J-Link
#
# http://www.segger.com/jlink.html
#
adapter driver jlink
transport select jtag
adapter speed 200
# Target configuration for the riscv chip
set _CHIPNAME riscv
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x1000008b
set _TARGETNAME $_CHIPNAME.tap
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
# Configure work area in on-chip SRAM
# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0
riscv expose_csrs 1988
# Be verbose about GDB errors
gdb_report_data_abort enable
gdb_report_register_access_error enable
# Increase timeouts in simulation
riscv set_command_timeout_sec 1200
# Conclude OpenOCD configuration
init
# Halt the target
halt
# The serial number can be used to select a specific device in case more than
# one is connected to the host.
#
# Example: Select J-Link with serial number 123456789
#
# adapter serial 123456789

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// Assembly code for Hello World
// Not using only ALU ops for creating the string
#include "defines.h"
#define STDOUT 0xd0580000
// Code to execute
.section .text
.global _start
_start:
// Clear minstret
csrw minstret, zero
csrw minstreth, zero
// Set up MTVEC - not expecting to use it though
li x1, RV_ICCM_SADR
csrw mtvec, x1
// Enable Caches in MRAC
li x1, 0x5f555555
csrw 0x7c0, x1
// Load string from hw_data
// and write to stdout address
li x3, STDOUT
la x4, hw_data
loop:
lb x5, 0(x4)
sb x5, 0(x3)
addi x4, x4, 1
bnez x5, loop
li x3, STDOUT
la x4, hw_data
loop2:
lb x5, 0(x4)
sb x5, 0(x3)
addi x4, x4, 1
bnez x5, loop2
loop3:
beq x0, x0, loop3
// Write 0xff to STDOUT for TB to terminate test.
_finish:
li x3, STDOUT
addi x5, x0, 0xff
sb x5, 0(x3)
beq x0, x0, _finish
.rept 100
nop
.endr
.global hw_data
.data
hw_data:
.ascii "----------------------------------\n"
.ascii "Hello World Colin.liang EL2@WDC !!\n"
.ascii "----------------------------------\n"
.byte 0

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OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
. = 0x80000000;
.text_init : { *(.text_init*) }
.text : { *(.text*) }
_end = .;
. = 0xf0040000;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
.bss : { *(.bss) }
. = 0xd0580000;
.data.io : { *(.data.io) }
}

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OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
. = 0x0000;
.text_init : { *(.text_init*) }
.text : { *(.text*) }
_end = .;
. = 0x800;
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
.bss : { *(.bss) }
. = 0xd0580000;
.data.io : { *(.data.io) }
}

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LOCATE COMP "clk" SITE "P3";
IOBUF PORT "clk" IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk" 25 MHZ;
LOCATE COMP "dbg_rst" SITE "N2";
IOBUF PORT "dbg_rst" IO_TYPE=LVCMOS33;
FREQUENCY PORT "dbg_rst" 25 MHZ;
LOCATE COMP "rst" SITE "N3";
IOBUF PORT "rst" IO_TYPE=LVCMOS33;
FREQUENCY PORT "rst" 25 MHZ;
LOCATE COMP "jtag_tck" SITE "T2";
IOBUF PORT "jtag_tck" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_tck" 25 MHZ;
LOCATE COMP "jtag_tms" SITE "T3";
IOBUF PORT "jtag_tms" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_tms" 25 MHZ;
LOCATE COMP "jtag_tdi" SITE "N4";
IOBUF PORT "jtag_tdi" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_tdi" 25 MHZ;
LOCATE COMP "jtag_trst_n" SITE "M3";
IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_trst_n" 25 MHZ;
LOCATE COMP "jtag_tdo" SITE "M4";
IOBUF PORT "jtag_tdo" IO_TYPE=LVCMOS33;
LOCATE COMP "clk_o" SITE "A3";
IOBUF PORT "clk_o" IO_TYPE=LVCMOS33;

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# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket
# speaking the remote_bitbang protocol. The adapter is implemented as
# SystemVerilog DPI module.
adapter driver remote_bitbang
remote_bitbang host localhost
remote_bitbang port 44853
# Target configuration for the riscv chip
set _CHIPNAME riscv
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME tap -irlen 5 -expected-id 0x1000008b
set _TARGETNAME $_CHIPNAME.tap
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
# Configure work area in on-chip SRAM
# $_TARGETNAME configure -work-area-phys 0x1000e000 -work-area-size 1000 -work-area-backup 0
riscv expose_csrs 1988
# Be verbose about GDB errors
gdb_report_data_abort enable
gdb_report_register_access_error enable
# Increase timeouts in simulation
riscv set_command_timeout_sec 1200
# Conclude OpenOCD configuration
init
# Halt the target
halt

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#!/bin/bash
set -ex
PWD=$(pwd)
SOC=$PWD/../soc/
SOCFILE=../soc/soc_top.mk
DEFINE_DIR=$PWD/../design/snapshots/default
DEFINE="${DEFINE_DIR}/pd_defines.vh"
mkdir -p gen
rm -rf gen/*
mkdir gen/design
YOSYS_COARSE=true
YOSYS_GLOBRST=false
YOSYS_SPLITNETS=false
TOP="soc_top"
RTL_FILES="$DEFINE $(cat $SOCFILE | sed 's/[[:space:]]//g' | sed '/^$/d' | sed -e "s!^!$SOC!" | tr '\n' ' ')"
sv2v -I${DEFINE_DIR} $RTL_FILES > gen/soc_top.v
{
echo "read_verilog gen/soc_top.v"
if test -n "$TOP"; then
echo "hierarchy -check -top $TOP"
else
echo "hierarchy -check"
fi
if $YOSYS_GLOBRST; then
# insertation of global reset (e.g. for FPGA cores)
echo "add -global_input globrst 1"
echo "proc -global_arst globrst"
fi
echo "synth -run coarse; opt -fine"
# echo "tee -o gen/brams.log memory_bram -rules scripts/brams.txt;;"
if ! $YOSYS_COARSE; then
echo "memory_map; techmap; opt; abc -dff; clean"
fi
if $YOSYS_SPLITNETS; then
# icarus verilog has a performance problems when there are
# dependencies between the bits of a long vector
echo "splitnets; clean"
fi
if $YOSYS_COARSE; then
echo "write_verilog -noexpr -noattr gen/synth.v"
else
echo "select -assert-none t:\$[!_]"
echo "write_verilog -noattr gen/synth.v"
fi
echo "synth_ecp5 -top $TOP -json gen/soc.json"
# echo "synth_xilinx -top $TOP"
} > gen/synth.ys
yosys -v2 -l gen/synth.log gen/synth.ys
nextpnr-ecp5 --25k --package CABGA381 --speed 6 --textcfg soc.cfg --lpf soc.lpf --freq 1 --json gen/soc.json

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
#include <stdlib.h>
#include <iostream>
#include <utility>
#include <string>
#include "Vsoc_sim.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
vluint64_t main_time = 0;
double sc_time_stamp () {
return main_time;
}
int main(int argc, char** argv) {
std::cout << "\nVerilatorTB: Start of sim\n" << std::endl;
Verilated::commandArgs(argc, argv);
Vsoc_sim* soc = new Vsoc_sim;
// init trace dump
VerilatedVcdC* tfp = NULL;
#if VM_TRACE
Verilated::traceEverOn(true);
tfp = new VerilatedVcdC;
soc->trace (tfp, 24);
tfp->open ("sim.vcd");
#endif
// Simulate
while(!Verilated::gotFinish()){
#if VM_TRACE
tfp->dump (main_time);
#endif
main_time += 5;
soc->core_clk = !soc->core_clk;
soc->eval();
}
#if VM_TRACE
tfp->close();
#endif
std::cout << "\nVerilatorTB: End of sim" << std::endl;
exit(EXIT_SUCCESS);
}

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// ThisBuild / scalaVersion := "2.13.8"
// ThisBuild / version := "3.3.0"
// ThisBuild / organization := "COLIN"
// mainClass in (Compile, run) := Some("QUASAR_Wrp")
// resolvers ++= Seq(
// Resolver.sonatypeRepo("snapshots"),
// Resolver.sonatypeRepo("releases")
// )
// val chiselVersion = "3.5.2"
// lazy val root = (project in file("."))
// .settings(
// name := "QUASAR",
// libraryDependencies ++= Seq(
// "edu.berkeley.cs" %% "chisel3" % chiselVersion,
// "edu.berkeley.cs" %% "chisel-iotesters" % "2.5.2",
// "edu.berkeley.cs" %% "chiseltest" % "0.5.2"
// ),
// scalacOptions ++= Seq(
// "-language:reflectiveCalls",
// "-deprecation",
// "-feature",
// "-Xcheckinit",
// "-P:chiselplugin:genBundleElements",
// "-Ymacro-annotations",
// ),
// addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full),
// )
ThisBuild / scalaVersion := "2.12.10"
ThisBuild / version := "3.3.0"
ThisBuild / organization := "COLIN"
mainClass in (Compile, run) := Some("QUASAR_Wrp")
resolvers ++= Seq(
Resolver.sonatypeRepo("snapshots"),
Resolver.sonatypeRepo("releases")
)
lazy val root = (project in file("."))
.settings(
name := "QUASAR",
libraryDependencies ++= Seq(
"edu.berkeley.cs" %% "chisel-iotesters" % "1.4.1",
"edu.berkeley.cs" %% "chiseltest" % "0.2.1+"
),
scalacOptions ++= Seq(
"-Xsource:2.11"
),
addCompilerPlugin(
"org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full
)
)

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import os
key= "RV_ROOT"
root = os.getenv(key)
infile = root+"/design/quasar_wrapper.v"
outfile = root+"/design/quasar_wrapper.sv"
delete_list1 = ["if (dbg_dm_rst_l)"]
delete_list2 = ["if (_T_597)"]
delete_list3 = ["if (io_dbg_rst_l)"]
delete_list4 = ["if (reset)"]
delete_list5 = ["posedge reset"]
delete_list6 = ["posedge dbg_dm_rst_l"]
delete_list7 = ["posedge _T_597"]
delete_list8 = ["posedge io_dbg_rst_l"]
delete_list9 = ["if (rst_not)"]
delete_list10 = ["posedge rst_not"]
delete_list11 = ["rvclkhdr"]
fin = open(infile)
fout = open(outfile, "w+")
for line in fin:
for word in delete_list1:
line = line.replace(word, "if (~dbg_dm_rst_l)")
for word in delete_list2:
line = line.replace(word, "if (~_T_597)")
for word in delete_list3:
line = line.replace(word, "if (~io_dbg_rst_l)")
for word in delete_list4:
line = line.replace(word, "if (~reset)")
for word in delete_list5:
line = line.replace(word, "negedge reset")
for word in delete_list6:
line = line.replace(word, "negedge dbg_dm_rst_l")
for word in delete_list7:
line = line.replace(word, "negedge _T_597")
for word in delete_list8:
line = line.replace(word, "negedge io_dbg_rst_l")
for word in delete_list9:
line = line.replace(word, "if (~rst_not)")
for word in delete_list10:
line = line.replace(word, "negedge rst_not")
for word in delete_list11:
line = line.replace(word, "rvclkhdr_ch")
fout.write(line)
fin.close()
fout.close()

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// all flops call the rvdff flop
`define RV_FPGA_OPTIMIZE 1
`define RV_PHYSICAL 1
module rvdff #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
if (SHORT == 1) begin
assign dout = din;
end
else begin
`ifdef RV_CLOCKGATE
always @(posedge tb_top.clk) begin
#0 $strobe("CG: %0t %m din %x dout %x clk %b width %d",$time,din,dout,clk,WIDTH);
end
`endif
always_ff @(posedge clk or negedge rst_l) begin
if (rst_l == 0)
dout[WIDTH-1:0] <= 0;
else
dout[WIDTH-1:0] <= din[WIDTH-1:0];
end
end
endmodule
// rvdff with 2:1 input mux to flop din iff sel==1
module rvdffs #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
if (SHORT == 1) begin : genblock
assign dout = din;
end
else begin : genblock
rvdff #(WIDTH) dffs (.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]), .*);
end
endmodule
// rvdff with en and clear
module rvdffsc #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clear,
input logic clk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_new;
if (SHORT == 1) begin
assign dout = din;
end
else begin
assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]);
rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*);
end
endmodule
// _fpga versions
module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
if (SHORT == 1) begin
assign dout = din;
end
else begin
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken), .*);
`else
rvdff #(WIDTH) dff (.*);
`endif
end
endmodule
// rvdff with 2:1 input mux to flop din iff sel==1
module rvdffs_fpga #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
if (SHORT == 1) begin : genblock
assign dout = din;
end
else begin : genblock
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken & en), .*);
`else
rvdffs #(WIDTH) dffs (.*);
`endif
end
endmodule
// rvdff with en and clear
module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clear,
input logic clk,
input logic clken,
input logic rawclk,
input logic rst_l,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_new;
if (SHORT == 1) begin
assign dout = din;
end
else begin
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dffs (.clk(rawclk), .din(din[WIDTH-1:0] & {WIDTH{~clear}}),.en((en | clear) & clken), .*);
`else
rvdffsc #(WIDTH) dffsc (.*);
`endif
end
endmodule
module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 )
(
input logic [WIDTH-1:0] din,
input logic en,
input logic clk,
input logic rst_l,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
logic l1clk;
if (SHORT == 1) begin : genblock
if (1) begin : genblock
assign dout = din;
end
end
else begin : genblock
`ifndef RV_PHYSICAL
if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvclkhdr clkhdr ( .* );
rvdff #(WIDTH) dff (.*, .clk(l1clk));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffe must be WIDTH >= 8");
`endif
end // else: !if(SHORT == 1)
endmodule // rvdffe
module rvdffpcie #( parameter WIDTH=31 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic en,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
`ifndef RV_PHYSICAL
if (WIDTH == 31) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvdfflie #(.WIDTH(WIDTH), .LEFT(19)) dff (.*);
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffpcie width must be 31");
`endif
endmodule
// format: { LEFT, EXTRA }
// LEFT # of bits will be done with rvdffie, all else EXTRA with rvdffe
module rvdfflie #( parameter WIDTH=16, LEFT=8 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic en,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
localparam EXTRA = WIDTH-LEFT;
localparam LMSB = WIDTH-1;
localparam LLSB = LMSB-LEFT+1;
localparam XMSB = LLSB-1;
localparam XLSB = LLSB-EXTRA;
`ifndef RV_PHYSICAL
if (WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvdffiee #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
rvdffe #(EXTRA) dff_extra (.*, .din(din[XMSB:XLSB]), .dout(dout[XMSB:XLSB]));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdfflie musb be WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8");
`endif
endmodule
// special power flop for predict packet
// format: { LEFT, RIGHT==31 }
// LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
module rvdffppe #( parameter WIDTH=32 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic en,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
localparam RIGHT = 31;
localparam LEFT = WIDTH - RIGHT;
localparam LMSB = WIDTH-1;
localparam LLSB = LMSB-LEFT+1;
localparam RMSB = LLSB-1;
localparam RLSB = LLSB-RIGHT;
`ifndef RV_PHYSICAL
if (WIDTH>=32 && LEFT>=8 && RIGHT>=8) begin: genblock
`endif
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvdffe #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
rvdffe #(RIGHT) dff_right (.*, .din(din[RMSB:RLSB]), .dout(dout[RMSB:RLSB]), .en(en & din[LLSB])); // qualify with pret
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: must be WIDTH>=32 && LEFT>=8 && RIGHT>=8");
`endif
endmodule
module rvdffie #( parameter WIDTH=1, OVERRIDE=0 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic scan_mode,
output logic [WIDTH-1:0] dout
);
logic l1clk;
logic en;
`ifndef RV_PHYSICAL
if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
`endif
assign en = |(din ^ dout);
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .* );
`else
rvclkhdr clkhdr ( .* );
rvdff #(WIDTH) dff (.*, .clk(l1clk));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffie must be WIDTH >= 8");
`endif
endmodule
// ie flop but it has an .en input
module rvdffiee #( parameter WIDTH=1, OVERRIDE=0 )
(
input logic [WIDTH-1:0] din,
input logic clk,
input logic rst_l,
input logic scan_mode,
input logic en,
output logic [WIDTH-1:0] dout
);
logic l1clk;
logic final_en;
`ifndef RV_PHYSICAL
if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
`endif
assign final_en = (|(din ^ dout)) & en;
`ifdef RV_FPGA_OPTIMIZE
rvdffs #(WIDTH) dff ( .*, .en(final_en) );
`else
rvdffe #(WIDTH) dff (.*, .en(final_en));
`endif
`ifndef RV_PHYSICAL
end
else
$error("%m: rvdffie width must be >= 8");
`endif
endmodule
module rvsyncss #(parameter WIDTH = 251)
(
input logic clk,
input logic rst_l,
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_ff1;
rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));
rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
endmodule // rvsyncss
module rvsyncss_fpga #(parameter WIDTH = 251)
(
input logic gw_clk,
input logic rawclk,
input logic clken,
input logic rst_l,
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:0] din_ff1;
rvdff_fpga #(WIDTH) sync_ff1 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));
rvdff_fpga #(WIDTH) sync_ff2 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
endmodule // rvsyncss
module rvlsadder
(
input logic [31:0] rs1,
input logic [11:0] offset,
output logic [31:0] dout
);
logic cout;
logic sign;
logic [31:12] rs1_inc;
logic [31:12] rs1_dec;
assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
assign rs1_inc[31:12] = rs1[31:12] + 1;
assign rs1_dec[31:12] = rs1[31:12] - 1;
assign sign = offset[11];
assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) |
({20{ ~sign & cout}} & rs1_inc[31:12]) |
({20{ sign & ~cout}} & rs1_dec[31:12]);
endmodule // rvlsadder
// assume we only maintain pc[31:1] in the pipe
module rvbradder
(
input [31:1] pc,
input [12:1] offset,
output [31:1] dout
);
logic cout;
logic sign;
logic [31:13] pc_inc;
logic [31:13] pc_dec;
assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]};
assign pc_inc[31:13] = pc[31:13] + 1;
assign pc_dec[31:13] = pc[31:13] - 1;
assign sign = offset[12];
assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) |
({19{ ~sign & cout}} & pc_inc[31:13]) |
({19{ sign & ~cout}} & pc_dec[31:13]);
endmodule // rvbradder
// 2s complement circuit
module rvtwoscomp #( parameter WIDTH=32 )
(
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din
genvar i;
for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one
assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i];
end : flip_after_first_one
assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] };
endmodule // 2'scomp
// find first
module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) )
(
input logic [WIDTH-1:0] din,
output logic [SHIFT-1:0] dout
);
logic done;
always_comb begin
dout[SHIFT-1:0] = {SHIFT{1'b0}};
done = 1'b0;
for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one
done |= din[i];
dout[SHIFT-1:0] += done ? 1'b0 : 1'b1;
end : find_first_one
end
endmodule // rvfindfirst1
module rvfindfirst1hot #( parameter WIDTH=32 )
(
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout
);
logic done;
always_comb begin
dout[WIDTH-1:0] = {WIDTH{1'b0}};
done = 1'b0;
for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one
dout[i] = ~done & din[i];
done |= din[i];
end : find_first_one
end
endmodule // rvfindfirst1hot
// mask and match function matches bits after finding the first 0 position
// find first starting from LSB. Skip that location and match the rest of the bits
module rvmaskandmatch #( parameter WIDTH=32 )
(
input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions
input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits
input logic masken, // when 1 : do mask. 0 : full match
output logic match
);
logic [WIDTH-1:0] matchvec;
logic masken_or_fullmask;
assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]);
assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]);
genvar i;
for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero
assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]);
end : match_after_first_zero
assign match = &matchvec[WIDTH-1:0]; // all bits either matched or were masked off
endmodule // rvmaskandmatch
// Check if the S_ADDR <= addr < E_ADDR
module rvrangecheck #(CCM_SADR = 32'h0,
CCM_SIZE = 128) (
input logic [31:0] addr, // Address to be checked for range
output logic in_range, // S_ADDR <= start_addr < E_ADDR
output logic in_region
);
localparam REGION_BITS = 4;
localparam MASK_BITS = 10 + $clog2(CCM_SIZE);
logic [31:0] start_addr;
logic [3:0] region;
assign start_addr[31:0] = CCM_SADR;
assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)];
assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]);
if (CCM_SIZE == 48)
assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]);
else
assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]);
endmodule // rvrangechecker
// 16 bit even parity generator
module rveven_paritygen #(WIDTH = 16) (
input logic [WIDTH-1:0] data_in, // Data
output logic parity_out // generated even parity
);
assign parity_out = ^(data_in[WIDTH-1:0]) ;
endmodule // rveven_paritygen
module rveven_paritycheck #(WIDTH = 16) (
input logic [WIDTH-1:0] data_in, // Data
input logic parity_in,
output logic parity_err // Parity error
);
assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ;
endmodule // rveven_paritycheck
module rvecc_encode (
input [31:0] din,
output [6:0] ecc_out
);
logic [5:0] ecc_out_temp;
assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]};
endmodule // rvecc_encode
module rvecc_decode (
input en,
input [31:0] din,
input [6:0] ecc_in,
input sed_ded, // only do detection and no correction. Used for the I$
output [31:0] dout,
output [6:0] ecc_out,
output single_ecc_error,
output double_ecc_error
);
logic [6:0] ecc_check;
logic [38:0] error_mask;
logic [38:0] din_plus_parity, dout_plus_parity;
// Generate the ecc bits
assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
// This is the parity bit
assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded;
assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded
assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE
// Generate the mask for error correctiong
for (genvar i=1; i<40; i++) begin
assign error_mask[i-1] = (ecc_check[5:0] == i);
end
// Generate the corrected data
assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]};
assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0];
assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]};
assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]};
endmodule // rvecc_decode
module rvecc_encode_64 (
input [63:0] din,
output [6:0] ecc_out
);
assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
assign ecc_out[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63];
assign ecc_out[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63];
assign ecc_out[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_out[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_out[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_out[6] = din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63];
endmodule // rvecc_encode_64
module rvecc_decode_64 (
input en,
input [63:0] din,
input [6:0] ecc_in,
output ecc_error
);
logic [6:0] ecc_check;
// Generate the ecc bits
assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63];
assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63];
assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
assign ecc_check[6] = ecc_in[6]^din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63];
assign ecc_error = en & (ecc_check[6:0] != 0); // all errors in the sed_ded case will be recorded as DE
endmodule // rvecc_decode_64
module TEC_RV_ICG
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
`ifdef VERILATOR
always @(negedge CK) begin
en_ff <= enable;
end
`else
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
`endif
assign Q = CK & en_ff;
endmodule
module rvoclkhdr
(
input logic en,
input logic clk,
input logic scan_mode,
output logic l1clk
);
logic SE;
assign SE = 0;
`ifdef RV_FPGA_OPTIMIZE
assign l1clk = clk;
`else
TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
`endif
endmodule

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//------------------------------------------------------------------------------------
//
// Copyright Western Digital, 2019
// Owner : Alex Grobman
// Description:
// This module Synchronizes the signals between JTAG (TCK) and
// processor (Core_clk)
//
//-------------------------------------------------------------------------------------
module dmi_jtag_to_core_sync (
// JTAG signals
input rd_en, // 1 bit Read Enable from JTAG
input wr_en, // 1 bit Write enable from JTAG
// Processor Signals
input rst_n, // Core reset
input clk, // Core clock
output reg_en, // 1 bit Write interface bit to Processor
output reg_wr_en // 1 bit Write enable to Processor
);
wire c_rd_en;
wire c_wr_en;
reg [2:0] rden, wren;
// Outputs
assign reg_en = c_wr_en | c_rd_en;
assign reg_wr_en = c_wr_en;
// synchronizers
always @ ( posedge clk or negedge rst_n) begin
if(!rst_n) begin
rden <= '0;
wren <= '0;
end
else begin
rden <= {rden[1:0], rd_en};
wren <= {wren[1:0], wr_en};
end
end
assign c_rd_en = rden[1] & ~rden[2];
assign c_wr_en = wren[1] & ~wren[2];
endmodule

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//------------------------------------------------------------------------------------
//
// Copyright Western Digital, 2018
// Owner : Anusha Narayanamoorthy
// Description:
// Wrapper module for JTAG_TAP and DMI synchronizer
//
//-------------------------------------------------------------------------------------
module dmi_wrapper(
// JTAG signals
input trst_n, // JTAG reset
input tck, // JTAG clock
input tms, // Test mode select
input tdi, // Test Data Input
output tdo, // Test Data Output
output tdoEnable, // Test Data Output enable
// Processor Signals
input core_rst_n, // Core reset
input core_clk, // Core clock
input [31:1] jtag_id, // JTAG ID
input [31:0] rd_data, // 32 bit Read data from Processor
output [31:0] reg_wr_data, // 32 bit Write data to Processor
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
output reg_en, // 1 bit Read enable to Processor
output reg_wr_en, // 1 bit Write enable to Processor
output dmi_hard_reset
);
//Wire Declaration
wire rd_en;
wire wr_en;
wire dmireset;
//jtag_tap instantiation
rvjtag_tap i_jtag_tap(
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
.tck(tck), // dedicated JTAG TCK pad signal
.tms(tms), // dedicated JTAG TMS pad signal
.tdi(tdi), // dedicated JTAG TDI pad signal
.tdo(tdo), // dedicated JTAG TDO pad signal
.tdoEnable(tdoEnable), // enable for TDO pad
.wr_data(reg_wr_data), // 32 bit Write data
.wr_addr(reg_wr_addr), // 7 bit Write address
.rd_en(rd_en), // 1 bit read enable
.wr_en(wr_en), // 1 bit Write enable
.rd_data(rd_data), // 32 bit Read data
.rd_status(2'b0),
.idle(3'h0), // no need to wait to sample data
.dmi_stat(2'b0), // no need to wait or error possible
.version(4'h1), // debug spec 0.13 compliant
.jtag_id(jtag_id),
.dmi_hard_reset(dmi_hard_reset),
.dmi_reset(dmireset)
);
// dmi_jtag_to_core_sync instantiation
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
.wr_en(wr_en), // 1 bit Write enable
.rd_en(rd_en), // 1 bit Read enable
.rst_n(core_rst_n),
.clk(core_clk),
.reg_en(reg_en), // 1 bit Write interface bit
.reg_wr_en(reg_wr_en) // 1 bit Write enable
);
endmodule

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module gated_latch
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule

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//********************************************************************************
// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//********************************************************************************
//********************************************************************************
// Icache closely coupled memory --- ICCM
//********************************************************************************
module ifu_iccm_mem
//`include "parameter.sv"
#(
parameter ICCM_BITS,
parameter ICCM_BANK_INDEX_LO,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICCM_NUM_BANKS,
// parameter ICCM_ENABLE= 'b1,
parameter ICCM_BANK_BITS
)
(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
input logic clk_override, // Override non-functional clock gating
input logic iccm_wren, // ICCM write enable
input logic iccm_rden, // ICCM read enable
input logic [ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // ICCM under a correction - This is needed to guard replacements when hit
input logic [2:0] iccm_wr_size, // ICCM write size
input logic [77:0] iccm_wr_data, // ICCM write data
input iccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, // External packet
output logic [63:0] iccm_rd_data, // ICCM read data
output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc
input logic scan_mode // Scan mode control
);
logic [ICCM_NUM_BANKS-1:0] wren_bank;
logic [ICCM_NUM_BANKS-1:0] rden_bank;
logic [ICCM_NUM_BANKS-1:0] iccm_clken;
logic [ICCM_NUM_BANKS-1:0] [ICCM_BITS-1:ICCM_BANK_INDEX_LO] addr_bank;
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_dout, iccm_bank_dout_fn;
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data;
logic [ICCM_BITS-1:1] addr_bank_inc;
logic [ICCM_BANK_HI : 2] iccm_rd_addr_hi_q;
logic [ICCM_BANK_HI : 1] iccm_rd_addr_lo_q;
logic [63:0] iccm_rd_data_pre;
logic [63:0] iccm_data;
logic [1:0] addr_incr;
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data_vec;
// logic to handle hard persisten faults
logic [1:0] [ICCM_BITS-1:2] redundant_address;
logic [1:0] [38:0] redundant_data;
logic [1:0] redundant_valid;
logic [ICCM_NUM_BANKS-1:0] sel_red1, sel_red0, sel_red1_q, sel_red0_q;
logic [38:0] redundant_data0_in, redundant_data1_in;
logic redundant_lru, redundant_lru_in, redundant_lru_en;
logic redundant_data0_en;
logic redundant_data1_en;
logic r0_addr_en, r1_addr_en;
// Testing persistent flip
// logic [3:0] not_iccm_bank_dout;
// logic [15:3] ecc_insert_flip_in, ecc_insert_flip;
// logic flip_en, flip_match, flip_match_q;
//
// assign flip_in = (iccm_rw_addr[3:2] != 2'b00); // dont flip when bank0 - this is to make some progress in DMA streaming cases
// assign flip_en = iccm_rden;
//
// rvdffs #(1) flipmatch (.*,
// .clk(clk),
// .din(flip_in),
// .en(flip_en),
// .dout(flip_match_q));
//
// end of testing flip
assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11) ? 2'b10: 2'b01;
assign addr_bank_inc[ICCM_BITS-1 : 1] = iccm_rw_addr[ICCM_BITS-1 : 1] + addr_incr[1:0];
for (genvar i=0; i<ICCM_NUM_BANKS/2; i++) begin: mem_bank_data
assign iccm_bank_wr_data_vec[(2*i)] = iccm_wr_data[38:0];
assign iccm_bank_wr_data_vec[(2*i)+1] = iccm_wr_data[77:39];
end
for (genvar i=0; i<ICCM_NUM_BANKS; i++) begin: mem_bank
assign wren_bank[i] = iccm_wren & ((iccm_rw_addr[ICCM_BANK_HI:2] == i) | (addr_bank_inc[ICCM_BANK_HI:2] == i));
assign iccm_bank_wr_data[i] = iccm_bank_wr_data_vec[i];
assign rden_bank[i] = iccm_rden & ( (iccm_rw_addr[ICCM_BANK_HI:2] == i) | (addr_bank_inc[ICCM_BANK_HI:2] == i));
assign iccm_clken[i] = wren_bank[i] | rden_bank[i] | clk_override;
assign addr_bank[i][ICCM_BITS-1 : ICCM_BANK_INDEX_LO] = wren_bank[i] ? iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO] :
((addr_bank_inc[ICCM_BANK_HI:2] == i) ?
addr_bank_inc[ICCM_BITS-1 : ICCM_BANK_INDEX_LO] :
iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO]);
`ifdef VERILATOR
el2_ram #(.depth(1<<ICCM_INDEX_BITS), .width(39)) iccm_bank (
// Primary ports
.ME(iccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
`else
if (ICCM_INDEX_BITS == 6 ) begin : iccm
ram_64x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 7 ) begin : iccm
ram_128x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 8 ) begin : iccm
ram_256x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 9 ) begin : iccm
ram_512x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 10 ) begin : iccm
ram_1024x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 11 ) begin : iccm
ram_2048x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 12 ) begin : iccm
ram_4096x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 13 ) begin : iccm
ram_8192x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else if (ICCM_INDEX_BITS == 14 ) begin : iccm
ram_16384x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
else begin : iccm
ram_32768x39 iccm_bank (
// Primary ports
.CLK(clk),
.ME(iccm_clken[i]),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(iccm_bank_wr_data[i][38:0]),
.Q(iccm_bank_dout[i][38:0]),
.ROP ( ),
// These are used by SoC
.TEST1(iccm_ext_in_pkt[i].TEST1),
.RME(iccm_ext_in_pkt[i].RME),
.RM(iccm_ext_in_pkt[i].RM),
.LS(iccm_ext_in_pkt[i].LS),
.DS(iccm_ext_in_pkt[i].DS),
.SD(iccm_ext_in_pkt[i].SD) ,
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
.BC1(iccm_ext_in_pkt[i].BC1),
.BC2(iccm_ext_in_pkt[i].BC2)
);
end // block: iccm
`endif
// match the redundant rows
assign sel_red1[i] = (redundant_valid[1] & (((iccm_rw_addr[ICCM_BITS-1:2] == redundant_address[1][ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
((addr_bank_inc[ICCM_BITS-1:2]== redundant_address[1][ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
assign sel_red0[i] = (redundant_valid[0] & (((iccm_rw_addr[ICCM_BITS-1:2] == redundant_address[0][ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
((addr_bank_inc[ICCM_BITS-1:2]== redundant_address[0][ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
rvdff #(1) selred0 (.*,
.clk(active_clk),
.din(sel_red0[i]),
.dout(sel_red0_q[i]));
rvdff #(1) selred1 (.*,
.clk(active_clk),
.din(sel_red1[i]),
.dout(sel_red1_q[i]));
// muxing out the memory data with the redundant data if the address matches
assign iccm_bank_dout_fn[i][38:0] = ({39{sel_red1_q[i]}} & redundant_data[1][38:0]) |
({39{sel_red0_q[i]}} & redundant_data[0][38:0]) |
({39{~sel_red0_q[i] & ~sel_red1_q[i]}} & iccm_bank_dout[i][38:0]);
end : mem_bank
// This section does the redundancy for tolerating single bit errors
// 2x 39 bit data values with address[hi:2] and a valid bit is needed to CAM and sub out the reads/writes to the particular locations
// Also a LRU flop is kept to decide which of the redundant element to replace.
assign r0_addr_en = ~redundant_lru & iccm_buf_correct_ecc;
assign r1_addr_en = redundant_lru & iccm_buf_correct_ecc;
assign redundant_lru_en = iccm_buf_correct_ecc | (((|sel_red0[ICCM_NUM_BANKS-1:0]) | (|sel_red1[ICCM_NUM_BANKS-1:0])) & iccm_rden & iccm_correction_state);
assign redundant_lru_in = iccm_buf_correct_ecc ? ~redundant_lru : (|sel_red0[ICCM_NUM_BANKS-1:0]) ? 1'b1 : 1'b0;
rvdffs #() red_lru (.*, // LRU flop for the redundant replacements
.clk(active_clk),
.en(redundant_lru_en),
.din(redundant_lru_in),
.dout(redundant_lru));
rvdffs #(ICCM_BITS-2) r0_address (.*, // Redundant Row 0 address
.clk(active_clk),
.en(r0_addr_en),
.din(iccm_rw_addr[ICCM_BITS-1:2]),
.dout(redundant_address[0][ICCM_BITS-1:2]));
rvdffs #(ICCM_BITS-2) r1_address (.*, // Redundant Row 0 address
.clk(active_clk),
.en(r1_addr_en),
.din(iccm_rw_addr[ICCM_BITS-1:2]),
.dout(redundant_address[1][ICCM_BITS-1:2]));
rvdffs #(1) r0_valid (.*,
.clk(active_clk), // Redundant Row 0 Valid
.en(r0_addr_en),
.din(1'b1),
.dout(redundant_valid[0]));
rvdffs #(1) r1_valid (.*, // Redundant Row 1 Valid
.clk(active_clk),
.en(r1_addr_en),
.din(1'b1),
.dout(redundant_valid[1]));
// We will have to update the Redundant copies in addition to the memory on subsequent writes to this memory location.
// The data gets updated on : 1) correction cycle, 2) Future writes - this could be W writes from DMA ( match up till addr[2]) or DW writes ( match till address[3])
// The data to pick also depends on the current address[2], size and the addr[2] stored in the address field of the redundant flop. Correction cycle is always W write and the data is splat on both legs, so choosing lower Word
assign redundant_data0_en = ((iccm_rw_addr[ICCM_BITS-1:3] == redundant_address[0][ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[0][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[0] & iccm_wren) |
(~redundant_lru & iccm_buf_correct_ecc);
assign redundant_data0_in[38:0] = (((iccm_rw_addr[2] == redundant_address[0][2]) & iccm_rw_addr[2]) | (redundant_address[0][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
rvdffs #(39) r0_data (.*, // Redundant Row 1 data
.clk(active_clk),
.en(redundant_data0_en),
.din(redundant_data0_in[38:0]),
.dout(redundant_data[0][38:0]));
assign redundant_data1_en = ((iccm_rw_addr[ICCM_BITS-1:3] == redundant_address[1][ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[1][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[1] & iccm_wren) |
(redundant_lru & iccm_buf_correct_ecc);
assign redundant_data1_in[38:0] = (((iccm_rw_addr[2] == redundant_address[1][2]) & iccm_rw_addr[2]) | (redundant_address[1][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
rvdffs #(39) r1_data (.*, // Redundant Row 1 data
.clk(active_clk),
.en(redundant_data1_en),
.din(redundant_data1_in[38:0]),
.dout(redundant_data[1][38:0]));
rvdffs #(ICCM_BANK_HI) rd_addr_lo_ff (.*, .clk(active_clk), .din(iccm_rw_addr [ICCM_BANK_HI:1]), .dout(iccm_rd_addr_lo_q[ICCM_BANK_HI:1]), .en(1'b1)); // bit 0 of address is always 0
rvdffs #(ICCM_BANK_BITS) rd_addr_hi_ff (.*, .clk(active_clk), .din(addr_bank_inc[ICCM_BANK_HI:2]), .dout(iccm_rd_addr_hi_q[ICCM_BANK_HI:2]), .en(1'b1));
assign iccm_rd_data_pre[63:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][31:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][31:0]};
assign iccm_data[63:0] = 64'({16'b0, (iccm_rd_data_pre[63:0] >> (16*iccm_rd_addr_lo_q[1]))});
assign iccm_rd_data[63:0] = {iccm_data[63:0]};
assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][38:0]};
endmodule // ifu_iccm_mem

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// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//********************************************************************************
// $Id$
//
//
// Owner:
// Function: DCCM for LSU pipe
// Comments: Single ported memory
//
//
// DC1 -> DC2 -> DC3 -> DC4 (Commit)
//
// //********************************************************************************
`define LOCAL_DCCM_RAM_TEST_PORTS .TEST1(dccm_ext_in_pkt[i].TEST1), \
.RME(dccm_ext_in_pkt[i].RME), \
.RM(dccm_ext_in_pkt[i].RM), \
.LS(dccm_ext_in_pkt[i].LS), \
.DS(dccm_ext_in_pkt[i].DS), \
.SD(dccm_ext_in_pkt[i].SD), \
.TEST_RNM(dccm_ext_in_pkt[i].TEST_RNM), \
.BC1(dccm_ext_in_pkt[i].BC1), \
.BC2(dccm_ext_in_pkt[i].BC2), \
module lsu_dccm_mem
//`include "parameter.sv"
#(
parameter DCCM_BYTE_WIDTH,
parameter DCCM_BITS,
parameter DCCM_NUM_BANKS,
parameter DCCM_ENABLE= 'b1,
parameter DCCM_BANK_BITS,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter DCCM_WIDTH_BITS
)
(
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
input logic rst_l, // reset, active low
input logic clk_override, // Override non-functional clock gating
input logic dccm_wren, // write enable
input logic dccm_rden, // read enable
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo, // write address
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi, // write address
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo, // read address
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data
input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, // the dccm packet from the soc
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank
input logic scan_mode
);
//localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS);
localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank
logic [DCCM_NUM_BANKS-1:0] wren_bank;
logic [DCCM_NUM_BANKS-1:0] rden_bank;
logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank;
logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd;
logic rd_unaligned, wr_unaligned;
logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;
logic [DCCM_FDATA_WIDTH-1:0] wrdata;
logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank;
logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;
logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;
logic [DCCM_NUM_BANKS-1:0] dccm_clken;
assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
// Align the read data
assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
// 8 Banks, 16KB each (2048 x 72)
for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank
assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i));
assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i));
assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ?
dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]) :
(((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ?
dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]);
assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0];
// clock gating section
assign dccm_clken[i] = (wren_bank[i] | rden_bank[i] | clk_override) ;
// end clock gating section
`ifdef VERILATOR
el2_ram #(DCCM_INDEX_DEPTH,39) ram (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
`else
if (DCCM_INDEX_DEPTH == 32768) begin : dccm
ram_32768x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 16384) begin : dccm
ram_16384x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
ram_8192x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
ram_4096x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 3072) begin : dccm
ram_3072x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 2048) begin : dccm
ram_2048x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 1024) begin : dccm
ram_1024x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 512) begin : dccm
ram_512x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 256) begin : dccm
ram_256x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
else if (DCCM_INDEX_DEPTH == 128) begin : dccm
ram_128x39 dccm_bank (
// Primary ports
.ME(dccm_clken[i]),
.CLK(clk),
.WE(wren_bank[i]),
.ADR(addr_bank[i]),
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
.ROP ( ),
// These are used by SoC
`LOCAL_DCCM_RAM_TEST_PORTS
.*
);
end
`endif
end : mem_bank
// Flops
rvdff #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .clk(active_clk));
rvdff #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .clk(active_clk));
`undef LOCAL_DCCM_RAM_TEST_PORTS
endmodule // lsu_dccm_mem

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@ -0,0 +1,549 @@
//********************************************************************************
// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//********************************************************************************
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} iccm_ext_in_pkt_t;
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} dccm_ext_in_pkt_t;
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} ic_data_ext_in_pkt_t;
typedef struct packed {
logic TEST1;
logic RME;
logic [3:0] RM;
logic LS;
logic DS;
logic SD;
logic TEST_RNM;
logic BC1;
logic BC2;
} ic_tag_ext_in_pkt_t;
module mem#(
parameter ICACHE_BEAT_BITS,
parameter ICCM_BITS,
parameter ICACHE_NUM_WAYS,
parameter DCCM_BYTE_WIDTH,
parameter ICCM_BANK_INDEX_LO,
parameter ICACHE_BANK_BITS,
parameter DCCM_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICACHE_BANKS_WAY,
parameter ICACHE_INDEX_HI,
parameter DCCM_NUM_BANKS,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter DCCM_ENABLE= 'b1,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICCM_NUM_BANKS,
parameter ICACHE_ECC,
parameter ICACHE_ENABLE= 'b1,
parameter DCCM_BANK_BITS,
parameter ICCM_ENABLE= 'b1,
parameter ICCM_BANK_BITS,
parameter ICACHE_TAG_DEPTH,
parameter ICACHE_WAYPACK,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_DATA_DEPTH,
parameter DCCM_WIDTH_BITS,
parameter ICACHE_NUM_BYPASS,
parameter ICACHE_TAG_NUM_BYPASS,
parameter ICACHE_TAG_NUM_BYPASS_WIDTH,
parameter ICACHE_TAG_BYPASS_ENABLE,
parameter ICACHE_NUM_BYPASS_WIDTH,
parameter ICACHE_BYPASS_ENABLE,
parameter ICACHE_LN_SZ
)
(
input logic clk,
input logic rst_l,
input logic dccm_clk_override,
input logic icm_clk_override,
input logic dec_tlu_core_ecc_disable,
//DCCM ports
input logic dccm_wren,
input logic dccm_rden,
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE
//input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
input logic dccm_ext_in_pkt_TEST1_0,
input logic dccm_ext_in_pkt_RME_0,
input logic [3:0] dccm_ext_in_pkt_RM_0,
input logic dccm_ext_in_pkt_LS_0,
input logic dccm_ext_in_pkt_DS_0,
input logic dccm_ext_in_pkt_SD_0,
input logic dccm_ext_in_pkt_TEST_RNM_0,
input logic dccm_ext_in_pkt_BC1_0,
input logic dccm_ext_in_pkt_BC2_0,
input logic dccm_ext_in_pkt_TEST1_1,
input logic dccm_ext_in_pkt_RME_1,
input logic [3:0] dccm_ext_in_pkt_RM_1,
input logic dccm_ext_in_pkt_LS_1,
input logic dccm_ext_in_pkt_DS_1,
input logic dccm_ext_in_pkt_SD_1,
input logic dccm_ext_in_pkt_TEST_RNM_1,
input logic dccm_ext_in_pkt_BC1_1,
input logic dccm_ext_in_pkt_BC2_1,
input logic dccm_ext_in_pkt_TEST1_2,
input logic dccm_ext_in_pkt_RME_2,
input logic [3:0] dccm_ext_in_pkt_RM_2,
input logic dccm_ext_in_pkt_LS_2,
input logic dccm_ext_in_pkt_DS_2,
input logic dccm_ext_in_pkt_SD_2,
input logic dccm_ext_in_pkt_TEST_RNM_2,
input logic dccm_ext_in_pkt_BC1_2,
input logic dccm_ext_in_pkt_BC2_2,
input logic dccm_ext_in_pkt_TEST1_3,
input logic dccm_ext_in_pkt_RME_3,
input logic [3:0] dccm_ext_in_pkt_RM_3,
input logic dccm_ext_in_pkt_LS_3,
input logic dccm_ext_in_pkt_DS_3,
input logic dccm_ext_in_pkt_SD_3,
input logic dccm_ext_in_pkt_TEST_RNM_3,
input logic dccm_ext_in_pkt_BC1_3,
input logic dccm_ext_in_pkt_BC2_3,
//`endif
//ICCM ports
input logic iccm_ext_in_pkt_TEST1_0,
input logic iccm_ext_in_pkt_RME_0,
input logic [3:0] iccm_ext_in_pkt_RM_0,
input logic iccm_ext_in_pkt_LS_0,
input logic iccm_ext_in_pkt_DS_0,
input logic iccm_ext_in_pkt_SD_0,
input logic iccm_ext_in_pkt_TEST_RNM_0,
input logic iccm_ext_in_pkt_BC1_0,
input logic iccm_ext_in_pkt_BC2_0,
input logic iccm_ext_in_pkt_TEST1_1,
input logic iccm_ext_in_pkt_RME_1,
input logic [3:0] iccm_ext_in_pkt_RM_1,
input logic iccm_ext_in_pkt_LS_1,
input logic iccm_ext_in_pkt_DS_1,
input logic iccm_ext_in_pkt_SD_1,
input logic iccm_ext_in_pkt_TEST_RNM_1,
input logic iccm_ext_in_pkt_BC1_1,
input logic iccm_ext_in_pkt_BC2_1,
input logic iccm_ext_in_pkt_TEST1_2,
input logic iccm_ext_in_pkt_RME_2,
input logic [3:0] iccm_ext_in_pkt_RM_2,
input logic iccm_ext_in_pkt_LS_2,
input logic iccm_ext_in_pkt_DS_2,
input logic iccm_ext_in_pkt_SD_2,
input logic iccm_ext_in_pkt_TEST_RNM_2,
input logic iccm_ext_in_pkt_BC1_2,
input logic iccm_ext_in_pkt_BC2_2,
input logic iccm_ext_in_pkt_TEST1_3,
input logic iccm_ext_in_pkt_RME_3,
input logic [3:0] iccm_ext_in_pkt_RM_3,
input logic iccm_ext_in_pkt_LS_3,
input logic iccm_ext_in_pkt_DS_3,
input logic iccm_ext_in_pkt_SD_3,
input logic iccm_ext_in_pkt_TEST_RNM_3,
input logic iccm_ext_in_pkt_BC1_3,
input logic iccm_ext_in_pkt_BC2_3,
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
input logic iccm_wren,
input logic iccm_rden,
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
output logic [63:0] iccm_rd_data,
output logic [77:0] iccm_rd_data_ecc,
// Icache and Itag Ports
input logic [31:1] ic_rw_addr,
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
// input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
input logic ic_tag_ext_in_pkt_TEST1_0,
input logic ic_tag_ext_in_pkt_RME_0,
input logic [3:0] ic_tag_ext_in_pkt_RM_0,
input logic ic_tag_ext_in_pkt_LS_0,
input logic ic_tag_ext_in_pkt_DS_0,
input logic ic_tag_ext_in_pkt_SD_0,
input logic ic_tag_ext_in_pkt_TEST_RNM_0,
input logic ic_tag_ext_in_pkt_BC1_0,
input logic ic_tag_ext_in_pkt_BC2_0,
input logic ic_tag_ext_in_pkt_TEST1_1,
input logic ic_tag_ext_in_pkt_RME_1,
input logic [3:0] ic_tag_ext_in_pkt_RM_1,
input logic ic_tag_ext_in_pkt_LS_1,
input logic ic_tag_ext_in_pkt_DS_1,
input logic ic_tag_ext_in_pkt_SD_1,
input logic ic_tag_ext_in_pkt_TEST_RNM_1,
input logic ic_tag_ext_in_pkt_BC1_1,
input logic ic_tag_ext_in_pkt_BC2_1,
input logic ic_data_ext_in_pkt_0_TEST1_0,
input logic ic_data_ext_in_pkt_0_RME_0,
input logic [3:0] ic_data_ext_in_pkt_0_RM_0,
input logic ic_data_ext_in_pkt_0_LS_0,
input logic ic_data_ext_in_pkt_0_DS_0,
input logic ic_data_ext_in_pkt_0_SD_0,
input logic ic_data_ext_in_pkt_0_TEST_RNM_0,
input logic ic_data_ext_in_pkt_0_BC1_0,
input logic ic_data_ext_in_pkt_0_BC2_0,
input logic ic_data_ext_in_pkt_0_TEST1_1,
input logic ic_data_ext_in_pkt_0_RME_1,
input logic [3:0] ic_data_ext_in_pkt_0_RM_1,
input logic ic_data_ext_in_pkt_0_LS_1,
input logic ic_data_ext_in_pkt_0_DS_1,
input logic ic_data_ext_in_pkt_0_SD_1,
input logic ic_data_ext_in_pkt_0_TEST_RNM_1,
input logic ic_data_ext_in_pkt_0_BC1_1,
input logic ic_data_ext_in_pkt_0_BC2_1,
input logic ic_data_ext_in_pkt_1_TEST1_0,
input logic ic_data_ext_in_pkt_1_RME_0,
input logic [3:0] ic_data_ext_in_pkt_1_RM_0,
input logic ic_data_ext_in_pkt_1_LS_0,
input logic ic_data_ext_in_pkt_1_DS_0,
input logic ic_data_ext_in_pkt_1_SD_0,
input logic ic_data_ext_in_pkt_1_TEST_RNM_0,
input logic ic_data_ext_in_pkt_1_BC1_0,
input logic ic_data_ext_in_pkt_1_BC2_0,
input logic ic_data_ext_in_pkt_1_TEST1_1,
input logic ic_data_ext_in_pkt_1_RME_1,
input logic [3:0] ic_data_ext_in_pkt_1_RM_1,
input logic ic_data_ext_in_pkt_1_LS_1,
input logic ic_data_ext_in_pkt_1_DS_1,
input logic ic_data_ext_in_pkt_1_SD_1,
input logic ic_data_ext_in_pkt_1_TEST_RNM_1,
input logic ic_data_ext_in_pkt_1_BC1_1,
input logic ic_data_ext_in_pkt_1_BC2_1,
// input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
input logic ic_debug_rd_en, // Icache debug rd
input logic ic_debug_wr_en, // Icache debug wr
input logic ic_debug_tag_array, // Debug tag array
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error
input logic scan_mode
);
iccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt;
dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt;
ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt;
ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt;
assign dccm_ext_in_pkt[0].TEST1 = dccm_ext_in_pkt_TEST1_0;
assign dccm_ext_in_pkt[0].RME = dccm_ext_in_pkt_RME_0;
assign dccm_ext_in_pkt[0].RM = dccm_ext_in_pkt_RM_0[3:0];
assign dccm_ext_in_pkt[0].LS = dccm_ext_in_pkt_LS_0;
assign dccm_ext_in_pkt[0].DS = dccm_ext_in_pkt_DS_0;
assign dccm_ext_in_pkt[0].SD = dccm_ext_in_pkt_SD_0;
assign dccm_ext_in_pkt[0].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_0;
assign dccm_ext_in_pkt[0].BC1 = dccm_ext_in_pkt_BC1_0;
assign dccm_ext_in_pkt[0].BC2 = dccm_ext_in_pkt_BC2_0;
assign dccm_ext_in_pkt[1].TEST1 = dccm_ext_in_pkt_TEST1_1;
assign dccm_ext_in_pkt[1].RME = dccm_ext_in_pkt_RME_1;
assign dccm_ext_in_pkt[1].RM = dccm_ext_in_pkt_RM_1[3:0];
assign dccm_ext_in_pkt[1].LS = dccm_ext_in_pkt_LS_1;
assign dccm_ext_in_pkt[1].DS = dccm_ext_in_pkt_DS_1;
assign dccm_ext_in_pkt[1].SD = dccm_ext_in_pkt_SD_1;
assign dccm_ext_in_pkt[1].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_1;
assign dccm_ext_in_pkt[1].BC1 = dccm_ext_in_pkt_BC1_1;
assign dccm_ext_in_pkt[1].BC2 = dccm_ext_in_pkt_BC2_1;
assign dccm_ext_in_pkt[2].TEST1 = dccm_ext_in_pkt_TEST1_2;
assign dccm_ext_in_pkt[2].RME = dccm_ext_in_pkt_RME_2;
assign dccm_ext_in_pkt[2].RM = dccm_ext_in_pkt_RM_2[3:0];
assign dccm_ext_in_pkt[2].LS = dccm_ext_in_pkt_LS_2;
assign dccm_ext_in_pkt[2].DS = dccm_ext_in_pkt_DS_2;
assign dccm_ext_in_pkt[2].SD = dccm_ext_in_pkt_SD_2;
assign dccm_ext_in_pkt[2].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_2;
assign dccm_ext_in_pkt[2].BC1 = dccm_ext_in_pkt_BC1_2;
assign dccm_ext_in_pkt[2].BC2 = dccm_ext_in_pkt_BC2_2;
assign dccm_ext_in_pkt[3].TEST1 = dccm_ext_in_pkt_TEST1_3;
assign dccm_ext_in_pkt[3].RME = dccm_ext_in_pkt_RME_3;
assign dccm_ext_in_pkt[3].RM = dccm_ext_in_pkt_RM_3[3:0];
assign dccm_ext_in_pkt[3].LS = dccm_ext_in_pkt_LS_3;
assign dccm_ext_in_pkt[3].DS = dccm_ext_in_pkt_DS_3;
assign dccm_ext_in_pkt[3].SD = dccm_ext_in_pkt_SD_3;
assign dccm_ext_in_pkt[3].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_3;
assign dccm_ext_in_pkt[3].BC1 = dccm_ext_in_pkt_BC1_3;
assign dccm_ext_in_pkt[3].BC2 = dccm_ext_in_pkt_BC2_3;
assign iccm_ext_in_pkt[0].TEST1 = iccm_ext_in_pkt_TEST1_0;
assign iccm_ext_in_pkt[0].RME = iccm_ext_in_pkt_RME_0;
assign iccm_ext_in_pkt[0].RM = iccm_ext_in_pkt_RM_0[3:0];
assign iccm_ext_in_pkt[0].LS = iccm_ext_in_pkt_LS_0;
assign iccm_ext_in_pkt[0].DS = iccm_ext_in_pkt_DS_0;
assign iccm_ext_in_pkt[0].SD = iccm_ext_in_pkt_SD_0;
assign iccm_ext_in_pkt[0].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_0;
assign iccm_ext_in_pkt[0].BC1 = iccm_ext_in_pkt_BC1_0;
assign iccm_ext_in_pkt[0].BC2 = iccm_ext_in_pkt_BC2_0;
assign iccm_ext_in_pkt[1].TEST1 = iccm_ext_in_pkt_TEST1_1;
assign iccm_ext_in_pkt[1].RME = iccm_ext_in_pkt_RME_1;
assign iccm_ext_in_pkt[1].RM = iccm_ext_in_pkt_RM_1[3:0];
assign iccm_ext_in_pkt[1].LS = iccm_ext_in_pkt_LS_1;
assign iccm_ext_in_pkt[1].DS = iccm_ext_in_pkt_DS_1;
assign iccm_ext_in_pkt[1].SD = iccm_ext_in_pkt_SD_1;
assign iccm_ext_in_pkt[1].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_1;
assign iccm_ext_in_pkt[1].BC1 = iccm_ext_in_pkt_BC1_1;
assign iccm_ext_in_pkt[1].BC2 = iccm_ext_in_pkt_BC2_1;
assign iccm_ext_in_pkt[2].TEST1 = iccm_ext_in_pkt_TEST1_2;
assign iccm_ext_in_pkt[2].RME = iccm_ext_in_pkt_RME_2;
assign iccm_ext_in_pkt[2].RM = iccm_ext_in_pkt_RM_2[3:0];
assign iccm_ext_in_pkt[2].LS = iccm_ext_in_pkt_LS_2;
assign iccm_ext_in_pkt[2].DS = iccm_ext_in_pkt_DS_2;
assign iccm_ext_in_pkt[2].SD = iccm_ext_in_pkt_SD_2;
assign iccm_ext_in_pkt[2].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_2;
assign iccm_ext_in_pkt[2].BC1 = iccm_ext_in_pkt_BC1_2;
assign iccm_ext_in_pkt[2].BC2 = iccm_ext_in_pkt_BC2_2;
assign iccm_ext_in_pkt[3].TEST1 = iccm_ext_in_pkt_TEST1_3;
assign iccm_ext_in_pkt[3].RME = iccm_ext_in_pkt_RME_3;
assign iccm_ext_in_pkt[3].RM = iccm_ext_in_pkt_RM_3[3:0];
assign iccm_ext_in_pkt[3].LS = iccm_ext_in_pkt_LS_3;
assign iccm_ext_in_pkt[3].DS = iccm_ext_in_pkt_DS_3;
assign iccm_ext_in_pkt[3].SD = iccm_ext_in_pkt_SD_3;
assign iccm_ext_in_pkt[3].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_3;
assign iccm_ext_in_pkt[3].BC1 = iccm_ext_in_pkt_BC1_3;
assign iccm_ext_in_pkt[3].BC2 = iccm_ext_in_pkt_BC2_3;
assign ic_tag_ext_in_pkt[0].TEST1 = ic_tag_ext_in_pkt_TEST1_0;
assign ic_tag_ext_in_pkt[0].RME = ic_tag_ext_in_pkt_RME_0;
assign ic_tag_ext_in_pkt[0].RM = ic_tag_ext_in_pkt_RM_0[3:0];
assign ic_tag_ext_in_pkt[0].LS = ic_tag_ext_in_pkt_LS_0;
assign ic_tag_ext_in_pkt[0].DS = ic_tag_ext_in_pkt_DS_0;
assign ic_tag_ext_in_pkt[0].SD = ic_tag_ext_in_pkt_SD_0;
assign ic_tag_ext_in_pkt[0].TEST_RNM = ic_tag_ext_in_pkt_TEST_RNM_0;
assign ic_tag_ext_in_pkt[0].BC1 = ic_tag_ext_in_pkt_BC1_0;
assign ic_tag_ext_in_pkt[0].BC2 = ic_tag_ext_in_pkt_BC2_0;
assign ic_tag_ext_in_pkt[1].TEST1 = ic_tag_ext_in_pkt_TEST1_1;
assign ic_tag_ext_in_pkt[1].RME = ic_tag_ext_in_pkt_RME_1;
assign ic_tag_ext_in_pkt[1].RM = ic_tag_ext_in_pkt_RM_1[3:0];
assign ic_tag_ext_in_pkt[1].LS = ic_tag_ext_in_pkt_LS_1;
assign ic_tag_ext_in_pkt[1].DS = ic_tag_ext_in_pkt_DS_1;
assign ic_tag_ext_in_pkt[1].SD = ic_tag_ext_in_pkt_SD_1;
assign ic_tag_ext_in_pkt[1].TEST_RNM = ic_tag_ext_in_pkt_TEST_RNM_1;
assign ic_tag_ext_in_pkt[1].BC1 = ic_tag_ext_in_pkt_BC1_1;
assign ic_tag_ext_in_pkt[1].BC2 = ic_tag_ext_in_pkt_BC2_1;
// PKT connection
assign ic_data_ext_in_pkt[0][0].TEST1 = ic_data_ext_in_pkt_0_TEST1_0;
assign ic_data_ext_in_pkt[0][0].RME = ic_data_ext_in_pkt_0_RME_0;
assign ic_data_ext_in_pkt[0][0].RM = ic_data_ext_in_pkt_0_RM_0[3:0];
assign ic_data_ext_in_pkt[0][0].LS = ic_data_ext_in_pkt_0_LS_0;
assign ic_data_ext_in_pkt[0][0].DS = ic_data_ext_in_pkt_0_DS_0;
assign ic_data_ext_in_pkt[0][0].SD = ic_data_ext_in_pkt_0_SD_0;
assign ic_data_ext_in_pkt[0][0].TEST_RNM = ic_data_ext_in_pkt_0_TEST_RNM_0;
assign ic_data_ext_in_pkt[0][0].BC1 = ic_data_ext_in_pkt_0_BC1_0;
assign ic_data_ext_in_pkt[0][0].BC2 = ic_data_ext_in_pkt_0_BC2_0;
assign ic_data_ext_in_pkt[0][1].TEST1 = ic_data_ext_in_pkt_1_TEST1_1;
assign ic_data_ext_in_pkt[0][1].RME = ic_data_ext_in_pkt_1_RME_1;
assign ic_data_ext_in_pkt[0][1].RM = ic_data_ext_in_pkt_1_RM_1[3:0];
assign ic_data_ext_in_pkt[0][1].LS = ic_data_ext_in_pkt_1_LS_1;
assign ic_data_ext_in_pkt[0][1].DS = ic_data_ext_in_pkt_1_DS_1;
assign ic_data_ext_in_pkt[0][1].SD = ic_data_ext_in_pkt_1_SD_1;
assign ic_data_ext_in_pkt[0][1].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_1;
assign ic_data_ext_in_pkt[0][1].BC1 = ic_data_ext_in_pkt_1_BC1_1;
assign ic_data_ext_in_pkt[0][1].BC2 = ic_data_ext_in_pkt_1_BC2_1;
assign ic_data_ext_in_pkt[1][0].TEST1 = ic_data_ext_in_pkt_1_TEST1_0;
assign ic_data_ext_in_pkt[1][0].RME = ic_data_ext_in_pkt_1_RME_0;
assign ic_data_ext_in_pkt[1][0].RM = ic_data_ext_in_pkt_1_RM_0[3:0];
assign ic_data_ext_in_pkt[1][0].LS = ic_data_ext_in_pkt_1_LS_0;
assign ic_data_ext_in_pkt[1][0].DS = ic_data_ext_in_pkt_1_DS_0;
assign ic_data_ext_in_pkt[1][0].SD = ic_data_ext_in_pkt_1_SD_0;
assign ic_data_ext_in_pkt[1][0].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_0;
assign ic_data_ext_in_pkt[1][0].BC1 = ic_data_ext_in_pkt_1_BC1_0;
assign ic_data_ext_in_pkt[1][0].BC2 = ic_data_ext_in_pkt_1_BC2_0;
assign ic_data_ext_in_pkt[1][1].TEST1 = ic_data_ext_in_pkt_1_TEST1_1;
assign ic_data_ext_in_pkt[1][1].RME = ic_data_ext_in_pkt_1_RME_1;
assign ic_data_ext_in_pkt[1][1].RM = ic_data_ext_in_pkt_1_RM_1[3:0];
assign ic_data_ext_in_pkt[1][1].LS = ic_data_ext_in_pkt_1_LS_1;
assign ic_data_ext_in_pkt[1][1].DS = ic_data_ext_in_pkt_1_DS_1;
assign ic_data_ext_in_pkt[1][1].SD = ic_data_ext_in_pkt_1_SD_1;
assign ic_data_ext_in_pkt[1][1].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_1;
assign ic_data_ext_in_pkt[1][1].BC1 = ic_data_ext_in_pkt_1_BC1_1;
assign ic_data_ext_in_pkt[1][1].BC2 = ic_data_ext_in_pkt_1_BC2_1;
wire active_clk;
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
// DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH),
.DCCM_WIDTH_BITS(DCCM_WIDTH_BITS)) dccm (
.clk_override(dccm_clk_override),
.*
);
end else begin: Gen_dccm_disable
assign dccm_rd_data_lo = '0;
assign dccm_rd_data_hi = '0;
end
if ( ICACHE_ENABLE ) begin: icache
ifu_ic_mem #(
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
.ICACHE_BANK_HI(ICACHE_BANK_HI),
.ICACHE_BANK_LO(ICACHE_BANK_LO),
.ICACHE_TAG_LO(ICACHE_TAG_LO),
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
.ICACHE_ECC(ICACHE_ECC),
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
.ICACHE_WAYPACK(ICACHE_WAYPACK),
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH),
.ICACHE_TAG_NUM_BYPASS(ICACHE_TAG_NUM_BYPASS),
.ICACHE_TAG_NUM_BYPASS_WIDTH(ICACHE_TAG_NUM_BYPASS_WIDTH),
.ICACHE_TAG_BYPASS_ENABLE(ICACHE_TAG_BYPASS_ENABLE),
.ICACHE_NUM_BYPASS_WIDTH(ICACHE_NUM_BYPASS_WIDTH),
.ICACHE_BYPASS_ENABLE(ICACHE_BYPASS_ENABLE),
.ICACHE_NUM_BYPASS(ICACHE_NUM_BYPASS),
.ICACHE_LN_SZ(ICACHE_LN_SZ)) icm (
.clk_override(icm_clk_override),
.*
);
end
else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ic_tag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE )
if (ICCM_ENABLE) begin : iccm
ifu_iccm_mem #(
.ICCM_BITS(ICCM_BITS),
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
.ICCM_BANK_HI(ICCM_BANK_HI),
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
.clk_override(icm_clk_override),
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
.iccm_rd_data(iccm_rd_data[63:0])
);
end
else begin
assign iccm_rd_data = '0 ;
assign iccm_rd_data_ecc = '0 ;
end
endmodule

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design/src/main/resources/vsrc/mem_lib.sv Normal file
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// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`define EL2_LOCAL_RAM_TEST_IO \
input logic WE, \
input logic ME, \
input logic CLK, \
input logic TEST1, \
input logic RME, \
input logic [3:0] RM, \
input logic LS, \
input logic DS, \
input logic SD, \
input logic TEST_RNM, \
input logic BC1, \
input logic BC2, \
output logic ROP
`define EL2_RAM(depth, width) \
module ram_``depth``x``width( \
input logic [$clog2(depth)-1:0] ADR, \
input logic [(width-1):0] D, \
output logic [(width-1):0] Q, \
`EL2_LOCAL_RAM_TEST_IO \
); \
reg [(width-1):0] ram_core [(depth-1):0]; \
`ifdef GTLSIM \
integer i; \
initial begin \
for (i=0; i<depth; i=i+1) \
ram_core[i] = '0; \
end \
`endif \
always @(posedge CLK) begin \
`ifdef GTLSIM \
if (ME && WE) ram_core[ADR] <= D; \
`else \
if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end \
`endif \
if (ME && ~WE) Q <= ram_core[ADR]; \
end \
assign ROP = ME; \
\
endmodule
`define EL2_RAM_BE(depth, width) \
module ram_be_``depth``x``width( \
input logic [$clog2(depth)-1:0] ADR, \
input logic [(width-1):0] D, WEM, \
output logic [(width-1):0] Q, \
`EL2_LOCAL_RAM_TEST_IO \
); \
reg [(width-1):0] ram_core [(depth-1):0]; \
`ifdef GTLSIM \
integer i; \
initial begin \
for (i=0; i<depth; i=i+1) \
ram_core[i] = '0; \
end \
`endif \
always @(posedge CLK) begin \
`ifdef GTLSIM \
if (ME && WE) ram_core[ADR] <= D & WEM | ~WEM & ram_core[ADR]; \
`else \
if (ME && WE) begin ram_core[ADR] <= D & WEM | ~WEM & ram_core[ADR]; Q <= 'x; end \
`endif \
if (ME && ~WE) Q <= ram_core[ADR]; \
end \
assign ROP = ME; \
\
endmodule
// parameterizable RAM for verilator sims
module el2_ram #(depth=4096, width=39) (
input logic [$clog2(depth)-1:0] ADR,
input logic [(width-1):0] D,
output logic [(width-1):0] Q,
`EL2_LOCAL_RAM_TEST_IO
);
reg [(width-1):0] ram_core [(depth-1):0];
always @(posedge CLK) begin
`ifdef GTLSIM
if (ME && WE) ram_core[ADR] <= D;
`else
if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end
`endif
if (ME && ~WE) Q <= ram_core[ADR];
end
endmodule
//=========================================================================================================================
//=================================== START OF CCM =======================================================================
//============= Possible sram sizes for a 39 bit wide memory ( 4 bytes + 7 bits ECC ) =====================================
//-------------------------------------------------------------------------------------------------------------------------
`EL2_RAM(32768, 39)
`EL2_RAM(16384, 39)
`EL2_RAM(8192, 39)
`EL2_RAM(4096, 39)
`EL2_RAM(3072, 39)
`EL2_RAM(2048, 39)
`EL2_RAM(1536, 39) // need this for the 48KB DCCM option)
`EL2_RAM(1024, 39)
`EL2_RAM(768, 39)
`EL2_RAM(512, 39)
`EL2_RAM(256, 39)
`EL2_RAM(128, 39)
`EL2_RAM(1024, 20)
`EL2_RAM(512, 20)
`EL2_RAM(256, 20)
`EL2_RAM(128, 20)
`EL2_RAM(64, 20)
`EL2_RAM(4096, 34)
`EL2_RAM(2048, 34)
`EL2_RAM(1024, 34)
`EL2_RAM(512, 34)
`EL2_RAM(256, 34)
`EL2_RAM(128, 34)
`EL2_RAM(64, 34)
`EL2_RAM(8192, 68)
`EL2_RAM(4096, 68)
`EL2_RAM(2048, 68)
`EL2_RAM(1024, 68)
`EL2_RAM(512, 68)
`EL2_RAM(256, 68)
`EL2_RAM(128, 68)
`EL2_RAM(64, 68)
`EL2_RAM(8192, 71)
`EL2_RAM(4096, 71)
`EL2_RAM(2048, 71)
`EL2_RAM(1024, 71)
`EL2_RAM(512, 71)
`EL2_RAM(256, 71)
`EL2_RAM(128, 71)
`EL2_RAM(64, 71)
`EL2_RAM(4096, 42)
`EL2_RAM(2048, 42)
`EL2_RAM(1024, 42)
`EL2_RAM(512, 42)
`EL2_RAM(256, 42)
`EL2_RAM(128, 42)
`EL2_RAM(64, 42)
`EL2_RAM(4096, 22)
`EL2_RAM(2048, 22)
`EL2_RAM(1024, 22)
`EL2_RAM(512, 22)
`EL2_RAM(256, 22)
`EL2_RAM(128, 22)
`EL2_RAM(64, 22)
`EL2_RAM(1024, 26)
`EL2_RAM(4096, 26)
`EL2_RAM(2048, 26)
`EL2_RAM(512, 26)
`EL2_RAM(256, 26)
`EL2_RAM(128, 26)
`EL2_RAM(64, 26)
`EL2_RAM(32, 26)
`EL2_RAM(32, 22)
`EL2_RAM_BE(8192, 142)
`EL2_RAM_BE(4096, 142)
`EL2_RAM_BE(2048, 142)
`EL2_RAM_BE(1024, 142)
`EL2_RAM_BE(512, 142)
`EL2_RAM_BE(256, 142)
`EL2_RAM_BE(128, 142)
`EL2_RAM_BE(64, 142)
`EL2_RAM_BE(8192, 284)
`EL2_RAM_BE(4096, 284)
`EL2_RAM_BE(2048, 284)
`EL2_RAM_BE(1024, 284)
`EL2_RAM_BE(512, 284)
`EL2_RAM_BE(256, 284)
`EL2_RAM_BE(128, 284)
`EL2_RAM_BE(64, 284)
`EL2_RAM_BE(8192, 136)
`EL2_RAM_BE(4096, 136)
`EL2_RAM_BE(2048, 136)
`EL2_RAM_BE(1024, 136)
`EL2_RAM_BE(512, 136)
`EL2_RAM_BE(256, 136)
`EL2_RAM_BE(128, 136)
`EL2_RAM_BE(64, 136)
`EL2_RAM_BE(8192, 272)
`EL2_RAM_BE(4096, 272)
`EL2_RAM_BE(2048, 272)
`EL2_RAM_BE(1024, 272)
`EL2_RAM_BE(512, 272)
`EL2_RAM_BE(256, 272)
`EL2_RAM_BE(128, 272)
`EL2_RAM_BE(64, 272)
`EL2_RAM_BE(4096, 52)
`EL2_RAM_BE(2048, 52)
`EL2_RAM_BE(1024, 52)
`EL2_RAM_BE(512, 52)
`EL2_RAM_BE(256, 52)
`EL2_RAM_BE(128, 52)
`EL2_RAM_BE(64, 52)
`EL2_RAM_BE(32, 52)
`EL2_RAM_BE(4096, 104)
`EL2_RAM_BE(2048, 104)
`EL2_RAM_BE(1024, 104)
`EL2_RAM_BE(512, 104)
`EL2_RAM_BE(256, 104)
`EL2_RAM_BE(128, 104)
`EL2_RAM_BE(64, 104)
`EL2_RAM_BE(32, 104)
`EL2_RAM_BE(4096, 44)
`EL2_RAM_BE(2048, 44)
`EL2_RAM_BE(1024, 44)
`EL2_RAM_BE(512, 44)
`EL2_RAM_BE(256, 44)
`EL2_RAM_BE(128, 44)
`EL2_RAM_BE(64, 44)
`EL2_RAM_BE(32, 44)
`EL2_RAM_BE(4096, 88)
`EL2_RAM_BE(2048, 88)
`EL2_RAM_BE(1024, 88)
`EL2_RAM_BE(512, 88)
`EL2_RAM_BE(256, 88)
`EL2_RAM_BE(128, 88)
`EL2_RAM_BE(64, 88)
`EL2_RAM_BE(32, 88)
`EL2_RAM(64, 39)
`undef EL2_RAM
`undef EL2_RAM_BE
`undef EL2_LOCAL_RAM_TEST_IO

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#(parameter AWIDTH = 7,
TAG = 1'h1,
BHT_ADDR_HI = 4'h9,
BHT_ADDR_LO = 2'h2,
BHT_ARRAY_DEPTH = 11'h100,
BHT_GHR_HASH_1 = 1'h0,
BHT_GHR_SIZE = 4'h8,
BHT_SIZE = 12'h200,
BTB_ADDR_HI = 5'h09,
BTB_ADDR_LO = 2'h2,
BTB_ARRAY_DEPTH = 9'h100,
BTB_BTAG_FOLD = 1'h0,
BTB_BTAG_SIZE = 4'h5,
BTB_FOLD2_INDEX_HASH = 1'h0,
BTB_INDEX1_HI = 5'h09,
BTB_INDEX1_LO = 5'h02,
BTB_INDEX2_HI = 5'h11,
BTB_INDEX2_LO = 5'h0A,
BTB_INDEX3_HI = 5'h19,
BTB_INDEX3_LO = 5'h12,
BTB_SIZE = 10'h200,
BUILD_AHB_LITE = 1'h0,
BUILD_AXI4 = 1'h1,
BUILD_AXI_NATIVE = 1'h1,
BUS_PRTY_DEFAULT = 2'h3,
DATA_ACCESS_ADDR0 = 32'h00000000,
DATA_ACCESS_ADDR1 = 32'h00000000,
DATA_ACCESS_ADDR2 = 32'h00000000,
DATA_ACCESS_ADDR3 = 32'h00000000,
DATA_ACCESS_ADDR4 = 32'h00000000,
DATA_ACCESS_ADDR5 = 32'h00000000,
DATA_ACCESS_ADDR6 = 32'h00000000,
DATA_ACCESS_ADDR7 = 32'h00000000,
DATA_ACCESS_ENABLE0 = 1'h0,
DATA_ACCESS_ENABLE1 = 1'h0,
DATA_ACCESS_ENABLE2 = 1'h0,
DATA_ACCESS_ENABLE3 = 1'h0,
DATA_ACCESS_ENABLE4 = 1'h0,
DATA_ACCESS_ENABLE5 = 1'h0,
DATA_ACCESS_ENABLE6 = 1'h0,
DATA_ACCESS_ENABLE7 = 1'h0,
DATA_ACCESS_MASK0 = 32'h0FFFFFFF,
DATA_ACCESS_MASK1 = 32'h0FFFFFFF,
DATA_ACCESS_MASK2 = 32'h0FFFFFFF,
DATA_ACCESS_MASK3 = 32'h0FFFFFFF,
DATA_ACCESS_MASK4 = 32'h0FFFFFFF,
DATA_ACCESS_MASK5 = 32'h0FFFFFFF,
DATA_ACCESS_MASK6 = 32'h0FFFFFFF,
DATA_ACCESS_MASK7 = 32'h0FFFFFFF,
DCCM_BANK_BITS = 3'h2,
DCCM_BITS = 5'h10,
DCCM_BYTE_WIDTH = 3'h4,
DCCM_DATA_WIDTH = 6'h20,
DCCM_ECC_WIDTH = 3'h7,
DCCM_ENABLE = 1'h1,
DCCM_FDATA_WIDTH = 6'h27,
//DCCM_INDEX_BITS = 4'hC,
DCCM_NUM_BANKS = 5'h04,
DCCM_REGION = 4'hF,
DCCM_SADR = 32'hF0040000,
DCCM_SIZE = 10'h040,
//DCCM_WIDTH_BITS = 2'h2,
DMA_BUF_DEPTH = 3'h5,
DMA_BUS_ID = 1'h1,
DMA_BUS_PRTY = 2'h2,
DMA_BUS_TAG = 4'h1,
FAST_INTERRUPT_REDIRECT = 1'h1,
ICACHE_2BANKS = 1'h1,
ICACHE_BANK_BITS = 3'h1,
ICACHE_BANK_HI = 3'h3,
ICACHE_BANK_LO = 2'h3,
ICACHE_BANK_WIDTH = 4'h8,
ICACHE_BANKS_WAY = 3'h2,
ICACHE_BEAT_ADDR_HI = 4'h5,
ICACHE_BEAT_BITS = 4'h3,
ICACHE_DATA_DEPTH = 14'h0200,
ICACHE_DATA_INDEX_LO = 3'h4,
ICACHE_DATA_WIDTH = 7'h40,
ICACHE_ECC = 1'h1,
ICACHE_ENABLE = 1'h1,
ICACHE_FDATA_WIDTH = 7'h47,
ICACHE_INDEX_HI = 5'h0C,
ICACHE_LN_SZ = 7'h40,
ICACHE_NUM_BEATS = 4'h8,
ICACHE_NUM_WAYS = 3'h2,
ICACHE_ONLY = 1'h0,
ICACHE_SCND_LAST = 4'h6,
ICACHE_SIZE = 9'h010,
ICACHE_STATUS_BITS = 3'h1,
ICACHE_TAG_DEPTH = 13'h0080,
ICACHE_TAG_INDEX_LO = 3'h6,
ICACHE_TAG_LO = 5'h0D,
ICACHE_WAYPACK = 1'h0,
ICCM_BANK_BITS = 3'h2,
ICCM_BANK_HI = 5'h03,
ICCM_BANK_INDEX_LO = 5'h04,
ICCM_BITS = 5'h10,
ICCM_ENABLE = 1'h1,
ICCM_ICACHE = 1'h1,
ICCM_INDEX_BITS = 4'hC,
ICCM_NUM_BANKS = 5'h04,
ICCM_ONLY = 1'h0,
ICCM_REGION = 4'hE,
ICCM_SADR = 32'hEE000000,
ICCM_SIZE = 10'h040,
IFU_BUS_ID = 1'h1,
IFU_BUS_PRTY = 2'h2,
IFU_BUS_TAG = 4'h3,
INST_ACCESS_ADDR0 = 32'h00000000,
INST_ACCESS_ADDR1 = 32'h00000000,
INST_ACCESS_ADDR2 = 32'h00000000,
INST_ACCESS_ADDR3 = 32'h00000000,
INST_ACCESS_ADDR4 = 32'h00000000,
INST_ACCESS_ADDR5 = 32'h00000000,
INST_ACCESS_ADDR6 = 32'h00000000,
INST_ACCESS_ADDR7 = 32'h00000000,
INST_ACCESS_ENABLE0 = 1'h0,
INST_ACCESS_ENABLE1 = 1'h0,
INST_ACCESS_ENABLE2 = 1'h0,
INST_ACCESS_ENABLE3 = 1'h0,
INST_ACCESS_ENABLE4 = 1'h0,
INST_ACCESS_ENABLE5 = 1'h0,
INST_ACCESS_ENABLE6 = 1'h0,
INST_ACCESS_ENABLE7 = 1'h0,
INST_ACCESS_MASK0 = 32'h0FFFFFFF,
INST_ACCESS_MASK1 = 32'h0FFFFFFF,
INST_ACCESS_MASK2 = 32'h0FFFFFFF,
INST_ACCESS_MASK3 = 32'h0FFFFFFF,
INST_ACCESS_MASK4 = 32'h0FFFFFFF,
INST_ACCESS_MASK5 = 32'h0FFFFFFF,
INST_ACCESS_MASK6 = 32'h0FFFFFFF,
INST_ACCESS_MASK7 = 32'h0FFFFFFF,
LOAD_TO_USE_PLUS1 = 1'h0,
LSU2DMA = 1'h0,
LSU_BUS_ID = 1'h1,
LSU_BUS_PRTY = 2'h2,
LSU_BUS_TAG = 4'h3,
LSU_NUM_NBLOAD = 5'h04,
LSU_NUM_NBLOAD_WIDTH = 3'h2,
LSU_SB_BITS = 5'h10,
LSU_STBUF_DEPTH = 4'h4,
NO_ICCM_NO_ICACHE = 1'h0,
PIC_2CYCLE = 1'h0,
PIC_BASE_ADDR = 32'hF00C0000,
PIC_BITS = 5'h0F,
PIC_INT_WORDS = 4'h1,
PIC_REGION = 4'hF,
PIC_SIZE = 9'h020,
PIC_TOTAL_INT = 8'h1F,
PIC_TOTAL_INT_PLUS1 = 9'h020,
RET_STACK_SIZE = 4'h8,
SB_BUS_ID = 1'h1,
SB_BUS_PRTY = 2'h2,
SB_BUS_TAG = 4'h1,
TIMER_LEGAL_EN = 1'h1,
RV_FPGA_OPTIMIZE = 5'h01,
DIV_NEW = 5'h01,
DIV_BIT = 7'h04,
BTB_ENABLE = 5'h01,
BTB_TOFFSET_SIZE = 9'h00C,
BTB_FULLYA = 5'h00,
BITMANIP_ZBA = 5'h00 ,
BITMANIP_ZBB = 5'h01 ,
BITMANIP_ZBC = 5'h00 ,
BITMANIP_ZBE = 5'h00 ,
BITMANIP_ZBF = 5'h00 ,
BITMANIP_ZBP = 5'h00 ,
BITMANIP_ZBR = 5'h00 ,
BITMANIP_ZBS = 5'h01 ,
ICACHE_BYPASS_ENABLE = 5'h01,
ICACHE_NUM_BYPASS = 8'h02,
ICACHE_NUM_BYPASS_WIDTH = 8'h02,
ICACHE_TAG_BYPASS_ENABLE = 5'h01,
ICACHE_TAG_NUM_BYPASS = 8'h02,
ICACHE_TAG_NUM_BYPASS_WIDTH = 8'h02
)

223
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// SPDX-License-Identifier: Apache-2.0
// Copyright 2019 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License
module rvjtag_tap #(
parameter AWIDTH = 7
)
(
input trst,
input tck,
input tms,
input tdi,
output reg tdo,
output tdoEnable,
output [31:0] wr_data,
output [AWIDTH-1:0] wr_addr,
output wr_en,
output rd_en,
input [31:0] rd_data,
input [1:0] rd_status,
output reg dmi_reset,
output reg dmi_hard_reset,
input [2:0] idle,
input [1:0] dmi_stat,
/*
-- revisionCode : 4'h0;
-- manufacturersIdCode : 11'h45;
-- deviceIdCode : 16'h0001;
-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB]
*/
input [31:1] jtag_id,
input [3:0] version
);
localparam USER_DR_LENGTH = AWIDTH + 34;
reg [USER_DR_LENGTH-1:0] sr, nsr, dr;
///////////////////////////////////////////////////////
// Tap controller
///////////////////////////////////////////////////////
logic[3:0] state, nstate;
logic [4:0] ir;
wire jtag_reset;
wire shift_dr;
wire pause_dr;
wire update_dr;
wire capture_dr;
wire shift_ir;
wire pause_ir ;
wire update_ir ;
wire capture_ir;
wire[1:0] dr_en;
wire devid_sel;
wire [5:0] abits;
assign abits = AWIDTH[5:0];
localparam TEST_LOGIC_RESET_STATE = 0;
localparam RUN_TEST_IDLE_STATE = 1;
localparam SELECT_DR_SCAN_STATE = 2;
localparam CAPTURE_DR_STATE = 3;
localparam SHIFT_DR_STATE = 4;
localparam EXIT1_DR_STATE = 5;
localparam PAUSE_DR_STATE = 6;
localparam EXIT2_DR_STATE = 7;
localparam UPDATE_DR_STATE = 8;
localparam SELECT_IR_SCAN_STATE = 9;
localparam CAPTURE_IR_STATE = 10;
localparam SHIFT_IR_STATE = 11;
localparam EXIT1_IR_STATE = 12;
localparam PAUSE_IR_STATE = 13;
localparam EXIT2_IR_STATE = 14;
localparam UPDATE_IR_STATE = 15;
always_comb begin
nstate = state;
case(state)
TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE;
RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE;
CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;
SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;
EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE;
PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE;
EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE;
UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE;
CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE;
PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE;
EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE;
UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
default: nstate = TEST_LOGIC_RESET_STATE;
endcase
end
always @ (posedge tck or negedge trst) begin
if(!trst) state <= TEST_LOGIC_RESET_STATE;
else state <= nstate;
end
assign jtag_reset = state == TEST_LOGIC_RESET_STATE;
assign shift_dr = state == SHIFT_DR_STATE;
assign pause_dr = state == PAUSE_DR_STATE;
assign update_dr = state == UPDATE_DR_STATE;
assign capture_dr = state == CAPTURE_DR_STATE;
assign shift_ir = state == SHIFT_IR_STATE;
assign pause_ir = state == PAUSE_IR_STATE;
assign update_ir = state == UPDATE_IR_STATE;
assign capture_ir = state == CAPTURE_IR_STATE;
assign tdoEnable = shift_dr | shift_ir;
///////////////////////////////////////////////////////
// IR register
///////////////////////////////////////////////////////
always @ (negedge tck or negedge trst) begin
if (!trst) ir <= 5'b1;
else begin
if (jtag_reset) ir <= 5'b1;
else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];
end
end
assign devid_sel = ir == 5'b00001;
assign dr_en[0] = ir == 5'b10000;
assign dr_en[1] = ir == 5'b10001;
///////////////////////////////////////////////////////
// Shift register
///////////////////////////////////////////////////////
always @ (posedge tck or negedge trst) begin
if(!trst)begin
sr <= '0;
end
else begin
sr <= nsr;
end
end
// SR next value
always_comb begin
nsr = sr;
case(1)
shift_dr: begin
case(1)
dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]};
dr_en[0],
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]};
default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass
endcase
end
capture_dr: begin
case(1)
dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};
dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1};
endcase
end
shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};
endcase
end
// TDO retiming
always @ (negedge tck ) tdo <= sr[0];
// DMI CS register
always @ (posedge tck or negedge trst) begin
if(!trst) begin
dmi_hard_reset <= 1'b0;
dmi_reset <= 1'b0;
end
else if (update_dr & dr_en[0]) begin
dmi_hard_reset <= sr[17];
dmi_reset <= sr[16];
end
else begin
dmi_hard_reset <= 1'b0;
dmi_reset <= 1'b0;
end
end
// DR register
always @ (posedge tck or negedge trst) begin
if(!trst)
dr <= '0;
else begin
if (update_dr & dr_en[1])
dr <= sr;
else
dr <= {dr[USER_DR_LENGTH-1:2],2'b0};
end
end
assign {wr_addr, wr_data, wr_en, rd_en} = dr;
endmodule

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{
"files.watcherExclude": {
"**/target": true
}
}

564
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package dbg
import chisel3._
import chisel3.util._
import lib._
import include._
object state_t {
val idle = 0.U(4.W)
val halting = 1.U(4.W)
val halted = 2.U(4.W)
val core_cmd_start = 3.U(4.W)
val core_cmd_wait = 4.U(4.W)
val sb_cmd_start = 5.U(4.W)
val sb_cmd_send = 6.U(4.W)
val sb_cmd_resp = 7.U(4.W)
val cmd_done = 8.U(4.W)
val resuming = 9.U(4.W)
}
object sb_state_t {
val sbidle = 0.U(4.W)
val wait_rd = 1.U(4.W)
val wait_wr = 2.U(4.W)
val cmd_rd = 3.U(4.W)
val cmd_wr = 4.U(4.W)
val cmd_wr_addr = 5.U(4.W)
val cmd_wr_data = 6.U(4.W)
val rsp_rd = 7.U(4.W)
val rsp_wr = 8.U(4.W)
val done = 9.U(4.W)
}
class dbg extends Module with lib with RequireAsyncReset {
val io = IO(new Bundle {
val dbg_cmd_size = Output(UInt(2.W))
val dbg_core_rst_l = Output(Bool())
val core_dbg_rddata = Input(UInt(32.W))
val core_dbg_cmd_done = Input(Bool())
val core_dbg_cmd_fail = Input(Bool())
val dbg_halt_req = Output(Bool())
val dbg_resume_req = Output(Bool())
val dec_tlu_debug_mode = Input(Bool())
val dec_tlu_dbg_halted = Input(Bool())
val dec_tlu_mpc_halted_only = Input(Bool())
val dec_tlu_resume_ack = Input(Bool())
val dmi_reg_en = Input(Bool())
val dmi_reg_addr = Input(UInt(7.W))
val dmi_reg_wr_en = Input(Bool())
val dmi_reg_wdata = Input(UInt(32.W))
val dmi_reg_rdata = Output(UInt(32.W))
val sb_axi = new axi_channels(SB_BUS_TAG)
val dbg_dec_dma = Flipped(new dec_dbg)
val dbg_dma = Flipped(new dbg_dma)
val dbg_bus_clk_en = Input(Bool())
val dbg_rst_l = Input(AsyncReset())
val clk_override = Input(Bool())
val scan_mode = Input(Bool())
})
val dbg_state = WireInit(state_t.idle)
val dbg_state_en = WireInit(false.B)
val sb_state = WireInit(sb_state_t.sbidle)
val sb_state_en = WireInit(Bool(), false.B)
val dmcontrol_reg = WireInit(0.U(32.W))
val sbaddress0_reg = WireInit(0.U(32.W))
val sbcs_sbbusy_wren = WireInit(false.B)
val sbcs_sberror_wren = WireInit(false.B)
val sb_bus_rdata = WireInit(0.U(64.W))
val sbaddress0_reg_wren1 = WireInit(false.B)
val dmstatus_reg = WireInit(0.U(32.W))
val dmstatus_havereset = WireInit(false.B)
val dmstatus_haveresetn = WireInit(false.B)
val dmstatus_resumeack = WireInit(false.B)
val dmstatus_unavail = WireInit(false.B)
val dmstatus_running = WireInit(false.B)
val dmstatus_halted = WireInit(false.B)
val abstractcs_busy_wren = WireInit(false.B)
val abstractcs_busy_din = WireInit(false.B)
val sb_bus_cmd_read = WireInit(false.B)
val sb_bus_cmd_write_addr = WireInit(false.B)
val sb_bus_cmd_write_data = WireInit(false.B)
val sb_bus_rsp_read = WireInit(false.B)
val sb_bus_rsp_error = WireInit(false.B)
val sb_bus_rsp_write = WireInit(false.B)
val sbcs_sbbusy_din = WireInit(false.B)
val sbcs_sberror_din = WireInit(0.U(3.W))
val data1_reg = WireInit(0.U(32.W))
val sbcs_reg = WireInit(0.U(32.W))
val execute_command = WireInit(false.B)
val command_reg = WireInit(0.U(32.W))
val dbg_sb_bus_error = WireInit(false.B)
val command_wren = WireInit(false.B)
val command_din = WireInit(0.U(32.W))
val dbg_cmd_next_addr = WireInit(0.U(32.W))
val data0_reg_wren2 = WireInit(false.B)
val sb_abmem_cmd_done_in = WireInit(false.B)
val sb_abmem_data_done_in = WireInit(false.B)
val sb_abmem_cmd_done_en = WireInit(false.B)
val sb_abmem_data_done_en = WireInit(false.B)
val abmem_addr_external = WireInit(false.B)
val sb_cmd_pending = WireInit(false.B)
val sb_abmem_cmd_write = WireInit(false.B)
val abmem_addr_in_dccm_region = WireInit(false.B)
val abmem_addr_in_iccm_region = WireInit(false.B)
val abmem_addr_in_pic_region = WireInit(false.B)
val sb_abmem_cmd_size = WireInit(0.U(4.W))
val abstractcs_error_din = WireInit(0.U(3.W))
val dmcontrol_wren_Q = WireInit(false.B)
val abstractcs_reg = WireInit(2.U(32.W))
val dbg_free_clken = io.dmi_reg_en | execute_command | (dbg_state =/= state_t.idle) | dbg_state_en | io.dec_tlu_dbg_halted |
io.dec_tlu_mpc_halted_only | io.dec_tlu_debug_mode | io.dbg_halt_req | io.clk_override
val sb_free_clken = io.dmi_reg_en | execute_command | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override;
val dbg_free_clk = rvoclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc
val sb_free_clk = rvoclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc
val dbg_dm_rst_l = (io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)).asAsyncReset()
io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool() | io.scan_mode
val sbcs_wren = (io.dmi_reg_addr === "h38".U(7.W)) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle)
val sbcs_sbbusyerror_wren = (sbcs_wren & io.dmi_reg_wdata(22)) | (sbcs_reg(21) & io.dmi_reg_en & ((io.dmi_reg_wr_en &
(io.dmi_reg_addr === "h39".U(7.W))) | (io.dmi_reg_addr === "h3c".U(7.W)) |
(io.dmi_reg_addr === "h3d".U(7.W))))
val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt()
val temp_sbcs_22 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren)} // sbcs_sbbusyerror_reg
val temp_sbcs_21 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren)} // sbcs_sbbusy_reg
val temp_sbcs_20 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren)} // sbcs_sbreadonaddr_reg
val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(Cat(io.dmi_reg_wdata(19), ~io.dmi_reg_wdata(18), io.dmi_reg_wdata(17, 15)), 0.U, sbcs_wren)} // sbcs_misc_reg
val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren)} // sbcs_error_reg
sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15(4), ~temp_sbcs_19_15(3),
temp_sbcs_19_15(2,0), temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W))
val sbcs_unaligned = (sbcs_reg(19, 17) === 1.U(3.W)) & sbaddress0_reg(0) |
(sbcs_reg(19, 17) === 2.U(3.W)) & sbaddress0_reg(1, 0).orR |
(sbcs_reg(19, 17) === 3.U(3.W)) & sbaddress0_reg(2, 0).orR
val sbcs_illegal_size = sbcs_reg(19)
val sbaddress0_incr = Fill(4, (sbcs_reg(19, 17) === 0.U(3.W))) & 1.U(4.W) | Fill(4, (sbcs_reg(19, 17) === 1.U(3.W))) & 2.U(4.W) |
Fill(4, (sbcs_reg(19, 17) === 2.U(3.W))) & 4.U(4.W) | Fill(4, (sbcs_reg(19, 17) === 3.U(3.W))) & 8.U(4.W)
val sbdata0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U)
val sbdata0_reg_wren1 = (sb_state === sb_state_t.rsp_rd) & sb_state_en & !sbcs_sberror_wren
val sbdata0_reg_wren = sbdata0_reg_wren0 | sbdata0_reg_wren1
val sbdata1_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3d".U)
val sbdata1_reg_wren1 = (sb_state === sb_state_t.rsp_rd) & sb_state_en & !sbcs_sberror_wren
val sbdata1_reg_wren = sbdata1_reg_wren0 | sbdata1_reg_wren1
val sbdata0_din = Fill(32, sbdata0_reg_wren0) & io.dmi_reg_wdata | Fill(32, sbdata0_reg_wren1) & sb_bus_rdata(31, 0)
val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata | Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32)
val sbdata0_reg = withReset(dbg_dm_rst_l) { rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode)} // dbg_sbdata0_reg
val sbdata1_reg = withReset(dbg_dm_rst_l) { rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode)} // dbg_sbdata1_reg
val sbaddress0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h39".U)
val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1
val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata |
Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr))
sbaddress0_reg := withReset(dbg_dm_rst_l) { rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode)} // dbg_sbaddress0_reg
val sbreadonaddr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h39".U) & sbcs_reg(20)
val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15)
val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U)
val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en
val resumereq = (dmcontrol_reg(30) & !dmcontrol_reg(31) & dmcontrol_wren_Q).asBool()
val dm_temp = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)),0.U, dmcontrol_wren)} // dmcontrolff
val dm_temp_0 = withClockAndReset(dbg_free_clk, io.dbg_rst_l) {
RegEnable(io.dmi_reg_wdata(0), 0.U, dmcontrol_wren)} // dmcontrol_dmactive_ff
val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0)
dmcontrol_reg := temp
dmcontrol_wren_Q := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(dmcontrol_wren, 0.U)} // dmcontrol_wrenff
dmstatus_reg := Cat(0.U(12.W), Fill(2, dmstatus_havereset), Fill(2, dmstatus_resumeack), 0.U(2.W), Fill(2, dmstatus_unavail),
Fill(2, dmstatus_running), Fill(2, dmstatus_halted), 1.U(1.W), 0.U(3.W), 2.U(4.W))
val dmstatus_resumeack_wren = (dbg_state === state_t.resuming) & io.dec_tlu_resume_ack | dmstatus_resumeack & resumereq & dmstatus_halted
val dmstatus_resumeack_din = (dbg_state === state_t.resuming) & io.dec_tlu_resume_ack
val dmstatus_haveresetn_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_wdata(28) & io.dmi_reg_en & io.dmi_reg_wr_en & dmcontrol_reg(0)
dmstatus_havereset := ~dmstatus_haveresetn
val temp_rst = reset.asBool()
dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool()
dmstatus_running := ~(dmstatus_unavail | dmstatus_halted)
dmstatus_resumeack := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren.asBool())} // dmstatus_resumeack_reg
dmstatus_halted := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U)} // dmstatus_halted_reg
dmstatus_haveresetn := withClock(dbg_free_clk) {
RegEnable(true.B, 0.U, dmstatus_haveresetn_wren)} // dmstatus_haveresetn_reg
val haltsum0_reg = Cat(0.U(31.W), dmstatus_halted)
val abstractcs_error_sel0 = abstractcs_reg(12) & ~(abstractcs_reg(10,8).orR) & io.dmi_reg_en & ((io.dmi_reg_wr_en & ((io.dmi_reg_addr === "h16".U(7.W)) |
(io.dmi_reg_addr === "h17".U(7.W))) | (io.dmi_reg_addr === "h18".U(7.W))) | (io.dmi_reg_addr === 4.U(7.W)) |
(io.dmi_reg_addr === 5.U(7.W)))
val abstractcs_error_sel1 = execute_command & ~(abstractcs_reg(10,8).orR) &
((!((command_reg(31,24) === 0.U(8.W)) | (command_reg(31,24) === 2.U(8.W)))) | // Illegal command
(((command_reg(22,20) === 3.U(3.W)) | (command_reg(22))) & (command_reg(31,24) === 2.U(8.W))) | // Illegal abstract memory size (can't be DW or higher)
((command_reg(22,20) =/= 2.U(3.W)) & ((command_reg(31,24) === 0.U(8.W)) & command_reg(17))) | // Illegal abstract reg size
((command_reg(31,24) === 0.U(8.W)) & command_reg(18))) // postexec for abstract register access
val abstractcs_error_sel2 = ((io.core_dbg_cmd_done & io.core_dbg_cmd_fail) | // exception from core
(execute_command & (command_reg(31,24) === 0.U(8.W)) & // unimplemented regs
(((command_reg(15,12) === 1.U(4.W)) & (command_reg(11,5) =/= 0.U(7.W))) | (command_reg(15,13) =/= 0.U(3.W))))) & ~(abstractcs_reg(10,8).orR)
val abstractcs_error_sel3 = execute_command & (dbg_state =/= state_t.halted) & ~(abstractcs_reg(10,8).orR)
val abstractcs_error_sel4 = dbg_sb_bus_error & io.dbg_bus_clk_en & ~(abstractcs_reg(10,8).orR) // sb bus error for abstract memory command
val abstractcs_error_sel5 = execute_command & (command_reg(31,24) === 2.U(8.W)) & ~(abstractcs_reg(10,8).orR) &
(((command_reg(22,20) === 1.U(3.W)) & data1_reg(0)) | ((command_reg(22,20) === 2.U(3.W)) & (data1_reg(1,0).orR))) //Unaligned address for abstract memory
val abstractcs_error_sel6 = (io.dmi_reg_addr === "h16".U(7.W)) & io.dmi_reg_en & io.dmi_reg_wr_en
abstractcs_error_din := MuxCase(abstractcs_reg(10,8), Array(
abstractcs_error_sel0 -> 1.U(3.W),
abstractcs_error_sel1 -> 2.U(3.W),
abstractcs_error_sel2 -> 3.U(3.W),
abstractcs_error_sel3 -> 4.U(3.W),
abstractcs_error_sel4 -> 5.U(3.W),
abstractcs_error_sel5 -> 7.U(3.W),
abstractcs_error_sel6 -> (~io.dmi_reg_wdata(10,8) & abstractcs_reg(10,8))
))
val abs_temp_12 = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren)} // dmabstractcs_busy_reg
val abs_temp_10_8 = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(abstractcs_error_din, 0.U)} // dmabstractcs_error_reg
abstractcs_reg := Cat(0.U(19.W), abs_temp_12, 0.U(1.W), abs_temp_10_8, 2.U(8.W))
val abstractauto_reg_wren = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h18".U(7.W)) & !abstractcs_reg(12)
val abstractauto_reg = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(io.dmi_reg_wdata(1,0), 0.U, abstractauto_reg_wren)} // dbg_abstractauto_reg
val execute_command_ns = command_wren | (io.dmi_reg_en & !abstractcs_reg(12) & (((io.dmi_reg_addr === 4.U(7.W)) &
abstractauto_reg(0)) | ((io.dmi_reg_addr === 5.U(7.W)) & abstractauto_reg(1))))
command_wren := (io.dmi_reg_addr === "h17".U(7.W)) & io.dmi_reg_en & io.dmi_reg_wr_en
val command_regno_wren = command_wren | ((command_reg(31,24) === 0.U(8.W)) & command_reg(19) & (dbg_state === state_t.cmd_done) &
~(abstractcs_reg(10,8).orR)) // aarpostincrement
val command_postexec_din = (io.dmi_reg_wdata(31,24) === 0.U(8.W)) & io.dmi_reg_wdata(18)
val command_transfer_din = (io.dmi_reg_wdata(31,24) === 0.U(8.W)) & io.dmi_reg_wdata(17)
val temp_command_din_31_16 = Cat(io.dmi_reg_wdata(31,24), 0.U, io.dmi_reg_wdata(22,19), command_postexec_din, command_transfer_din, io.dmi_reg_wdata(16))
val temp_command_din_15_0 = Mux(command_wren, io.dmi_reg_wdata(15,0), dbg_cmd_next_addr(15,0))
command_din := Cat(temp_command_din_31_16, temp_command_din_15_0)
execute_command := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(execute_command_ns, false.B)} // execute_commandff
val temp_command_reg_31_16 = withReset(dbg_dm_rst_l) {
rvdffe(command_din(31,16), command_wren, clock, io.scan_mode)} // dmcommand_reg
val temp_command_reg_15_0 = withReset(dbg_dm_rst_l) {
rvdffe(command_din(15,0), command_regno_wren, clock, io.scan_mode)} // dmcommand_regno_reg
command_reg := Cat(temp_command_reg_31_16, temp_command_reg_15_0)
val data0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h4".U) & (dbg_state === state_t.halted) & !abstractcs_reg(12)
val data0_reg_wren1 = io.core_dbg_cmd_done & (dbg_state === state_t.core_cmd_wait) & !command_reg(16)
val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 | data0_reg_wren2
val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata |
Fill(32, data0_reg_wren1) & io.core_dbg_rddata |
Fill(32, data0_reg_wren2) & sb_bus_rdata(31,0)
val data0_reg = withReset(dbg_dm_rst_l.asAsyncReset()) {
rvdffe(data0_din, data0_reg_wren, clock, io.scan_mode)
} // dbg_data0_reg
val data1_reg_wren0 = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === 5.U(7.W)) & (dbg_state === state_t.halted)) & !abstractcs_reg(12)
val data1_reg_wren1 = (dbg_state === state_t.cmd_done) & (command_reg(31,24) === 2.U(8.W)) & command_reg(19) & ~(abstractcs_reg(10,8).orR) // aampostincrement
val data1_reg_wren = data1_reg_wren0 | data1_reg_wren1
val data1_din = Fill(32, data1_reg_wren0) & io.dmi_reg_wdata | Fill(32, data1_reg_wren1) & dbg_cmd_next_addr(31,0)
data1_reg := withReset(dbg_dm_rst_l.asAsyncReset()) {
rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode)} // dbg_data1_reg
val sb_abmem_cmd_done = withClockAndReset(dbg_free_clk, dbg_dm_rst_l){
RegEnable(sb_abmem_cmd_done_in, false.B, sb_abmem_cmd_done_en)} // sb_abmem_cmd_doneff
val sb_abmem_data_done = withClockAndReset(dbg_free_clk, dbg_dm_rst_l){
RegEnable(sb_abmem_data_done_in, false.B, sb_abmem_data_done_en)} // sb_abmem_data_doneff
val dbg_nxtstate = WireInit(state_t.idle)
dbg_nxtstate := state_t.idle
dbg_state_en := false.B
abstractcs_busy_wren := false.B
abstractcs_busy_din := false.B
io.dbg_halt_req := false.B
io.dbg_resume_req := false.B
dbg_sb_bus_error := false.B
data0_reg_wren2 := false.B
sb_abmem_cmd_done_in := false.B
sb_abmem_data_done_in := false.B
sb_abmem_cmd_done_en := false.B
sb_abmem_data_done_en := false.B
switch(dbg_state) {
is(state_t.idle) {
dbg_nxtstate := Mux(dmstatus_reg(9) | io.dec_tlu_mpc_halted_only, state_t.halted, state_t.halting)
dbg_state_en := ((dmcontrol_reg(31) | dmstatus_reg(9) | io.dec_tlu_mpc_halted_only))
io.dbg_halt_req := dmcontrol_reg(31).asBool()
}
is(state_t.halting) {
dbg_nxtstate := state_t.halted
dbg_state_en := dmstatus_reg(9) | io.dec_tlu_mpc_halted_only
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31)).asBool()
}
is(state_t.halted) {
dbg_nxtstate := Mux(dmstatus_reg(9), Mux(resumereq, state_t.resuming, Mux((command_reg(31, 24) === 2.U(8.W)) & abmem_addr_external,
state_t.sb_cmd_start, state_t.core_cmd_start)), Mux(dmcontrol_reg(31), state_t.halting, state_t.idle)) // This is MPC halted case
dbg_state_en := dmstatus_reg(9) & resumereq | execute_command | !(dmstatus_reg(9) | io.dec_tlu_mpc_halted_only)
abstractcs_busy_wren := dbg_state_en & ((dbg_nxtstate === state_t.core_cmd_start) | (dbg_nxtstate === state_t.sb_cmd_start))
abstractcs_busy_din := "b1".U
io.dbg_resume_req := (dbg_state_en & (dbg_nxtstate === state_t.resuming)).asBool()
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31)).asBool()
}
is(state_t.core_cmd_start) {
dbg_nxtstate := Mux(abstractcs_reg(10, 8).orR | ((command_reg(31, 24) === 0.U(8.W)) & !command_reg(17)), state_t.cmd_done, state_t.core_cmd_wait)
dbg_state_en := io.dbg_dec_dma.dbg_ib.dbg_cmd_valid | abstractcs_reg(10, 8).orR | ((command_reg(31, 24) === 0.U(8.W)) & !command_reg(17))
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31)).asBool()
}
is(state_t.core_cmd_wait) {
dbg_nxtstate := state_t.cmd_done
dbg_state_en := io.core_dbg_cmd_done
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31)).asBool()
}
is(state_t.sb_cmd_start) {
dbg_nxtstate := Mux(abstractcs_reg(10, 8).orR, state_t.cmd_done, state_t.sb_cmd_send)
dbg_state_en := (io.dbg_bus_clk_en & !sb_cmd_pending) | abstractcs_reg(10, 8).orR
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31)).asBool()
}
is(state_t.sb_cmd_send) {
sb_abmem_cmd_done_in := true.B
sb_abmem_data_done_in := true.B
sb_abmem_cmd_done_en := (sb_bus_cmd_read | sb_bus_cmd_write_addr) & io.dbg_bus_clk_en
sb_abmem_data_done_en := (sb_bus_cmd_read | sb_bus_cmd_write_data) & io.dbg_bus_clk_en
dbg_nxtstate := state_t.sb_cmd_resp
dbg_state_en := (sb_abmem_cmd_done | sb_abmem_cmd_done_en) & (sb_abmem_data_done | sb_abmem_data_done_en) & io.dbg_bus_clk_en
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31)).asBool()
}
is(state_t.sb_cmd_resp) {
dbg_nxtstate := state_t.cmd_done
dbg_state_en := (sb_bus_rsp_read | sb_bus_rsp_write) & io.dbg_bus_clk_en
dbg_sb_bus_error := (sb_bus_rsp_read | sb_bus_rsp_write) & sb_bus_rsp_error & io.dbg_bus_clk_en
data0_reg_wren2 := dbg_state_en & !sb_abmem_cmd_write & !dbg_sb_bus_error
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31)).asBool()
}
is(state_t.cmd_done) {
dbg_nxtstate := state_t.halted
dbg_state_en := true.B
abstractcs_busy_wren := dbg_state_en
abstractcs_busy_din := false.B
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31)).asBool()
sb_abmem_cmd_done_in := false.B
sb_abmem_data_done_in := false.B
sb_abmem_cmd_done_en := true.B
sb_abmem_data_done_en := true.B
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31)).asBool()
}
is(state_t.resuming) {
dbg_nxtstate := state_t.idle;
dbg_state_en := dmstatus_reg(17)
io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31)).asBool()
}}
val dmi_reg_rdata_din = Fill(32, io.dmi_reg_addr === "h4".U(7.W)).asUInt & data0_reg |
Fill(32, io.dmi_reg_addr === "h5".U(7.W)) & data1_reg |
Fill(32, io.dmi_reg_addr === "h10".U(7.W)) & Cat(0.U(2.W), dmcontrol_reg(29), 0.U, dmcontrol_reg(27,0)) |
Fill(32, io.dmi_reg_addr === "h11".U(7.W)) & dmstatus_reg |
Fill(32, io.dmi_reg_addr === "h16".U(7.W)) & abstractcs_reg |
Fill(32, io.dmi_reg_addr === "h17".U(7.W)) & command_reg |
Fill(32, io.dmi_reg_addr === "h18".U(7.W)) & Cat(0.U(30.W), abstractauto_reg(1,0)) |
Fill(32, io.dmi_reg_addr === "h40".U(7.W)) & haltsum0_reg |
Fill(32, io.dmi_reg_addr === "h38".U(7.W)) & sbcs_reg |
Fill(32, io.dmi_reg_addr === "h39".U(7.W)) & sbaddress0_reg |
Fill(32, io.dmi_reg_addr === "h3c".U(7.W)) & sbdata0_reg |
Fill(32, io.dmi_reg_addr === "h3d".U(7.W)) & sbdata1_reg
dbg_state := withClockAndReset(dbg_free_clk, (dbg_dm_rst_l.asBool() & temp_rst).asAsyncReset()) {
RegEnable(dbg_nxtstate, 0.U, dbg_state_en)} // dbg_state_reg
io.dmi_reg_rdata := withReset(dbg_dm_rst_l) {
rvdffe(dmi_reg_rdata_din, io.dmi_reg_en, clock, io.scan_mode)} // dmi_rddata_reg
val abmem_addr = data1_reg
val abmem_addr_core_local = (abmem_addr_in_dccm_region | abmem_addr_in_iccm_region | abmem_addr_in_pic_region)
abmem_addr_external := !abmem_addr_core_local
abmem_addr_in_dccm_region := (abmem_addr(31,28) === DCCM_REGION.asUInt) & (DCCM_ENABLE==1).B
abmem_addr_in_iccm_region := (abmem_addr(31,28) === ICCM_REGION.asUInt) & (ICCM_ENABLE==1).B
abmem_addr_in_pic_region := (abmem_addr(31,28) === PIC_REGION.asUInt)
io.dbg_dec_dma.dbg_ib.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), data1_reg, Cat(0.U(20.W), command_reg(11, 0)))
io.dbg_dec_dma.dbg_dctl.dbg_cmd_wrdata := data0_reg(31, 0)
io.dbg_dec_dma.dbg_ib.dbg_cmd_valid := (dbg_state === state_t.core_cmd_start) & !((abstractcs_reg(10,8).orR) | ((command_reg(31,24) === 0.U(8.W)) & !command_reg(17)) |
((command_reg(31,24) === 2.U(8.W)) & abmem_addr_external)) & io.dbg_dma.dma_dbg_ready
io.dbg_dec_dma.dbg_ib.dbg_cmd_write := command_reg(16).asBool()
io.dbg_dec_dma.dbg_ib.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U, Cat("b0".U, (command_reg(15, 12) === "b0".U)))
io.dbg_cmd_size := command_reg(21, 20)
val dbg_cmd_addr_incr = Mux((command_reg(31,24) === 2.U(8.W)), (1.U(4.W) << sb_abmem_cmd_size(1,0)), 1.U(4.W))
val dbg_cmd_curr_addr = Mux((command_reg(31,24) === 2.U(8.W)), data1_reg, Cat(0.U(16.W), command_reg(15,0)))
dbg_cmd_next_addr := dbg_cmd_curr_addr + Cat(0.U(28.W), dbg_cmd_addr_incr)
io.dbg_dma.dbg_dma_bubble := ((dbg_state === state_t.core_cmd_start) & ~(abstractcs_reg(10, 8).orR) | (dbg_state === state_t.core_cmd_wait)).asBool()
sb_cmd_pending := (sb_state === sb_state_t.cmd_rd) | (sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_addr) |
(sb_state === sb_state_t.cmd_wr_data) | (sb_state === sb_state_t.rsp_rd) | (sb_state === sb_state_t.rsp_wr)
val sb_abmem_cmd_pending = (dbg_state === state_t.sb_cmd_start) | (dbg_state === state_t.sb_cmd_send) | (dbg_state === state_t.sb_cmd_resp)
val sb_nxtstate = WireInit(sb_state_t.sbidle)
sb_nxtstate := sb_state_t.sbidle
//sb_state_en := true.B
sbcs_sbbusy_wren := false.B
sbcs_sbbusy_din := false.B
sbcs_sberror_wren := false.B
sbcs_sberror_din := 0.U(3.W)
sbaddress0_reg_wren1 := false.B
switch(sb_state) {
is(sb_state_t.sbidle) {
sb_nxtstate := Mux(sbdata0wr_access, sb_state_t.wait_wr, sb_state_t.wait_rd)
sb_state_en := (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(sbcs_reg(14,12).orR) & !sbcs_reg(22)
sbcs_sbbusy_wren := sb_state_en
sbcs_sbbusy_din := true.B
sbcs_sberror_wren := sbcs_wren & io.dmi_reg_wdata(14, 12).orR
sbcs_sberror_din := ~io.dmi_reg_wdata(14, 12) & sbcs_reg(14, 12)
}
is(sb_state_t.wait_rd) {
sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_rd)
sb_state_en := (io.dbg_bus_clk_en & !sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size
sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size
sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U(3.W), "b100".U(3.W))
}
is(sb_state_t.wait_wr) {
sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_wr)
sb_state_en := (io.dbg_bus_clk_en & !sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size
sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size;
sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U(3.W), "b100".U(3.W))
}
is(sb_state_t.cmd_rd) {
sb_nxtstate := sb_state_t.rsp_rd
sb_state_en := sb_bus_cmd_read & io.dbg_bus_clk_en
}
is(sb_state_t.cmd_wr) {
sb_nxtstate := Mux(sb_bus_cmd_write_addr & sb_bus_cmd_write_data, sb_state_t.rsp_wr,
Mux(sb_bus_cmd_write_data, sb_state_t.cmd_wr_addr, sb_state_t.cmd_wr_data))
sb_state_en := (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & io.dbg_bus_clk_en
}
is(sb_state_t.cmd_wr_addr) {
sb_nxtstate := sb_state_t.rsp_wr
sb_state_en := sb_bus_cmd_write_addr & io.dbg_bus_clk_en
}
is(sb_state_t.cmd_wr_data) {
sb_nxtstate := sb_state_t.rsp_wr
sb_state_en := sb_bus_cmd_write_data & io.dbg_bus_clk_en
}
is(sb_state_t.rsp_rd) {
sb_nxtstate := sb_state_t.done
sb_state_en := sb_bus_rsp_read & io.dbg_bus_clk_en
sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error
sbcs_sberror_din := "b010".U(3.W)
}
is(sb_state_t.rsp_wr) {
sb_nxtstate := sb_state_t.done;
sb_state_en := sb_bus_rsp_write & io.dbg_bus_clk_en
sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error
sbcs_sberror_din := "b010".U(3.W)
}
is(sb_state_t.done) {
sb_nxtstate := sb_state_t.sbidle;
sb_state_en := true.B
sbcs_sbbusy_wren := true.B
sbcs_sbbusy_din := false.B
sbaddress0_reg_wren1 := sbcs_reg(16) & (sbcs_reg(14,12) === 0.U(3.W))
}}
sb_state := withClockAndReset(sb_free_clk, dbg_dm_rst_l.asAsyncReset()) {
RegEnable(sb_nxtstate, 0.U, sb_state_en)
} // sb_state_reg
sb_abmem_cmd_write := command_reg(16)
sb_abmem_cmd_size := Cat(0.U(1.W), command_reg(21,20))
val sb_abmem_cmd_addr = abmem_addr
val sb_abmem_cmd_wdata = data0_reg
val sb_cmd_size = sbcs_reg(19,17)
val sb_cmd_wdata = Cat(sbdata1_reg(31,0), sbdata0_reg(31,0))
val sb_cmd_addr = sbaddress0_reg(31,0)
val sb_abmem_cmd_awvalid = (dbg_state === state_t.sb_cmd_send) & sb_abmem_cmd_write & !sb_abmem_cmd_done
val sb_abmem_cmd_wvalid = (dbg_state === state_t.sb_cmd_send) & sb_abmem_cmd_write & !sb_abmem_data_done
val sb_abmem_cmd_arvalid = (dbg_state === state_t.sb_cmd_send) & !sb_abmem_cmd_write & !sb_abmem_cmd_done & !sb_abmem_data_done
val sb_abmem_read_pend = (dbg_state === state_t.sb_cmd_resp) & !sb_abmem_cmd_write
val sb_cmd_awvalid = ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_addr))
val sb_cmd_wvalid = ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_data))
val sb_cmd_arvalid = (sb_state === sb_state_t.cmd_rd)
val sb_read_pend = (sb_state === sb_state_t.cmd_rd)
val sb_axi_size = Mux((sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid | sb_abmem_cmd_arvalid | sb_abmem_read_pend), sb_abmem_cmd_size(2,0), sb_cmd_size(2,0))
val sb_axi_addr = Mux((sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid | sb_abmem_cmd_arvalid | sb_abmem_read_pend), sb_abmem_cmd_addr(31,0), sb_cmd_addr(31,0))
val sb_axi_wrdata = Mux((sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid), Fill(2, sb_abmem_cmd_wdata(31,0)), sb_cmd_wdata(63,0))
sb_bus_cmd_read := io.sb_axi.ar.valid & io.sb_axi.ar.ready
sb_bus_cmd_write_addr := io.sb_axi.aw.valid & io.sb_axi.aw.ready
sb_bus_cmd_write_data := io.sb_axi.w.valid & io.sb_axi.w.ready
sb_bus_rsp_read := io.sb_axi.r.valid & io.sb_axi.r.ready
sb_bus_rsp_write := io.sb_axi.b.valid & io.sb_axi.b.ready
sb_bus_rsp_error := sb_bus_rsp_read & io.sb_axi.r.bits.resp(1, 0).orR | sb_bus_rsp_write & io.sb_axi.b.bits.resp(1, 0).orR
io.sb_axi.aw.valid := sb_abmem_cmd_awvalid | sb_cmd_awvalid
io.sb_axi.aw.bits.addr := sb_axi_addr
io.sb_axi.aw.bits.id := 0.U
io.sb_axi.aw.bits.size := sb_axi_size
io.sb_axi.aw.bits.prot := 1.U(3.W)
io.sb_axi.aw.bits.cache := "b1111".U(4.W)
io.sb_axi.aw.bits.region := sb_axi_addr(31, 28)
io.sb_axi.aw.bits.len := 0.U
io.sb_axi.aw.bits.burst := "b01".U(2.W)
io.sb_axi.aw.bits.qos := 0.U
io.sb_axi.aw.bits.lock := false.B
io.sb_axi.w.valid := sb_abmem_cmd_wvalid | sb_cmd_wvalid
io.sb_axi.w.bits.data := Fill(64, (sb_axi_size === 0.U(3.W))) & Fill(8, (sb_axi_wrdata(7, 0))) |
Fill(64, (sb_axi_size === 1.U(3.W))) & Fill(4, sb_axi_wrdata(15, 0)) |
Fill(64, (sb_axi_size === 2.U(3.W))) & Fill(2, (sb_axi_wrdata(31, 0))) |
Fill(64, (sb_axi_size === 3.U(3.W))) & sb_axi_wrdata
io.sb_axi.w.bits.strb := Fill(8, (sb_axi_size === 0.U(3.W))) & ("h1".U(8.W) << sb_axi_addr(2, 0)) |
Fill(8, (sb_axi_size === 1.U(3.W))) & ("h3".U(8.W) << Cat(sb_axi_addr(2, 1), 0.U(1.W))) |
Fill(8, (sb_axi_size === 2.U(3.W))) & ("hf".U(8.W) << Cat(sb_axi_addr(2), 0.U(2.W))) |
Fill(8, (sb_axi_size === 3.U(3.W))) & "hff".U(8.W)
io.sb_axi.w.bits.last := true.B
io.sb_axi.ar.valid := sb_abmem_cmd_arvalid | sb_cmd_arvalid
io.sb_axi.ar.bits.addr := sb_axi_addr
io.sb_axi.ar.bits.id := 0.U
io.sb_axi.ar.bits.size := sb_axi_size
io.sb_axi.ar.bits.prot := 1.U(3.W)
io.sb_axi.ar.bits.cache := 0.U(4.W)
io.sb_axi.ar.bits.region := sb_axi_addr(31, 28)
io.sb_axi.ar.bits.len := 0.U
io.sb_axi.ar.bits.burst := 1.U(2.W)
io.sb_axi.ar.bits.qos := 0.U
io.sb_axi.ar.bits.lock := false.B
io.sb_axi.b.ready := true.B
io.sb_axi.r.ready := true.B
sb_bus_rdata := Fill(64, (sb_axi_size === "h0".U)) & ((io.sb_axi.r.bits.data(63, 0) >> 8.U * sb_axi_addr(2, 0)) & "hff".U(64.W)) |
Fill(64, (sb_axi_size === "h1".U)) & ((io.sb_axi.r.bits.data(63, 0) >> 16.U * sb_axi_addr(2, 1)) & "hffff".U(64.W)) |
Fill(64, (sb_axi_size === "h2".U)) & ((io.sb_axi.r.bits.data(63, 0) >> 32.U * sb_axi_addr(2)) & "hffff_ffff".U(64.W)) |
Fill(64, (sb_axi_size === "h3".U)) & io.sb_axi.r.bits.data(63, 0)
}
object debug extends App {
(new chisel3.stage.ChiselStage).emitVerilog(new dbg)
}

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design/src/main/scala/dec/dec.scala Normal file
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package dec
import chisel3._
import chisel3.util._
import include._
import lib._
import lsu._
class dec_IO extends Bundle with lib {
val free_clk = Input(Clock())
val active_clk = Input(Clock())
val free_l2clk = Input(Clock())
val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating
val dec_tlu_core_empty = Output(Bool())
val rst_vec = Input(UInt(31.W)) // [31:1] reset vector, from core pins
val ifu_i0_fa_index = Input(UInt(log2Ceil(BTB_SIZE).W))
val dec_fa_error_index = Output(UInt(log2Ceil(BTB_SIZE).W))
val nmi_int = Input(Bool()) // NMI pin
val nmi_vec = Input(UInt(31.W)) // [31:1] NMI vector, from pins
val lsu_nonblock_load_data = Input(UInt(32.W))
val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU
val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU
val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw)
val o_cpu_halt_ack = Output(Bool()) // Halt request ack
val o_cpu_run_ack = Output(Bool()) // Run request ack
val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
val core_id = Input(UInt(28.W)) // [31:4] CORE ID
val mpc_debug_halt_req = Input(Bool()) // Async halt request
val mpc_debug_run_req = Input(Bool()) // Async run request
val mpc_reset_run_req = Input(Bool()) // Run/halt after reset
val mpc_debug_halt_ack = Output(Bool()) // Halt ack
val mpc_debug_run_ack = Output(Bool()) // Run ack
val debug_brkpt_status = Output(Bool()) // debug breakpoint
val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned
val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address
val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error
val lsu_trigger_match_m = Input(UInt(4.W))
val lsu_idle_any = Input(Bool()) // lsu idle for halting
val lsu_error_pkt_r = Flipped(Valid(new lsu_error_pkt_t)) // LSU exception/error packet
val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
val exu_div_result = Input(UInt(32.W)) // final div result
val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR
val lsu_result_m = Input(UInt(32.W)) // load result
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data
val lsu_load_stall_any = Input(Bool()) // This is for blocking loads
val lsu_store_stall_any = Input(Bool()) // This is for blocking stores
val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error
val exu_flush_final = Input(Bool()) // slot0 flush
val timer_int = Input(Bool()) // Timer interrupt pending (from pin)
val soft_int = Input(Bool()) // Software interrupt pending (from pin)
// Debug start
val dbg_halt_req = Input(Bool()) // DM requests a halt
val dbg_resume_req = Input(Bool()) // DM requests a resume
val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command
val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode
val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge
val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC
val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data
val dec_csr_rddata_d = Output(UInt(32.W))
val dec_dbg_cmd_done = Output(Bool()) // abstract command is done
val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address)
val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t)) // info needed by debug trigger blocks
val exu_i0_br_way_r = Input(Bool()) // way hit or repl
val lsu_p = Valid(new lsu_pkt_t) // lsu packet
val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
val dec_tlu_flush_lower_wb = Output(Bool())
val dec_lsu_valid_raw_d = Output(Bool())
val trace_rv_trace_pkt = Output(new trace_pkt_t) // trace packet
// clock gating overrides from mcgc
val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating
val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating
val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating
val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating
val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating
val dec_tlu_picio_clk_override = Output(Bool())
val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
val dec_i0_decode_d = Output(Bool())
val scan_mode = Input(Bool())
val ifu_dec = Flipped(new ifu_dec)
val dec_exu = Flipped(new dec_exu)
val lsu_dec = Flipped (new lsu_dec)
val lsu_tlu = Flipped (new lsu_tlu)
val dec_dbg = new dec_dbg
val dec_dma = new dec_dma
val dec_pic = new dec_pic
}
class dec extends Module with param with RequireAsyncReset{
val io = IO(new dec_IO)
val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U)
val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U)
val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U)
val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U)
val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U)
val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
val dec_tlu_trace_disable = WireInit(Bool(),0.B)
// val dec_i0_bp_fa_index = WireInit(UInt(log2Ceil(BTB_SIZE).W),0.U)
//val dec_debug_valid_d = WireInit(Bool(),0.B)
//--------------------------------------------------------------------------//
val instbuff = Module(new dec_ib_ctl)
val decode = Module(new dec_decode_ctl)
val gpr = Module(new dec_gpr_ctl)
val tlu = Module(new dec_tlu_ctl)
val dec_trigger = Module(new dec_trigger)
//connections for dec_Ib
//inputs
instbuff.io.ifu_ib <> io.ifu_dec.dec_aln.aln_ib
instbuff.io.ib_exu <> io.dec_exu.ib_exu
instbuff.io.dbg_ib <> io.dec_dbg.dbg_ib
instbuff.io.ifu_i0_fa_index := io.ifu_i0_fa_index
dec_trigger.io.dec_i0_pc_d := instbuff.io.ib_exu.dec_i0_pc_d
dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
dontTouch(dec_i0_trigger_match_d)
decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec
io.dec_i0_decode_d := decode.io.dec_i0_decode_d
decode.io.decode_exu<> io.dec_exu.decode_exu
decode.io.dec_alu<> io.dec_exu.dec_alu
decode.io.dec_div<> io.dec_exu.dec_div
decode.io.dctl_dma <> io.dec_dma.dctl_dma
decode.io.dec_tlu_trace_disable := tlu.io.dec_tlu_trace_disable
decode.io.dec_debug_valid_d := instbuff.io.dec_debug_valid_d
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt
decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff
decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable
decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m
decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_misaligned_m
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
decode.io.dec_i0_bp_fa_index := instbuff.io.dec_i0_bp_fa_index
decode.io.dec_tlu_flush_leak_one_r := tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb
decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d
decode.io.dbg_dctl <> io.dec_dbg.dbg_dctl
decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d
decode.io.dec_i0_icaf_second_d := instbuff.io.dec_i0_icaf_second_d
decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d
decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d
decode.io.dec_i0_brp := instbuff.io.dec_i0_brp
decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index
decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr
decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag
decode.io.lsu_idle_any := io.lsu_idle_any
decode.io.lsu_load_stall_any := io.lsu_load_stall_any
decode.io.lsu_store_stall_any := io.lsu_store_stall_any
decode.io.exu_div_wren := io.exu_div_wren
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc4_d
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
decode.io.lsu_result_m := io.lsu_result_m
decode.io.lsu_result_corr_r := io.lsu_result_corr_r
decode.io.exu_flush_final := io.exu_flush_final
decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
decode.io.free_l2clk := io.free_l2clk
decode.io.active_clk := io.active_clk
decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
decode.io.scan_mode := io.scan_mode
dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb //for tracer
dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb //for tracer
io.lsu_p := decode.io.lsu_p
io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d
io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d
io.dec_pause_state_cg := decode.io.dec_pause_state_cg
io.dec_exu.decode_exu.dec_qual_lsu_d := decode.io.decode_exu.dec_qual_lsu_d
io.dec_fa_error_index :=decode.io.dec_fa_error_index
gpr.io.raddr0 := decode.io.dec_i0_rs1_d
gpr.io.raddr1 := decode.io.dec_i0_rs2_d
gpr.io.wen0 := decode.io.dec_i0_wen_r
gpr.io.waddr0 := decode.io.dec_i0_waddr_r
gpr.io.wd0 := decode.io.dec_i0_wdata_r
gpr.io.wen1 := decode.io.dec_nonblock_load_wen
gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr
gpr.io.wd1 := io.lsu_nonblock_load_data
gpr.io.wen2 := io.exu_div_wren
gpr.io.waddr2 := decode.io.div_waddr_wb
gpr.io.wd2 := io.exu_div_result
gpr.io.scan_mode := io.scan_mode
io.dec_exu.gpr_exu <> gpr.io.gpr_exu
tlu.io.tlu_mem <> io.ifu_dec.dec_mem_ctrl
tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc
tlu.io.tlu_bp <> io.ifu_dec.dec_bp
tlu.io.tlu_exu <> io.dec_exu.tlu_exu
tlu.io.tlu_dma <> io.dec_dma.tlu_dma
tlu.io.free_l2clk := io.free_l2clk
tlu.io.free_clk := io.free_clk
tlu.io.scan_mode := io.scan_mode
tlu.io.rst_vec := io.rst_vec
tlu.io.nmi_int := io.nmi_int
tlu.io.nmi_vec := io.nmi_vec
tlu.io.i_cpu_halt_req := io.i_cpu_halt_req
tlu.io.i_cpu_run_req := io.i_cpu_run_req
tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any
tlu.io.ifu_pmu_instr_aligned := io.ifu_dec.dec_aln.ifu_pmu_instr_aligned
tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded
tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall
tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
tlu.io.lsu_store_stall_any := io.lsu_store_stall_any
io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff
io.lsu_tlu <> tlu.io.lsu_tlu
io.dec_pic <> tlu.io.dec_pic
tlu.io.lsu_fir_addr := io.lsu_fir_addr
tlu.io.lsu_fir_error := io.lsu_fir_error
tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error
tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
tlu.io.dec_pause_state := decode.io.dec_pause_state
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
tlu.io.dec_i0_decode_d := decode.io.dec_i0_decode_d
tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
tlu.io.dbg_halt_req := io.dbg_halt_req
tlu.io.dbg_resume_req := io.dbg_resume_req
tlu.io.lsu_idle_any := io.lsu_idle_any
tlu.io.dec_div_active := decode.io.dec_div_active
tlu.io.timer_int := io.timer_int
tlu.io.soft_int := io.soft_int
tlu.io.core_id := io.core_id
tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req
tlu.io.mpc_debug_run_req := io.mpc_debug_run_req
tlu.io.mpc_reset_run_req := io.mpc_reset_run_req
io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done
io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail
io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted
io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode
io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack
io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only
io.trigger_pkt_any := tlu.io.trigger_pkt_any
io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
io.o_debug_mode_status := tlu.io.o_debug_mode_status
io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
io.debug_brkpt_status := tlu.io.debug_brkpt_status
io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2
io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3
dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1
dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1
dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1
dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1
dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1
io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override
io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override
io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override
io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override
io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override
io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override
io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override
io.dec_tlu_picio_clk_override := tlu.io.dec_tlu_picio_clk_override
io.dec_tlu_core_empty := tlu.io.dec_tlu_core_empty
io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
//--------------------------------------------------------------------------//
io.trace_rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb
io.trace_rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb, 0.U)
io.trace_rv_trace_pkt.rv_i_valid_ip := tlu.io.dec_tlu_int_valid_wb1 | tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1
io.trace_rv_trace_pkt.rv_i_exception_ip := tlu.io.dec_tlu_int_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1
io.trace_rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0)
io.trace_rv_trace_pkt.rv_i_interrupt_ip := tlu.io.dec_tlu_int_valid_wb1
io.trace_rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1
// debug command read data
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
}
object dec_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new dec()))
}

270
design/src/main/scala/dec/dec_dec_ctl.scala Normal file
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@ -0,0 +1,270 @@
package dec
import chisel3._
import include._
import lib._
class dec_dec_ctl extends Module with lib{
val io = IO (new Bundle{
val ins = Input(UInt(32.W))
val out = Output(new dec_pkt_t)
})
def pattern(y : List[Int]) : UInt = {
val pat : Array[UInt] = new Array[UInt](y.size)
for (i <- 0 until y.size){
pat(i) = if(y(i)>=0) io.ins(y(i)) else !io.ins(y(i).abs)
}
pat.reduce(_&_)
}
io.out.alu := pattern(List(30,24,23,-22,-21,-20,14,-5,4)) | pattern(List(29,-27,-24,4)) |
pattern(List(-25,-13,-12,4)) | pattern(List(-30,-25,13,12)) | pattern(List(27,25,14,4)) |
pattern(List(29,27,-14,4)) | pattern(List(29,-14,5,4)) | pattern(List(-27,-25,14,4)) |
pattern(List(30,-29,-13,4)) | pattern(List(-30,-27,-25,4)) | pattern(List(13,-5,4)) |
pattern(List(-12,-5,4)) | pattern(List(2)) | pattern(List(6)) | pattern(List(30,24,23,22,21,20,-5,4)) |
pattern(List(-30,29,-24,-23,22,21,20,-5,4)) | pattern(List(-30,24,-23,-22,-21,-20,-5,4))
io.out.rs1 := pattern(List(-14,-13,-2)) | pattern(List(-13,11,-2)) | pattern(List(19,13,-2)) |
pattern(List(-13,10,-2)) | pattern(List(18,13,-2)) | pattern(List(-13,9,-2)) | pattern(List(17,13,-2)) |
pattern(List(-13,8,-2)) | pattern(List(16,13,-2)) | pattern(List(-13,7,-2)) |
pattern(List(15,13,-2)) | pattern(List(-4,-3)) | pattern(List(-6,-2))
io.out.rs2 := pattern(List(5,-4,-2)) | pattern(List(-6,5,-2))
io.out.imm12 := pattern(List(-4,-3,2)) | pattern(List(13,-5,4,-2)) | pattern(List(-13,-12,6,4)) | pattern(List(-12,-5,4,-2))
io.out.rd := pattern(List(-5,-2)) | pattern(List(5,2)) | pattern(List(4))
io.out.shimm5 := pattern(List(27,-13,12,-5,4,-2)) | pattern(List(-30,-13,12,-5,4,-2)) | pattern(List(14,-13,12,-5,4,-2))
io.out.imm20 := pattern(List(5,3)) | pattern(List(4,2))
io.out.pc := pattern(List(-5,-3,2)) | pattern(List(5,3))
io.out.load := pattern(List(-5,-4,-2))
io.out.store := pattern(List(-6,5,-4))
io.out.lsu := pattern(List(-6,-4,-2))
io.out.add := pattern(List(-14,-13,-12,-5,4)) | pattern(List(-5,-3,2)) | pattern(List(-30,-25,-14,-13,-12,-6,4,-2))
io.out.sub := pattern(List(30,-14,-12,-6,5,4,-2)) | pattern(List(-29,-25,-14,13,-6,4,-2)) |
pattern(List(27,25,14,-6,5,-2)) | pattern(List(-14,13,-5,4,-2)) | pattern(List(6,-4,-2))
io.out.land := pattern(List(-27,-25,14,13,12,-6,-2)) | pattern(List(14,13,12,-5,-2))
io.out.lor := pattern(List(-6,3)) | pattern(List(-29,-27,-25,14,13,-12,-6,-2)) | pattern(List(5,4,2)) |
pattern(List(-13,-12,6,4)) | pattern(List(14,13,-12,-5,-2))
io.out.lxor := pattern(List(-29,-27,-25,14,-13,-12,4,-2)) | pattern(List(14,-13,-12,-5,4,-2))
io.out.sll := pattern(List(-29,-27,-25,-14,-13,12,-6,4,-2))
io.out.sra := pattern(List(30,-29,-27,-13,12,-6,4,-2))
io.out.srl := pattern(List(-30,-29,-27,-25,14,-13,12,-6,4,-2))
io.out.slt := pattern(List(-29,-25,-14,13,-6,4,-2)) | pattern(List(-14,13,-5,4,-2))
io.out.unsign := pattern(List(-27,25,14,12,-6,5,-2)) | pattern(List(-14,13,12,-5,-2)) |
pattern(List(13,6,-4,-2)) | pattern(List(14,-5,-4)) | pattern(List(-25,-14,13,12,-6,-2)) |
pattern(List(27,25,14,13,-6,5,-2))
io.out.condbr := pattern(List(6,-4,-2))
io.out.beq := pattern(List(-14,-12,6,-4,-2))
io.out.bne := pattern(List(-14,12,6,-4,-2))
io.out.bge := pattern(List(14,12,5,-4,-2))
io.out.blt := pattern(List(14,-12,5,-4,-2))
io.out.jal := pattern(List(6,2))
io.out.by := pattern(List(-13,-12,-6,-4,-2))
io.out.half := pattern(List(12,-6,-4,-2))
io.out.word := pattern(List(13,-6,-4))
io.out.csr_read := pattern(List(13,6,4)) | pattern(List(7,6,4)) | pattern(List(8,6,4)) |
pattern(List(9,6,4)) | pattern(List(10,6,4)) | pattern(List(11,6,4))
io.out.csr_clr := pattern(List(15,13,12,6,4)) | pattern(List(16,13,12,6,4)) |
pattern(List(17,13,12,6,4)) | pattern(List(18,13,12,6,4)) | pattern(List(19,13,12,6,4))
io.out.csr_set := pattern(List(15,-12,6,4)) | pattern(List(16,-12,6,4)) | pattern(List(17,-12,6,4)) |
pattern(List(18,-12,6,4)) | pattern(List(19,-12,6,4))
io.out.csr_write := pattern(List(-13,12,6,4))
io.out.csr_imm := pattern(List(14,-13,6,4)) | pattern(List(15,14,6,4)) | pattern(List(16,14,6,4)) |
pattern(List(17,14,6,4)) | pattern(List(18,14,6,4)) | pattern(List(19,14,6,4))
io.out.presync := pattern(List(-5,3)) | pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) |
pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) | pattern(List(-13,11,6,4)) |
pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) |
pattern(List(18,13,6,4)) | pattern(List(19,13,6,4))
io.out.postsync := pattern(List(12,-5,3)) | pattern(List(-22,-13,-12,6,4)) |
pattern(List(-13,7,6,4)) | pattern(List(-13,8,6,4)) | pattern(List(-13,9,6,4)) | pattern(List(-13,10,6,4)) |
pattern(List(-13,11,6,4)) | pattern(List(15,13,6,4)) | pattern(List(16,13,6,4)) | pattern(List(17,13,6,4)) |
pattern(List(18,13,6,4)) | pattern(List(19,13,6,4))
io.out.ebreak := pattern(List(-22,20,-13,-12,6,4))
io.out.ecall := pattern(List(-21,-20,-13,-12,6,4))
io.out.mret := pattern(List(29,-13,-12,6,4))
io.out.mul := pattern(List(-30,27,24,20,14,-13,12,-5,4,-2)) | pattern(List(29,27,-24,23,14,-13,12,-5,4,-2)) |
pattern(List(29,27,-24,-20,14,-13,12,-5,4,-2)) | pattern(List(27,-25,13,-12,-6,5,4,-2)) |
pattern(List(30,27,13,-6,5,4,-2)) | pattern(List(29,27,22,-20,14,-13,12,-5,4,-2)) |
pattern(List(29,27,-21,20,14,-13,12,-5,4,-2)) | pattern(List(29,27,-22,21,14,-13,12,-5,4,-2)) |
pattern(List(30,29,27,-23,14,-13,12,-5,4,-2)) | pattern(List(-30,27,23,14,-13,12,-5,4,-2)) |
pattern(List(-30,-29,27,-25,-13,12,-6,4,-2)) | pattern(List(25,-14,-6,5,4,-2)) |
pattern(List(30,-27,24,-14,-13,12,-5,4,-2)) | pattern(List(29,27,14,-6,5,-2))
io.out.rs1_sign := pattern(List(-27,25,-14,13,-12,-6,5,4,-2)) | pattern(List(-27,25,-14,-13,12,-6,4,-2))
io.out.rs2_sign := pattern(List(-27,25,-14,-13,12,-6,4,-2))
io.out.low := pattern(List(25,-14,-13,-12,5,4,-2))
io.out.div := pattern(List(-27,25,14,-6,5,-2))
io.out.rem := pattern(List(-27,25,14,13,-6,5,-2))
io.out.fence := pattern(List(-5,3))
io.out.fence_i := pattern(List(12,-5,3))
io.out.clz := pattern(List(30,-27,-24,-22,-21,-20,-14,-13,12,-5,4,-2))
io.out.ctz := pattern(List(30,-27,-24,-22,20,-14,-13,12,-5,4,-2))
io.out.pcnt := pattern(List(30,-27,-24,21,-14,-13,12,-5,4,-2))
io.out.sext_b := pattern(List(30,-27,22,-20,-14,-13,12,-5,4,-2))
io.out.sext_h := pattern(List(30,-27,22,20,-14,-13,12,-5,4,-2))
io.out.slo := pattern(List(-30,29,-27,-14,-13,12,-6,4,-2))
io.out.sro := pattern(List(-30,29,-27,14,-13,12,-6,4,-2))
io.out.min := pattern(List(27,25,14,-12,-6,5,-2))
io.out.max := pattern(List(27,25,14,12,-6,5,-2))
io.out.pack := pattern(List(-30,27,-25,-13,-12,5,4,-2))
io.out.packu := pattern(List(30,27,-13,-12,5,4,-2))
io.out.packh := pattern(List(-30,27,-25,13,12,-6,5,-2))
io.out.rol := pattern(List(30,-27,-14,12,-6,5,4,-2))
io.out.ror := pattern(List(30,29,-27,14,-13,12,-6,4,-2))
io.out.zbb := pattern(List(30,-27,-24,-14,-13,12,-5,4,-2)) | pattern(List(-30,27,14,13,12,-6,5,-2)) |
pattern(List(30,29,-27,14,-13,12,-5,4,-2)) | pattern(List(27,-13,-12,5,4,-2)) |
pattern(List(30,14,-13,-12,-6,5,-2)) | pattern(List(30,-27,13,-6,5,4,-2)) |
pattern(List(30,29,-27,-6,5,4,-2)) | pattern(List(30,29,24,23,22,21,20,14,-13,12,-5,4,-2)) |
pattern(List(-30,29,27,-24,-23,22,21,20,14,-13,12,-5,4,-2)) |
pattern(List(-30,27,24,-23,-22,-21,-20,14,-13,12,-5,4,-2)) |
pattern(List(30,29,24,23,-22,-21,-20,14,-13,12,-5,4,-2)) | pattern(List(27,25,14,-6,5,-2))
io.out.sbset := pattern(List(-30,29,27,-14,-13,12,-6,4,-2))
io.out.sbclr := pattern(List(30,-29,-14,-13,12,-6,4,-2))
io.out.sbinv := pattern(List(30,29,27,-14,-13,12,-6,4,-2))
io.out.sbext := pattern(List(30,-29,27,14,-13,12,-6,4,-2))
io.out.zbs := pattern(List(29,27,-14,-13,12,-6,4,-2)) | pattern(List(30,-29,27,-13,12,-6,4,-2))
io.out.bext := pattern(List(-30,27,-25,13,-12,-6,5,4,-2))
io.out.bdep := pattern(List(30,27,13,-12,-6,5,4,-2))
io.out.zbe := pattern(List(27,-25,13,-12,-6,5,4,-2))
io.out.clmul := pattern(List(27,25,-14,-13,-6,5,4,-2))
io.out.clmulh := pattern(List(27,-14,13,12,-6,5,-2))
io.out.clmulr := pattern(List(27,-14,-12,-6,5,4,-2))
io.out.zbc := pattern(List(27,25,-14,-6,5,4,-2))
io.out.grev := pattern(List(30,29,27,14,-13,12,-6,4,-2))
io.out.gorc := pattern(List(-30,29,27,14,-13,12,-6,4,-2))
io.out.shfl := pattern(List(-30,-29,27,-25,-14,-13,12,-6,4,-2))
io.out.unshfl := pattern(List(-30,-29,27,-25,14,-13,12,-6,4,-2))
io.out.zbp := pattern(List(-30,29,-27,-13,12,-5,4,-2)) | pattern(List(-30,-29,27,-13,12,-5,4,-2)) |
pattern(List(30,-27,13,-6,5,4,-2)) | pattern(List(27,-25,-13,-12,5,4,-2)) |
pattern(List(30,14,-13,-12,5,4,-2)) | pattern(List(29,-27,12,-6,5,4,-2)) |
pattern(List(-30,-29,27,-25,12,-6,5,4,-2)) | pattern(List(29,14,-13,12,-6,4,-2))
io.out.crc32_b := pattern(List(30,-27,24,-23,-21,-20,-14,-13,12,-5,4,-2))
io.out.crc32_h := pattern(List(30,-27,24,-23,20,-14,-13,12,-5,4,-2))
io.out.crc32_w := pattern(List(30,-27,24,-23,21,-14,-13,12,-5,4,-2))
io.out.crc32c_b := pattern(List(30,-27,23,-21,-20,-14,-13,12,-5 ,4,-2))
io.out.crc32c_h := pattern(List(30,-27,23,20,-14,-13,12,-5,4,-2))
io.out.crc32c_w := pattern(List(30,-27,23,21,-14,-13,12,-5,4,-2))
io.out.zbr := pattern(List(30,-27,24,-14,-13,12,-5,4,-2))
io.out.bfp := pattern(List(30,27,13,12,-6,5,-2))
io.out.zbf := pattern(List(30,27,13,12,-6,5,-2))
io.out.sh1add := pattern(List(29,-14,-12,-6,5,4,-2))
io.out.sh2add := pattern(List(29,14,-13,-12,5,4,-2))
io.out.sh3add := pattern(List(29,14,13,-6,5,-2))
io.out.zba := pattern(List(29,-12,-6,5,4,-2))
io.out.pm_alu := pattern(List(28,22,-13,-12,4)) | pattern(List(-30,-29,-27,-25,-6,4)) |
pattern(List(-29,-27,-25,-13,12,-6,4)) | pattern(List(-29,-27,-25,-14,-6,4)) |
pattern(List(13,-5,4)) | pattern(List(4,2)) | pattern(List(-12,-5,4))
io.out.legal := pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) |
pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)) |
pattern(List(-31,29,-28,-26,-25,24,-22,-20,-6,-5,4,-3,1,0)) | pattern(List(-31,29,-28,-26,-25,24,-22,-21,-6,-5,4,-3,1,0)) |
pattern(List(-31,29,-28,-26,-25,-23,-22,-20,-6,-5,4,-3,1,0)) | pattern(List(-31,29,-28,-26,-25,-24,-23,-21,-6,-5,4,-3,1,0)) |
pattern(List(-31,-30,-29,-28,-26,25,13,-6,4,-3,1,0)) | pattern(List(-31,-30,-28,-26,-25,-24,-6,-5,4,-3,1,0)) |
pattern(List(-31,-30,-28,-27,-26,-25,14,-12,-6,4,-3,1,0)) | pattern(List(-31,-30,-28,-27,-26,-25,13,-12,-6,4,-3,1,0)) |
pattern(List(-31,-29,-28,-27,-26,-25,-13,-12,-6,4,-3,1,0)) | pattern(List(-31,-28,-27,-26,-25,14,-6,-5,4,-3,1,0)) |
pattern(List(-31,-30,-29,-28,-26,-13,12,5,4,-3,-2,1,0)) | pattern(List(-31,-30,-29,-28,-26,14,-6,5,4,-3,1,0)) |
pattern(List(-31,30,-28,27,-26,-25,-13,12,-6,4,-3,1,0)) | pattern(List(-31,29,-28,27,-26,-25 ,-6,-5,4,-3,1,0)) |
pattern(List(-31,-30,-28,-27,-26,-25,-6,-5,4,-3,1,0)) | pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)) |
pattern(List(-14,-13,-12,6,5,-4,-3,1,0)) | pattern(List(-31,-29,-28,-26,-25,14,-6,5,4,-3,1,0)) |
pattern(List(-31,29,-28,-26,-25,-13,12,5,4,-3,-2,1,0)) | pattern(List(14,6,5,-4,-3,-2,1,0)) |
pattern(List(-14,-13,5,-4,-3,-2,1,0)) | pattern(List(-12,-6,-5,4,-3,1,0)) | pattern(List(-13,12,6,5,-3,-2,1,0)) |
pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) |
pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)) |
pattern(List(13,6,5,4,-3,-2,1,0)) | pattern(List(6,5,-4,3,2,1,0)) | pattern(List(-14,-12,-6,-4,-3,-2,1,0)) |
pattern(List(-13,-6,-5,-4,-3,-2,1,0)) | pattern(List(13,-6,-5,4,-3,1,0)) | pattern(List(-6,4,-3,2,1,0))
}
object dec_dec extends App {
(new chisel3.stage.ChiselStage).emitVerilog(new dec_dec_ctl())
}

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