Update README.md

Update beh_lib.sv
fusesoc wrapper added
2021-03-16 14:46:59 +05:00 · 2021-03-05 17:48:48 +05:00 · 2021-02-16 14:43:32 +05:00 · 2021-02-16 14:22:02 +05:00 · 2021-02-01 17:19:56 +05:00 · 2021-01-21 15:06:03 +05:00
784 changed files with 75417 additions and 11918 deletions
--- a/.idea/misc.xml
+++ b/.idea/misc.xml
@ -1,4 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<project version="4">
-  <component name="ProjectRootManager" version="2" languageLevel="JDK_1_8" default="false" project-jdk-name="11" project-jdk-type="JavaSDK" />
-</project>
--- a/EL2_IC_DATA.anno.json
+++ b/EL2_IC_DATA.anno.json
@ -1,18 +0,0 @@
-[
-  {
-    "class":"firrtl.EmitCircuitAnnotation",
-    "emitter":"firrtl.VerilogEmitter"
-  },
-  {
-    "class":"firrtl.options.TargetDirAnnotation",
-    "directory":"."
-  },
-  {
-    "class":"firrtl.options.OutputAnnotationFileAnnotation",
-    "file":"EL2_IC_DATA"
-  },
-  {
-    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
-    "targetDir":"."
-  }
-]
--- a/EL2_IC_DATA.fir
+++ b/EL2_IC_DATA.fir
@ -1,26 +0,0 @@
-;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
-circuit EL2_IC_DATA : 
-  module EL2_IC_DATA : 
-    input clock : Clock
-    input reset : UInt<1>
-    output io : {flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip ic_rw_addr : UInt<12>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, flip ic_debug_wr_data : UInt<71>, ic_debug_rd_data : UInt<71>, ic_parerr : UInt<2>, ic_eccerr : UInt<2>, flip ic_debug_addr : UInt<15>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_rd_hit : UInt<2>, flip scan_mode : UInt<1>, flip mask : UInt<1>[2][2]}
-    
-    smem ic_memory : UInt<26>[2][2][512], undefined @[el2_ifu_ic_mem.scala 209:30]
-    wire data : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 210:48]
-    data[0][0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 210:48]
-    data[0][1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 210:48]
-    data[1][0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 210:48]
-    data[1][1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 210:48]
-    wire mem_mask : UInt<1>[2] @[el2_ifu_ic_mem.scala 211:51]
-    mem_mask[0] <= UInt<1>("h01") @[el2_ifu_ic_mem.scala 211:51]
-    mem_mask[1] <= UInt<1>("h01") @[el2_ifu_ic_mem.scala 211:51]
-    wire mem_mask2 : UInt<1>[2][2] @[el2_ifu_ic_mem.scala 212:52]
-    mem_mask2[0][0] <= mem_mask[0] @[el2_ifu_ic_mem.scala 212:52]
-    mem_mask2[0][1] <= mem_mask[1] @[el2_ifu_ic_mem.scala 212:52]
-    mem_mask2[1][0] <= mem_mask[0] @[el2_ifu_ic_mem.scala 212:52]
-    mem_mask2[1][1] <= mem_mask[1] @[el2_ifu_ic_mem.scala 212:52]
-    io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 214:23]
-    io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 215:17]
-    io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 216:16]
-    io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 217:16]
-    
--- a/EL2_IC_DATA.v
+++ b/EL2_IC_DATA.v
@ -1,34 +0,0 @@
-module EL2_IC_DATA(
-  input         clock,
-  input         reset,
-  input         io_rst_l,
-  input         io_clk_override,
-  input  [11:0] io_ic_rw_addr,
-  input  [1:0]  io_ic_wr_en,
-  input         io_ic_rd_en,
-  input  [70:0] io_ic_wr_data_0,
-  input  [70:0] io_ic_wr_data_1,
-  output [63:0] io_ic_rd_data,
-  input  [70:0] io_ic_debug_wr_data,
-  output [70:0] io_ic_debug_rd_data,
-  output [1:0]  io_ic_parerr,
-  output [1:0]  io_ic_eccerr,
-  input  [14:0] io_ic_debug_addr,
-  input         io_ic_debug_rd_en,
-  input         io_ic_debug_wr_en,
-  input         io_ic_debug_tag_array,
-  input  [1:0]  io_ic_debug_way,
-  input  [63:0] io_ic_premux_data,
-  input         io_ic_sel_premux_data,
-  input  [1:0]  io_ic_rd_hit,
-  input         io_scan_mode,
-  input         io_mask_0_0,
-  input         io_mask_0_1,
-  input         io_mask_1_0,
-  input         io_mask_1_1
-);
-  assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 215:17]
-  assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 214:23]
-  assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 217:16]
-  assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 216:16]
-endmodule
--- a/EL2_IC_TAG.anno.json
+++ b/EL2_IC_TAG.anno.json
@ -1,93 +0,0 @@
-[
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_out_1",
-    "sources":[
-      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_0",
-    "sources":[
-      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_1",
-    "sources":[
-      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_rd_hit",
-    "sources":[
-      "~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_out_0",
-    "sources":[
-      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_perr",
-    "sources":[
-      "~EL2_IC_TAG|EL2_IC_TAG>io_ic_tag_valid",
-      "~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_0",
-      "~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_0",
-      "~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_1",
-      "~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_1",
-      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_data_out_1",
-    "sources":[
-      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_sb_out_0",
-    "sources":[
-      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_data_out_0",
-    "sources":[
-      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test_ecc_db_out_1",
-    "sources":[
-      "~EL2_IC_TAG|EL2_IC_TAG>io_dec_tlu_core_ecc_disable"
-    ]
-  },
-  {
-    "class":"firrtl.EmitCircuitAnnotation",
-    "emitter":"firrtl.VerilogEmitter"
-  },
-  {
-    "class":"firrtl.options.TargetDirAnnotation",
-    "directory":"."
-  },
-  {
-    "class":"firrtl.options.OutputAnnotationFileAnnotation",
-    "file":"EL2_IC_TAG"
-  },
-  {
-    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
-    "targetDir":"."
-  }
-]
--- a/EL2_IC_TAG.fir
+++ b/EL2_IC_TAG.fir
--- a/EL2_IC_TAG.v
+++ b/EL2_IC_TAG.v
@ -1,384 +0,0 @@
-module rvecc_decode(
-  input  [31:0] io_din,
-  input  [6:0]  io_ecc_in,
-  output [6:0]  io_ecc_out,
-  output [31:0] io_dout,
-  output        io_single_ecc_error
-);
-  wire  w0_0 = io_din[0]; // @[beh_lib.scala 239:37]
-  wire  w0_1 = io_din[1]; // @[beh_lib.scala 239:37]
-  wire  w1_1 = io_din[2]; // @[beh_lib.scala 240:37]
-  wire  w0_2 = io_din[3]; // @[beh_lib.scala 239:37]
-  wire  w0_3 = io_din[4]; // @[beh_lib.scala 239:37]
-  wire  w1_3 = io_din[5]; // @[beh_lib.scala 240:37]
-  wire  w0_4 = io_din[6]; // @[beh_lib.scala 239:37]
-  wire  w2_3 = io_din[7]; // @[beh_lib.scala 241:37]
-  wire  w0_5 = io_din[8]; // @[beh_lib.scala 239:37]
-  wire  w1_5 = io_din[9]; // @[beh_lib.scala 240:37]
-  wire  w0_6 = io_din[10]; // @[beh_lib.scala 239:37]
-  wire  w0_7 = io_din[11]; // @[beh_lib.scala 239:37]
-  wire  w1_7 = io_din[12]; // @[beh_lib.scala 240:37]
-  wire  w0_8 = io_din[13]; // @[beh_lib.scala 239:37]
-  wire  w2_7 = io_din[14]; // @[beh_lib.scala 241:37]
-  wire  w0_9 = io_din[15]; // @[beh_lib.scala 239:37]
-  wire  w1_9 = io_din[16]; // @[beh_lib.scala 240:37]
-  wire  w0_10 = io_din[17]; // @[beh_lib.scala 239:37]
-  wire  w3_7 = io_din[18]; // @[beh_lib.scala 242:37]
-  wire  w0_11 = io_din[19]; // @[beh_lib.scala 239:37]
-  wire  w1_11 = io_din[20]; // @[beh_lib.scala 240:37]
-  wire  w0_12 = io_din[21]; // @[beh_lib.scala 239:37]
-  wire  w2_11 = io_din[22]; // @[beh_lib.scala 241:37]
-  wire  w0_13 = io_din[23]; // @[beh_lib.scala 239:37]
-  wire  w1_13 = io_din[24]; // @[beh_lib.scala 240:37]
-  wire  w0_14 = io_din[25]; // @[beh_lib.scala 239:37]
-  wire  w0_15 = io_din[26]; // @[beh_lib.scala 239:37]
-  wire  w1_15 = io_din[27]; // @[beh_lib.scala 240:37]
-  wire  w0_16 = io_din[28]; // @[beh_lib.scala 239:37]
-  wire  w2_15 = io_din[29]; // @[beh_lib.scala 241:37]
-  wire  w0_17 = io_din[30]; // @[beh_lib.scala 239:37]
-  wire  w1_17 = io_din[31]; // @[beh_lib.scala 240:37]
-  wire [5:0] _T_100 = {w1_17,w0_17,w2_15,w0_16,w1_15,w0_15}; // @[beh_lib.scala 247:86]
-  wire  _T_101 = ^_T_100; // @[beh_lib.scala 247:93]
-  wire  _T_102 = io_ecc_in[5] ^ _T_101; // @[beh_lib.scala 247:81]
-  wire [6:0] _T_109 = {w0_10,w1_9,w0_9,w2_7,w0_8,w1_7,w0_7}; // @[beh_lib.scala 247:116]
-  wire [14:0] _T_117 = {w0_14,w1_13,w0_13,w2_11,w0_12,w1_11,w0_11,w3_7,_T_109}; // @[beh_lib.scala 247:116]
-  wire  _T_118 = ^_T_117; // @[beh_lib.scala 247:123]
-  wire  _T_119 = io_ecc_in[4] ^ _T_118; // @[beh_lib.scala 247:111]
-  wire [6:0] _T_126 = {w0_6,w1_5,w0_5,w2_3,w0_4,w1_3,w0_3}; // @[beh_lib.scala 247:146]
-  wire [14:0] _T_134 = {w0_14,w1_13,w0_13,w2_11,w0_12,w1_11,w0_11,w3_7,_T_126}; // @[beh_lib.scala 247:146]
-  wire  _T_135 = ^_T_134; // @[beh_lib.scala 247:153]
-  wire  _T_136 = io_ecc_in[3] ^ _T_135; // @[beh_lib.scala 247:141]
-  wire [8:0] _T_145 = {w0_9,w2_7,w0_6,w1_5,w0_5,w2_3,w0_2,w1_1,w0_1}; // @[beh_lib.scala 247:176]
-  wire [17:0] _T_154 = {w1_17,w0_17,w2_15,w0_14,w1_13,w0_13,w2_11,w0_10,w1_9,_T_145}; // @[beh_lib.scala 247:176]
-  wire  _T_155 = ^_T_154; // @[beh_lib.scala 247:183]
-  wire  _T_156 = io_ecc_in[2] ^ _T_155; // @[beh_lib.scala 247:171]
-  wire [8:0] _T_165 = {w0_8,w1_7,w0_6,w1_5,w0_4,w1_3,w0_2,w1_1,w0_0}; // @[beh_lib.scala 247:206]
-  wire [17:0] _T_174 = {w1_17,w0_16,w1_15,w0_14,w1_13,w0_12,w1_11,w0_10,w1_9,_T_165}; // @[beh_lib.scala 247:206]
-  wire  _T_175 = ^_T_174; // @[beh_lib.scala 247:213]
-  wire  _T_176 = io_ecc_in[1] ^ _T_175; // @[beh_lib.scala 247:201]
-  wire [8:0] _T_185 = {w0_8,w0_7,w0_6,w0_5,w0_4,w0_3,w0_2,w0_1,w0_0}; // @[beh_lib.scala 247:236]
-  wire [17:0] _T_194 = {w0_17,w0_16,w0_15,w0_14,w0_13,w0_12,w0_11,w0_10,w0_9,_T_185}; // @[beh_lib.scala 247:236]
-  wire  _T_195 = ^_T_194; // @[beh_lib.scala 247:243]
-  wire  _T_196 = io_ecc_in[0] ^ _T_195; // @[beh_lib.scala 247:231]
-  wire [6:0] ecc_check = {1'h0,_T_102,_T_119,_T_136,_T_156,_T_176,_T_196}; // @[Cat.scala 29:58]
-  wire  error_mask_0 = ecc_check[5:0] == 6'h1; // @[beh_lib.scala 255:39]
-  wire  error_mask_1 = ecc_check[5:0] == 6'h2; // @[beh_lib.scala 255:39]
-  wire  error_mask_2 = ecc_check[5:0] == 6'h3; // @[beh_lib.scala 255:39]
-  wire  error_mask_3 = ecc_check[5:0] == 6'h4; // @[beh_lib.scala 255:39]
-  wire  error_mask_4 = ecc_check[5:0] == 6'h5; // @[beh_lib.scala 255:39]
-  wire  error_mask_5 = ecc_check[5:0] == 6'h6; // @[beh_lib.scala 255:39]
-  wire  error_mask_6 = ecc_check[5:0] == 6'h7; // @[beh_lib.scala 255:39]
-  wire  error_mask_7 = ecc_check[5:0] == 6'h8; // @[beh_lib.scala 255:39]
-  wire  error_mask_8 = ecc_check[5:0] == 6'h9; // @[beh_lib.scala 255:39]
-  wire  error_mask_9 = ecc_check[5:0] == 6'ha; // @[beh_lib.scala 255:39]
-  wire  error_mask_10 = ecc_check[5:0] == 6'hb; // @[beh_lib.scala 255:39]
-  wire  error_mask_11 = ecc_check[5:0] == 6'hc; // @[beh_lib.scala 255:39]
-  wire  error_mask_12 = ecc_check[5:0] == 6'hd; // @[beh_lib.scala 255:39]
-  wire  error_mask_13 = ecc_check[5:0] == 6'he; // @[beh_lib.scala 255:39]
-  wire  error_mask_14 = ecc_check[5:0] == 6'hf; // @[beh_lib.scala 255:39]
-  wire  error_mask_15 = ecc_check[5:0] == 6'h10; // @[beh_lib.scala 255:39]
-  wire  error_mask_16 = ecc_check[5:0] == 6'h11; // @[beh_lib.scala 255:39]
-  wire  error_mask_17 = ecc_check[5:0] == 6'h12; // @[beh_lib.scala 255:39]
-  wire  error_mask_18 = ecc_check[5:0] == 6'h13; // @[beh_lib.scala 255:39]
-  wire  error_mask_19 = ecc_check[5:0] == 6'h14; // @[beh_lib.scala 255:39]
-  wire  error_mask_20 = ecc_check[5:0] == 6'h15; // @[beh_lib.scala 255:39]
-  wire  error_mask_21 = ecc_check[5:0] == 6'h16; // @[beh_lib.scala 255:39]
-  wire  error_mask_22 = ecc_check[5:0] == 6'h17; // @[beh_lib.scala 255:39]
-  wire  error_mask_23 = ecc_check[5:0] == 6'h18; // @[beh_lib.scala 255:39]
-  wire  error_mask_24 = ecc_check[5:0] == 6'h19; // @[beh_lib.scala 255:39]
-  wire  error_mask_25 = ecc_check[5:0] == 6'h1a; // @[beh_lib.scala 255:39]
-  wire  error_mask_26 = ecc_check[5:0] == 6'h1b; // @[beh_lib.scala 255:39]
-  wire  error_mask_27 = ecc_check[5:0] == 6'h1c; // @[beh_lib.scala 255:39]
-  wire  error_mask_28 = ecc_check[5:0] == 6'h1d; // @[beh_lib.scala 255:39]
-  wire  error_mask_29 = ecc_check[5:0] == 6'h1e; // @[beh_lib.scala 255:39]
-  wire  error_mask_30 = ecc_check[5:0] == 6'h1f; // @[beh_lib.scala 255:39]
-  wire  error_mask_31 = ecc_check[5:0] == 6'h20; // @[beh_lib.scala 255:39]
-  wire  error_mask_32 = ecc_check[5:0] == 6'h21; // @[beh_lib.scala 255:39]
-  wire  error_mask_33 = ecc_check[5:0] == 6'h22; // @[beh_lib.scala 255:39]
-  wire  error_mask_34 = ecc_check[5:0] == 6'h23; // @[beh_lib.scala 255:39]
-  wire  error_mask_35 = ecc_check[5:0] == 6'h24; // @[beh_lib.scala 255:39]
-  wire  error_mask_36 = ecc_check[5:0] == 6'h25; // @[beh_lib.scala 255:39]
-  wire  error_mask_37 = ecc_check[5:0] == 6'h26; // @[beh_lib.scala 255:39]
-  wire  error_mask_38 = ecc_check[5:0] == 6'h27; // @[beh_lib.scala 255:39]
-  wire [7:0] _T_310 = {io_ecc_in[3],io_din[3:1],io_ecc_in[2],w0_0,io_ecc_in[1:0]}; // @[Cat.scala 29:58]
-  wire [38:0] din_plus_parity = {io_ecc_in[6],io_din[31:26],io_ecc_in[5],io_din[25:11],io_ecc_in[4],io_din[10:4],_T_310}; // @[Cat.scala 29:58]
-  wire [9:0] _T_333 = {error_mask_18,error_mask_17,error_mask_16,error_mask_15,error_mask_14,error_mask_13,error_mask_12,error_mask_11,error_mask_10,error_mask_9}; // @[beh_lib.scala 258:70]
-  wire [18:0] _T_334 = {_T_333,error_mask_8,error_mask_7,error_mask_6,error_mask_5,error_mask_4,error_mask_3,error_mask_2,error_mask_1,error_mask_0}; // @[beh_lib.scala 258:70]
-  wire [9:0] _T_343 = {error_mask_28,error_mask_27,error_mask_26,error_mask_25,error_mask_24,error_mask_23,error_mask_22,error_mask_21,error_mask_20,error_mask_19}; // @[beh_lib.scala 258:70]
-  wire [9:0] _T_352 = {error_mask_38,error_mask_37,error_mask_36,error_mask_35,error_mask_34,error_mask_33,error_mask_32,error_mask_31,error_mask_30,error_mask_29}; // @[beh_lib.scala 258:70]
-  wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[beh_lib.scala 258:70]
-  wire [38:0] _T_355 = _T_354 ^ din_plus_parity; // @[beh_lib.scala 258:77]
-  wire [38:0] dout_plus_parity = io_single_ecc_error ? _T_355 : din_plus_parity; // @[beh_lib.scala 258:29]
-  wire [3:0] _T_361 = {dout_plus_parity[6:4],dout_plus_parity[2]}; // @[Cat.scala 29:58]
-  wire [27:0] _T_363 = {dout_plus_parity[37:32],dout_plus_parity[30:16],dout_plus_parity[14:8]}; // @[Cat.scala 29:58]
-  wire  _T_367 = ecc_check == 7'h40; // @[beh_lib.scala 261:60]
-  wire  _T_368 = dout_plus_parity[38] ^ _T_367; // @[beh_lib.scala 261:42]
-  wire [3:0] _T_375 = {dout_plus_parity[7],dout_plus_parity[3],dout_plus_parity[1:0]}; // @[Cat.scala 29:58]
-  wire [2:0] _T_377 = {_T_368,dout_plus_parity[31],dout_plus_parity[15]}; // @[Cat.scala 29:58]
-  assign io_ecc_out = {_T_377,_T_375}; // @[beh_lib.scala 248:14 beh_lib.scala 261:14]
-  assign io_dout = {_T_363,_T_361}; // @[beh_lib.scala 260:11]
-  assign io_single_ecc_error = 1'h0; // @[beh_lib.scala 250:23]
-endmodule
-module EL2_IC_TAG(
-  input         clock,
-  input         reset,
-  input         io_clk,
-  input         io_rst_l,
-  input         io_clk_override,
-  input         io_dec_tlu_core_ecc_disable,
-  input  [31:0] io_ic_rw_addr,
-  input  [1:0]  io_ic_wr_en,
-  input  [1:0]  io_ic_tag_valid,
-  input         io_ic_rd_en,
-  input  [12:0] io_ic_debug_addr,
-  input         io_ic_debug_rd_en,
-  input         io_ic_debug_wr_en,
-  input         io_ic_debug_tag_array,
-  input  [1:0]  io_ic_debug_way,
-  output [25:0] io_ictag_debug_rd_data,
-  input  [70:0] io_ic_debug_wr_data,
-  output [1:0]  io_ic_rd_hit,
-  output        io_ic_tag_perr,
-  input         io_scan_mode,
-  output [25:0] io_test,
-  output [31:0] io_test_ecc_data_out_0,
-  output [31:0] io_test_ecc_data_out_1,
-  output [6:0]  io_test_ecc_out_0,
-  output [6:0]  io_test_ecc_out_1,
-  output        io_test_ecc_sb_out_0,
-  output        io_test_ecc_sb_out_1,
-  output        io_test_ecc_db_out_0,
-  output        io_test_ecc_db_out_1
-);
-`ifdef RANDOMIZE_MEM_INIT
-  reg [31:0] _RAND_0;
-  reg [31:0] _RAND_2;
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
-  reg [31:0] _RAND_1;
-  reg [31:0] _RAND_3;
-  reg [31:0] _RAND_4;
-  reg [31:0] _RAND_5;
-`endif // RANDOMIZE_REG_INIT
-  reg [25:0] ic_way_tag_0 [0:127]; // @[el2_ifu_ic_mem.scala 125:46]
-  wire [25:0] ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 125:46]
-  wire [6:0] ic_way_tag_0_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 125:46]
-  wire [25:0] ic_way_tag_0__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
-  wire [6:0] ic_way_tag_0__T_487_addr; // @[el2_ifu_ic_mem.scala 125:46]
-  wire  ic_way_tag_0__T_487_mask; // @[el2_ifu_ic_mem.scala 125:46]
-  wire  ic_way_tag_0__T_487_en; // @[el2_ifu_ic_mem.scala 125:46]
-  reg [6:0] ic_way_tag_0_ic_tag_data_raw_addr_pipe_0;
-  reg [25:0] ic_way_tag_1 [0:127]; // @[el2_ifu_ic_mem.scala 125:46]
-  wire [25:0] ic_way_tag_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 125:46]
-  wire [6:0] ic_way_tag_1_ic_tag_data_raw_addr; // @[el2_ifu_ic_mem.scala 125:46]
-  wire [25:0] ic_way_tag_1__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
-  wire [6:0] ic_way_tag_1__T_487_addr; // @[el2_ifu_ic_mem.scala 125:46]
-  wire  ic_way_tag_1__T_487_mask; // @[el2_ifu_ic_mem.scala 125:46]
-  wire  ic_way_tag_1__T_487_en; // @[el2_ifu_ic_mem.scala 125:46]
-  reg [6:0] ic_way_tag_1_ic_tag_data_raw_addr_pipe_0;
-  wire [31:0] rvecc_decode_io_din; // @[el2_ifu_ic_mem.scala 149:27]
-  wire [6:0] rvecc_decode_io_ecc_in; // @[el2_ifu_ic_mem.scala 149:27]
-  wire [6:0] rvecc_decode_io_ecc_out; // @[el2_ifu_ic_mem.scala 149:27]
-  wire [31:0] rvecc_decode_io_dout; // @[el2_ifu_ic_mem.scala 149:27]
-  wire  rvecc_decode_io_single_ecc_error; // @[el2_ifu_ic_mem.scala 149:27]
-  wire [31:0] rvecc_decode_1_io_din; // @[el2_ifu_ic_mem.scala 149:27]
-  wire [6:0] rvecc_decode_1_io_ecc_in; // @[el2_ifu_ic_mem.scala 149:27]
-  wire [6:0] rvecc_decode_1_io_ecc_out; // @[el2_ifu_ic_mem.scala 149:27]
-  wire [31:0] rvecc_decode_1_io_dout; // @[el2_ifu_ic_mem.scala 149:27]
-  wire  rvecc_decode_1_io_single_ecc_error; // @[el2_ifu_ic_mem.scala 149:27]
-  wire  _T_2 = io_ic_rw_addr[5:4] == 2'h1; // @[el2_ifu_ic_mem.scala 73:93]
-  wire [1:0] _T_4 = {_T_2,_T_2}; // @[Cat.scala 29:58]
-  wire [1:0] ic_tag_wren = io_ic_wr_en & _T_4; // @[el2_ifu_ic_mem.scala 73:33]
-  wire  _T_5 = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 75:68]
-  wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
-  wire [1:0] ic_debug_rd_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 75:93]
-  wire  _T_8 = io_ic_debug_wr_en & io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 76:68]
-  wire [1:0] _T_10 = {_T_8,_T_8}; // @[Cat.scala 29:58]
-  wire [1:0] ic_debug_wr_way_en = _T_10 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 76:93]
-  wire  _T_11 = io_ic_rd_en | io_clk_override; // @[el2_ifu_ic_mem.scala 77:55]
-  wire [1:0] _T_13 = {_T_11,_T_11}; // @[Cat.scala 29:58]
-  wire [1:0] _T_14 = _T_13 | io_ic_wr_en; // @[el2_ifu_ic_mem.scala 77:74]
-  wire [1:0] _T_15 = _T_14 | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 77:88]
-  wire [1:0] ic_tag_clken = _T_15 | ic_debug_rd_way_en; // @[el2_ifu_ic_mem.scala 77:109]
-  reg [31:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 80:30]
-  wire [1:0] ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en; // @[el2_ifu_ic_mem.scala 82:35]
-  wire [31:0] _T_30 = {13'h0,io_ic_rw_addr[31:13]}; // @[Cat.scala 29:58]
-  wire [8:0] _T_134 = {_T_30[16],_T_30[14],_T_30[12],_T_30[10],_T_30[8],_T_30[6],_T_30[5],_T_30[3],_T_30[1]}; // @[el2_lib.scala 211:22]
-  wire [17:0] _T_143 = {_T_30[31],_T_30[30],_T_30[28],_T_30[27],_T_30[25],_T_30[23],_T_30[21],_T_30[20],_T_30[18],_T_134}; // @[el2_lib.scala 211:22]
-  wire  _T_144 = ^_T_143; // @[el2_lib.scala 211:29]
-  wire [8:0] _T_152 = {_T_30[15],_T_30[14],_T_30[11],_T_30[10],_T_30[7],_T_30[6],_T_30[4],_T_30[3],_T_30[0]}; // @[el2_lib.scala 211:39]
-  wire [17:0] _T_161 = {_T_30[31],_T_30[29],_T_30[28],_T_30[26],_T_30[25],_T_30[22],_T_30[21],_T_30[19],_T_30[18],_T_152}; // @[el2_lib.scala 211:39]
-  wire  _T_162 = ^_T_161; // @[el2_lib.scala 211:46]
-  wire [8:0] _T_170 = {_T_30[15],_T_30[14],_T_30[9],_T_30[8],_T_30[7],_T_30[6],_T_30[2],_T_30[1],_T_30[0]}; // @[el2_lib.scala 211:56]
-  wire [17:0] _T_179 = {_T_30[30],_T_30[29],_T_30[28],_T_30[24],_T_30[23],_T_30[22],_T_30[21],_T_30[17],_T_30[16],_T_170}; // @[el2_lib.scala 211:56]
-  wire  _T_180 = ^_T_179; // @[el2_lib.scala 211:63]
-  wire [6:0] _T_186 = {_T_30[12],_T_30[11],_T_30[10],_T_30[9],_T_30[8],_T_30[7],_T_30[6]}; // @[el2_lib.scala 211:73]
-  wire [14:0] _T_194 = {_T_30[27],_T_30[26],_T_30[25],_T_30[24],_T_30[23],_T_30[22],_T_30[21],_T_30[13],_T_186}; // @[el2_lib.scala 211:73]
-  wire  _T_195 = ^_T_194; // @[el2_lib.scala 211:80]
-  wire [14:0] _T_209 = {_T_30[20],_T_30[19],_T_30[18],_T_30[17],_T_30[16],_T_30[15],_T_30[14],_T_30[13],_T_186}; // @[el2_lib.scala 211:90]
-  wire  _T_210 = ^_T_209; // @[el2_lib.scala 211:97]
-  wire [5:0] _T_215 = {_T_30[5],_T_30[4],_T_30[3],_T_30[2],_T_30[1],_T_30[0]}; // @[el2_lib.scala 211:107]
-  wire  _T_216 = ^_T_215; // @[el2_lib.scala 211:114]
-  wire [5:0] _T_221 = {_T_144,_T_162,_T_180,_T_195,_T_210,_T_216}; // @[Cat.scala 29:58]
-  wire  _T_222 = ^_T_30; // @[el2_lib.scala 212:13]
-  wire  _T_223 = ^_T_221; // @[el2_lib.scala 212:23]
-  wire  _T_224 = _T_222 ^ _T_223; // @[el2_lib.scala 212:18]
-  wire [6:0] _T_225 = {_T_224,_T_144,_T_162,_T_180,_T_195,_T_210,_T_216}; // @[Cat.scala 29:58]
-  wire [25:0] _T_229 = {io_ic_debug_wr_data[68:64],io_ic_debug_wr_data[31:11]}; // @[Cat.scala 29:58]
-  wire [25:0] _T_463 = {_T_225[4:0],2'h0,io_ic_rw_addr[31:13]}; // @[Cat.scala 29:58]
-  wire  _T_478 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 119:44]
-  reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 123:38]
-  wire [25:0] _GEN_17 = ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 137:75]
-  wire [25:0] _GEN_18 = ic_way_tag_0_ic_tag_data_raw_data[0] ? ic_way_tag_1_ic_tag_data_raw_data : _GEN_17; // @[el2_ifu_ic_mem.scala 137:75]
-  wire [36:0] w_tout_0 = {_GEN_18[25:21],_GEN_18[18:0],13'h0}; // @[Cat.scala 29:58]
-  wire [25:0] _GEN_22 = ic_way_tag_1_ic_tag_data_raw_data[0] ? ic_way_tag_1_ic_tag_data_raw_data : _GEN_17; // @[el2_ifu_ic_mem.scala 137:75]
-  wire [36:0] w_tout_1 = {_GEN_22[25:21],_GEN_22[18:0],13'h0}; // @[Cat.scala 29:58]
-  wire  ic_tag_way_perr_0 = io_test_ecc_sb_out_0 | io_test_ecc_db_out_0; // @[el2_ifu_ic_mem.scala 165:54]
-  wire  ic_tag_way_perr_1 = io_test_ecc_sb_out_1 | io_test_ecc_db_out_1; // @[el2_ifu_ic_mem.scala 165:54]
-  wire [9:0] _T_533 = {ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
-  wire [18:0] _T_542 = {_T_533,ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
-  wire [25:0] _T_549 = {_T_542,ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0],ic_debug_rd_way_en_ff[0]}; // @[Cat.scala 29:58]
-  wire [25:0] _T_550 = _T_549 & ic_way_tag_0_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 168:75]
-  wire [9:0] _T_561 = {ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
-  wire [18:0] _T_570 = {_T_561,ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
-  wire [25:0] _T_577 = {_T_570,ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1],ic_debug_rd_way_en_ff[1]}; // @[Cat.scala 29:58]
-  wire [25:0] _T_578 = _T_577 & ic_way_tag_1_ic_tag_data_raw_data; // @[el2_ifu_ic_mem.scala 168:75]
-  wire [36:0] _T_636 = w_tout_0 & w_tout_1; // @[el2_ifu_ic_mem.scala 176:31]
-  wire [1:0] _T_637 = {ic_tag_way_perr_0,ic_tag_way_perr_1}; // @[Cat.scala 29:58]
-  wire [1:0] _T_638 = _T_637 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 177:55]
-  wire  _T_642 = w_tout_0[31:13] == ic_rw_addr_ff[31:13]; // @[el2_ifu_ic_mem.scala 179:88]
-  wire [1:0] _GEN_25 = {{1'd0}, _T_642}; // @[el2_ifu_ic_mem.scala 179:133]
-  wire [1:0] _T_643 = _GEN_25 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 179:133]
-  wire  _T_646 = w_tout_1[31:13] == ic_rw_addr_ff[31:13]; // @[el2_ifu_ic_mem.scala 179:88]
-  wire [1:0] _GEN_26 = {{1'd0}, _T_646}; // @[el2_ifu_ic_mem.scala 179:133]
-  wire [1:0] _T_647 = _GEN_26 & io_ic_tag_valid; // @[el2_ifu_ic_mem.scala 179:133]
-  wire [3:0] _T_649 = {_T_643,_T_647}; // @[Cat.scala 29:58]
-  rvecc_decode rvecc_decode ( // @[el2_ifu_ic_mem.scala 149:27]
-    .io_din(rvecc_decode_io_din),
-    .io_ecc_in(rvecc_decode_io_ecc_in),
-    .io_ecc_out(rvecc_decode_io_ecc_out),
-    .io_dout(rvecc_decode_io_dout),
-    .io_single_ecc_error(rvecc_decode_io_single_ecc_error)
-  );
-  rvecc_decode rvecc_decode_1 ( // @[el2_ifu_ic_mem.scala 149:27]
-    .io_din(rvecc_decode_1_io_din),
-    .io_ecc_in(rvecc_decode_1_io_ecc_in),
-    .io_ecc_out(rvecc_decode_1_io_ecc_out),
-    .io_dout(rvecc_decode_1_io_dout),
-    .io_single_ecc_error(rvecc_decode_1_io_single_ecc_error)
-  );
-  assign ic_way_tag_0_ic_tag_data_raw_addr = ic_way_tag_0_ic_tag_data_raw_addr_pipe_0;
-  assign ic_way_tag_0_ic_tag_data_raw_data = ic_way_tag_0[ic_way_tag_0_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 125:46]
-  assign ic_way_tag_0__T_487_data = _T_8 ? _T_229 : _T_463;
-  assign ic_way_tag_0__T_487_addr = _T_478 ? io_ic_debug_addr[12:6] : io_ic_rw_addr[12:6];
-  assign ic_way_tag_0__T_487_mask = ic_tag_wren_q[0] & ic_tag_clken[0];
-  assign ic_way_tag_0__T_487_en = 1'h1;
-  assign ic_way_tag_1_ic_tag_data_raw_addr = ic_way_tag_1_ic_tag_data_raw_addr_pipe_0;
-  assign ic_way_tag_1_ic_tag_data_raw_data = ic_way_tag_1[ic_way_tag_1_ic_tag_data_raw_addr]; // @[el2_ifu_ic_mem.scala 125:46]
-  assign ic_way_tag_1__T_487_data = _T_8 ? _T_229 : _T_463;
-  assign ic_way_tag_1__T_487_addr = _T_478 ? io_ic_debug_addr[12:6] : io_ic_rw_addr[12:6];
-  assign ic_way_tag_1__T_487_mask = ic_tag_wren_q[1] & ic_tag_clken[1];
-  assign ic_way_tag_1__T_487_en = 1'h1;
-  assign io_ictag_debug_rd_data = _T_550 | _T_578; // @[el2_ifu_ic_mem.scala 175:26]
-  assign io_ic_rd_hit = _T_649[1:0]; // @[el2_ifu_ic_mem.scala 179:16]
-  assign io_ic_tag_perr = |_T_638; // @[el2_ifu_ic_mem.scala 177:18]
-  assign io_test = _T_636[25:0]; // @[el2_ifu_ic_mem.scala 176:13]
-  assign io_test_ecc_data_out_0 = rvecc_decode_io_dout; // @[el2_ifu_ic_mem.scala 160:29]
-  assign io_test_ecc_data_out_1 = rvecc_decode_1_io_dout; // @[el2_ifu_ic_mem.scala 160:29]
-  assign io_test_ecc_out_0 = rvecc_decode_io_ecc_out; // @[el2_ifu_ic_mem.scala 161:24]
-  assign io_test_ecc_out_1 = rvecc_decode_1_io_ecc_out; // @[el2_ifu_ic_mem.scala 161:24]
-  assign io_test_ecc_sb_out_0 = 1'h0; // @[el2_ifu_ic_mem.scala 162:27]
-  assign io_test_ecc_sb_out_1 = 1'h0; // @[el2_ifu_ic_mem.scala 162:27]
-  assign io_test_ecc_db_out_0 = 1'h0; // @[el2_ifu_ic_mem.scala 163:27]
-  assign io_test_ecc_db_out_1 = 1'h0; // @[el2_ifu_ic_mem.scala 163:27]
-  assign rvecc_decode_io_din = {11'h0,ic_way_tag_0_ic_tag_data_raw_data[20:0]}; // @[el2_ifu_ic_mem.scala 152:26]
-  assign rvecc_decode_io_ecc_in = {2'h0,ic_way_tag_0_ic_tag_data_raw_data[25:21]}; // @[el2_ifu_ic_mem.scala 153:29]
-  assign rvecc_decode_1_io_din = {11'h0,ic_way_tag_1_ic_tag_data_raw_data[20:0]}; // @[el2_ifu_ic_mem.scala 152:26]
-  assign rvecc_decode_1_io_ecc_in = {2'h0,ic_way_tag_1_ic_tag_data_raw_data[25:21]}; // @[el2_ifu_ic_mem.scala 153:29]
-`ifdef RANDOMIZE_GARBAGE_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_INVALID_ASSIGN
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_REG_INIT
-`define RANDOMIZE
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-`define RANDOMIZE
-`endif
-`ifndef RANDOM
-`define RANDOM $random
-`endif
-`ifdef RANDOMIZE_MEM_INIT
-  integer initvar;
-`endif
-`ifndef SYNTHESIS
-`ifdef FIRRTL_BEFORE_INITIAL
-`FIRRTL_BEFORE_INITIAL
-`endif
-initial begin
-  `ifdef RANDOMIZE
-    `ifdef INIT_RANDOM
-      `INIT_RANDOM
-    `endif
-    `ifndef VERILATOR
-      `ifdef RANDOMIZE_DELAY
-        #`RANDOMIZE_DELAY begin end
-      `else
-        #0.002 begin end
-      `endif
-    `endif
-`ifdef RANDOMIZE_MEM_INIT
-  _RAND_0 = {1{`RANDOM}};
-  for (initvar = 0; initvar < 128; initvar = initvar+1)
-    ic_way_tag_0[initvar] = _RAND_0[25:0];
-  _RAND_2 = {1{`RANDOM}};
-  for (initvar = 0; initvar < 128; initvar = initvar+1)
-    ic_way_tag_1[initvar] = _RAND_2[25:0];
-`endif // RANDOMIZE_MEM_INIT
-`ifdef RANDOMIZE_REG_INIT
-  _RAND_1 = {1{`RANDOM}};
-  ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 = _RAND_1[6:0];
-  _RAND_3 = {1{`RANDOM}};
-  ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 = _RAND_3[6:0];
-  _RAND_4 = {1{`RANDOM}};
-  ic_rw_addr_ff = _RAND_4[31:0];
-  _RAND_5 = {1{`RANDOM}};
-  ic_debug_rd_way_en_ff = _RAND_5[1:0];
-`endif // RANDOMIZE_REG_INIT
-  `endif // RANDOMIZE
-end // initial
-`ifdef FIRRTL_AFTER_INITIAL
-`FIRRTL_AFTER_INITIAL
-`endif
-`endif // SYNTHESIS
-  always @(posedge clock) begin
-    if(ic_way_tag_0__T_487_en & ic_way_tag_0__T_487_mask) begin
-      ic_way_tag_0[ic_way_tag_0__T_487_addr] <= ic_way_tag_0__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
-    end
-    if (_T_478) begin
-      ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 <= io_ic_debug_addr[12:6];
-    end else begin
-      ic_way_tag_0_ic_tag_data_raw_addr_pipe_0 <= io_ic_rw_addr[12:6];
-    end
-    if(ic_way_tag_1__T_487_en & ic_way_tag_1__T_487_mask) begin
-      ic_way_tag_1[ic_way_tag_1__T_487_addr] <= ic_way_tag_1__T_487_data; // @[el2_ifu_ic_mem.scala 125:46]
-    end
-    if (_T_478) begin
-      ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 <= io_ic_debug_addr[12:6];
-    end else begin
-      ic_way_tag_1_ic_tag_data_raw_addr_pipe_0 <= io_ic_rw_addr[12:6];
-    end
-    if (reset) begin
-      ic_rw_addr_ff <= 32'h0;
-    end else begin
-      ic_rw_addr_ff <= io_ic_rw_addr;
-    end
-    if (reset) begin
-      ic_debug_rd_way_en_ff <= 2'h0;
-    end else begin
-      ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
-    end
-  end
-endmodule
--- a/InoutPort.v
+++ b/InoutPort.v
@ -1,9 +0,0 @@
-
-module InoutPort( inout [15:0] a,
-                  input [15:0] b,
-                  input        sel,
-                  output [15:0] c);
-  assign a = sel ? 'bz : b;
-  assign c = sel ? a : 'bz;
-endmodule
-    
--- a/MakeInout.anno.json
+++ b/MakeInout.anno.json
@ -1,24 +0,0 @@
-[
-  {
-    "class":"firrtl.EmitCircuitAnnotation",
-    "emitter":"firrtl.VerilogEmitter"
-  },
-  {
-    "class":"firrtl.transforms.BlackBoxInlineAnno",
-    "target":"MakeInout.rvdff",
-    "name":"rvdff.v",
-    "text":"\nmodule InoutPort( input [15:0] in,\n                  input clk,\n                  input reset,\n                  output [15:0] out);\n  always@(posedge clk or negedge reset)\n  begin\n  if(reset == 0)\n  out <= 0;\n  else\n  out <= in\n  end\nendmodule\n    "
-  },
-  {
-    "class":"firrtl.options.TargetDirAnnotation",
-    "directory":"."
-  },
-  {
-    "class":"firrtl.options.OutputAnnotationFileAnnotation",
-    "file":"MakeInout"
-  },
-  {
-    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
-    "targetDir":"."
-  }
-]
--- a/MakeInout.fir
+++ b/MakeInout.fir
@ -1,26 +0,0 @@
-;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
-circuit MakeInout : 
-  extmodule rvdff : 
-    input in : UInt<16>
-    input clk : Clock
-    input reset : UInt<1>
-    output out : UInt<16>
-    
-    defname = rvdff
-    
-    
-  module MakeInout : 
-    input clock : Clock
-    input reset : UInt<1>
-    output io : {flip in : UInt<16>, flip clk : Clock, flip reset : UInt<1>, out : UInt<16>}
-    
-    inst m of rvdff @[GCD.scala 40:17]
-    m.out is invalid
-    m.reset is invalid
-    m.clk is invalid
-    m.in is invalid
-    io.out <= m.out @[GCD.scala 42:8]
-    m.reset <= io.reset @[GCD.scala 42:8]
-    m.clk <= io.clk @[GCD.scala 42:8]
-    m.in <= io.in @[GCD.scala 42:8]
-    
--- a/MakeInout.v
+++ b/MakeInout.v
@ -1,23 +0,0 @@
-module MakeInout(
-  input         clock,
-  input         reset,
-  input  [15:0] io_in,
-  input         io_clk,
-  input         io_reset,
-  output [15:0] io_out
-);
-  wire [15:0] m_in; // @[GCD.scala 40:17]
-  wire  m_clk; // @[GCD.scala 40:17]
-  wire  m_reset; // @[GCD.scala 40:17]
-  wire [15:0] m_out; // @[GCD.scala 40:17]
-  rvdff m ( // @[GCD.scala 40:17]
-    .in(m_in),
-    .clk(m_clk),
-    .reset(m_reset),
-    .out(m_out)
-  );
-  assign io_out = m_out; // @[GCD.scala 42:8]
-  assign m_in = io_in; // @[GCD.scala 42:8]
-  assign m_clk = io_clk; // @[GCD.scala 42:8]
-  assign m_reset = io_reset; // @[GCD.scala 42:8]
-endmodule
--- a/README.md
+++ b/README.md
@ -1,27 +1,243 @@
-# EL2 SweRV RISC-V Core Chiselified Version from <> LAMPRO MELLON
+# Quasar RISC-V Core 1.0 from Lampro Mellon

-This repository contains the SweRV EL2 Core design in CHISEL
+This repository contains the SweRV-EL2 Core written in CHISEL named "Quasar".

-## Back ground
+## License

-The project is being made for learning purpose. Copy rights to the SweRV-EL2 belongs to Wrestern Digital
+By contributing to this project, you agree that your contribution is governed by [Apache-2.0](LICENSE).  
+Files under the [tools](tools/) directory may be available under a different license. Please review individual file for details.
+
+## Background
+
+Quasar is a Chiselified version of EL2 SweRV RISC-V Core.

 ## Directory Structure

-    ├── configs                 # Configurations Dir
-    │   └── snapshots           # Where generated configuration files are created
-    ├── design                  # Design root dir
-    │   ├── dbg                 #   Debugger
-    │   ├── dec                 #   Decode, Registers and Exceptions
-    │   ├── dmi                 #   DMI block
-    │   ├── exu                 #   EXU (ALU/MUL/DIV)
-    │   ├── ifu                 #   Fetch & Branch Prediction
-    │   ├── include             
-    │   ├── lib
-    │   └── lsu                 #   Load/Store
-    ├── docs
-    ├── tools                   # Scripts/Makefiles
-    └── testbench               # (Very) simple testbench
-        ├── asm                 #   Example assembly files
-        └── hex                 #   Canned demo hex files
+    ├── configs                                 # Configurations dir
+    ├── design 
+    │   ├── project 
+    │       ├── project 
+    │       └── target
+    │   ├── snapshots 
+    │       └── default                         # Where generated configuration files are created
+    │   ├── src 
+    │       ├── main                            
+    │           ├── resources                   
+    │               └── vsrc                    # Blackbox files dir
+    │           └── scala                       # Design root dir
+    │               ├── dbg                     # Debugger
+    │               ├── dec                     # Decode, Registers and Exceptions 
+    │               ├── dmi                     # DMI block
+    │               ├── exu                     # EXU (ALU/MUL/DIV)
+    │               ├── ifu                     # Fetch & Branch Prediction
+    │               ├── include                 # Bundles file
+    │               ├── lib                     # Bridges and Library
+    │               └── lsu                     # Load/Store    
+    │       └── test 
+    │   ├── target 
+    │   └── test_run_dir    
+    ├── doc                                     # PPA Report
+    ├── generated_rtl                           # Quasar wrapper
+    ├── testbench 
+    │   ├── asm                                 # Example assembly files
+    │   └── hex                                 # Canned demo hex files
+    ├── tools                                   # Scripts/Makefiles
+    ├── tracer_logs                             # generated log files
+    └── verif                                     
+        ├── LEC                                  
+        └── sim                                 # Simulation log/dump files

+## Dependencies
+
+- Verilator **(4.030 or later)** must be installed on the system if running with verilator.
+- Vcs must be installed on the system if running with vcs.
+- RISCV tool chain (based on gcc version 7.3 or higher) must be
+installed so that it can be used to prepare RISCV binaries to run.
+- Sbt **(1.3.13 or later)** must be installed on the system.
+
+## Quickstart guide
+
+1. Clone the repository
+2. Setup RV_ROOT to point to the path in your local filesystem
+3. Determine your configuration {optional}
+4. Run make with $RV_ROOT/tools/Makefile
+
+## Release Notes for this version
+Please see [release notes](release-notes.md) for changes and bug fixes in this version of Quasar.
+
+### Configurations
+
+Quasar can be configured by running the script:
+```
+    $RV_ROOT/configs/quasar.config 
+```
+For detailed help options.
+```
+    $RV_ROOT/configs/quasar.config -h 
+```
+For example, to build with a DCCM of size 64Kb:  
+```
+    $RV_ROOT/configs/quasar.config -dccm_size=64  
+```
+This will update the **default** snapshot in `$RV_ROOT/design/snapshots/default/` with parameters for a 64K DCCM.  
+
+Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot *dccm64* and refer to it during the build.  
+
+There are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via the `-target=name` option to quasar.config.
+
+This script derives the following consistent set of include files :  
+```
+$RV_ROOT/design/snapshots/default
+    ├── common_defines.vh                       # `defines for testbench or design
+    ├── defines.h                               # defines for C/assembly headers
+    ├── param.vh                            	# Design parameters
+    ├── pdef.vh                             	# Parameter structure
+    ├── pd_defines.vh                           # `defines for physical design
+    ├── perl_configs.pl                         # Perl %configs hash for scripting
+    ├── pic_map_auto.h                          # PIC memory map based on configure size
+    └── whisper.json                            # JSON file for swerv-iss
+```
+#### 1. Generate scala parameter  
+```
+    make -f $RV_ROOT/tools/Makefile conf
+```
+This script will run `quasar.config` and derives the include file:
+```
+$RV_ROOT/design/src/main/scala/lib
+    └── param.scala                             # Scala design parameters
+```
+### Running RTL Simulation
+
+while in a work directory:
+
+#### 1. Set the RV_ROOT environment variable to the root of the Quasar directory structure.
+
+Example for bash shell:  
+```
+    export RV_ROOT=$(pwd)  
+```
+Example for csh or its derivatives:  
+```
+    setenv RV_ROOT /path/to/QUASAR
+```    
+#### 2. Create your specific configuration
+
+ *(Skip if default is sufficient)*  
+*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)*. For example, if `mybuild` is the name for the snapshot:
+
+set BUILD_PATH environment variable:
+```
+    setenv BUILD_PATH snapshots/mybuild
+
+    $RV_ROOT/configs/quasar.config [configuration options..] -snapshot=mybuild
+```
+
+Snapshots are placed in `$BUILD_PATH` directory.
+
+#### 3. Run sbt
+```
+    make -f $RV_ROOT/tools/Makefile sbt_
+```
+This command will generate the Quasar wrapper in system verilog in the `generated_rtl` directory and runs the `reset_script.py`
+*   In the reset_script we do a post verilog-generation changes, these changes are as follows:
+    
+    * Replace `posedge reset` with `negedge reset`
+    * Replace `if (reset)` with `if (~reset)`
+
+#### 4. Running a simple Hello World program (verilator)
+```    
+    make -f $RV_ROOT/tools/Makefile
+```
+This command will build a verilator model of Quasar with AXI bus, and execute a short sequence of instructions that writes out "HELLO WORLD"
+to the bus.
+
+The simulation produces output on the screen like:
+```
+
+VerilatorTB: Start of sim
+
+----------------------------------
+Hello World from Quasar @LM     !!
+----------------------------------
+TEST_PASSED
+
+Finished : minstret = 437, mcycle = 922
+See "exec.log" for execution trace with register updates..
+
+```
+
+The simulation generates following files in `$RV_ROOT/verif/sim`:
+
+ `console.log` contains what the cpu writes to the console address of 0xd0580000.  
+ `exec.log` shows instruction trace with GPR updates.  
+ `trace_port.csv` contains a log of the trace port.
+ 
+ Other log files are `dec.log`, `exu.log`, `ifu.log`, `lsu.log` and `pic.log`,  generates in `$RV_ROOT/tracer_logs`.
+ 
+ When `debug=1` is provided, a vcd file `sim.vcd` is created and can be browsed by gtkwave or similar waveform viewers.
+
+You can re-execute simulation using:  
+```    
+    make -f $RV_ROOT/tools/Makefile verilator
+```
+The simulation run/build command has following generic form:
+```
+    make -f $RV_ROOT/tools/Makefile [<simulator>] [debug=1] [snapshot=mybuild] [target=<target>] [TEST=<test>] [TEST_DIR=<path_to_test_dir>]
+```
+where:
+``` 
+<simulator> -  can be 'verilator' (by default) , 'vcs' - Synopsys VCS. if not provided, 'make' cleans work directory, builds verilator executable and runs a test.
+debug=1     -  allows VCD generation for verilator and VCS and SHM waves for irun option.
+<target>    -  predefined CPU configurations 'default' ( by default), 'default_ahb', 'typical_pd', 'high_perf'. 
+TEST        -  allows to run a C (<test>.c) or assembly (<test>.s) test, hello_world is run by default. 
+TEST_DIR    -  alternative to test source directory testbench/asm or testbench/tests.
+<snapshot>  -  run and build executable model of custom CPU configuration, remember to provide 'snapshot' argument for runs on custom configurations.
+CONF_PARAMS -  allows to provide -set options to quasar.conf script to alter predefined targets parameters.
+```
+#### Default for VCS/Verilotor
+If you want to run default configuration on verilator use the following command
+```
+make -f $RV_ROOT/tools/Makefile
+``` 
+For VCS use
+```
+make -f $RV_ROOT/tools/Makefile vcs_all
+```
+Example:
+```
+    make -f $RV_ROOT/tools/Makefile verilator TEST=cmark
+```
+will build and simulate  `testbench/asm/cmark.c` program with verilator. 
+
+
+If you want to compile a test only, you can run:
+```
+    make -f $RV_ROOT/tools/Makefile program.hex TEST=<test> [TEST_DIR=/path/to/dir]
+```
+
+The Makefile uses  `snapshot/<target>/link.ld` file, generated by quasar.conf script by default to build test executable. User can provide test specific linker file in form `<test_name>.ld` to build the test executable, in the same directory with the test source.
+
+User also can create a test specific makefile in form `<test_name>.makefile`, containing building instructions how to create `program.hex` file used by simulation. The private makefile should be in the same directory as the test source. See examples in `testbench/asm` directory.
+
+*(`program.hex` file is loaded to instruction and LSU bus memory slaves and optionally to DCCM/ICCM at the beginning of simulation)*.
+
+User can build `program.hex` file by any other means and then run simulation with following command:
+
+    make -f $RV_ROOT/tools/Makefile <simulator>
+
+Note: You may need to delete `program.hex` file from work directory, when run a new test.
+
+The `$RV_ROOT/testbench/asm` directory contains following tests ready to simulate:
+```
+hello_world      - default tes to run, prints Hello World message to screen and console.log
+hello_world_dccm  - the same as above, but takes the string from preloaded DCCM.
+hello_world_iccm  - the same as hello_world, but loads the test code to ICCM via LSU to DMA bridge and then executes
+                  it from there. Runs on QUASAR with AXI4 buses only. 
+cmark             - coremark benchmark running with code and data in external memories
+cmark_dccm        - the same as above, running data and stack from DCCM (faster)
+cmark_iccm        - the same as above with preloaded code to ICCM. 
+```
+
+The `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISCV SW tools are not installed.
+
+**Note**: The testbench has a simple synthesizable bridge that allows you to load the ICCM via load/store instructions. This is only supported for AXI4 builds.
--- a/RELEASE-NOTE.md
+++ b/RELEASE-NOTE.md
@ -0,0 +1,6 @@
+# Quasar RISC-V Core 1.0 from Lampro Mellon
+
+## Release Notes
+~~~
+Initial release DATE 
+~~~
--- a/RVCExpander.anno.json
+++ b/RVCExpander.anno.json
@ -1,73 +0,0 @@
-[
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~RVCExpander|RVCExpander>io_out_rs2",
-    "sources":[
-      "~RVCExpander|RVCExpander>io_in"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~RVCExpander|RVCExpander>io_out_rd",
-    "sources":[
-      "~RVCExpander|RVCExpander>io_in"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~RVCExpander|RVCExpander>io_out_rs1",
-    "sources":[
-      "~RVCExpander|RVCExpander>io_in"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~RVCExpander|RVCExpander>io_legal",
-    "sources":[
-      "~RVCExpander|RVCExpander>io_in"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~RVCExpander|RVCExpander>io_out_bits",
-    "sources":[
-      "~RVCExpander|RVCExpander>io_in"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~RVCExpander|RVCExpander>io_rvc",
-    "sources":[
-      "~RVCExpander|RVCExpander>io_in"
-    ]
-  },
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~RVCExpander|RVCExpander>io_out_rs3",
-    "sources":[
-      "~RVCExpander|RVCExpander>io_in"
-    ]
-  },
-  {
-    "class":"logger.LogLevelAnnotation",
-    "globalLogLevel":{
-      
-    }
-  },
-  {
-    "class":"firrtl.EmitCircuitAnnotation",
-    "emitter":"firrtl.VerilogEmitter"
-  },
-  {
-    "class":"firrtl.options.TargetDirAnnotation",
-    "directory":"."
-  },
-  {
-    "class":"firrtl.options.OutputAnnotationFileAnnotation",
-    "file":"RVCExpander"
-  },
-  {
-    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
-    "targetDir":"."
-  }
-]
--- a/RVCExpander.fir
+++ b/RVCExpander.fir
--- a/RVCExpander.v
+++ b/RVCExpander.v
@ -1,404 +0,0 @@
-module RVCExpander(
-  input         clock,
-  input         reset,
-  input  [31:0] io_in,
-  output [31:0] io_out_bits,
-  output [4:0]  io_out_rd,
-  output [4:0]  io_out_rs1,
-  output [4:0]  io_out_rs2,
-  output [4:0]  io_out_rs3,
-  output        io_rvc,
-  output        io_legal
-);
-  wire  _T_3 = |io_in[12:5]; // @[RVC.scala 58:29]
-  wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[RVC.scala 58:20]
-  wire [4:0] _T_14 = {2'h1,io_in[4:2]}; // @[Cat.scala 29:58]
-  wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58]
-  wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
-  wire [4:0] _T_30 = {2'h1,io_in[9:7]}; // @[Cat.scala 29:58]
-  wire [27:0] _T_36 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
-  wire [6:0] _T_50 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 29:58]
-  wire [26:0] _T_58 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
-  wire [26:0] _T_80 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
-  wire [26:0] _T_111 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58]
-  wire [27:0] _T_138 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58]
-  wire [26:0] _T_169 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58]
-  wire [26:0] _T_200 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h27}; // @[Cat.scala 29:58]
-  wire [6:0] _T_211 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
-  wire [11:0] _T_213 = {_T_211,io_in[6:2]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_219 = {_T_211,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
-  wire [9:0] _T_228 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
-  wire [20:0] _T_243 = {_T_228,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_306 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h1,7'h6f}; // @[Cat.scala 29:58]
-  wire [31:0] _T_321 = {_T_211,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
-  wire  _T_332 = |_T_213; // @[RVC.scala 95:29]
-  wire [6:0] _T_333 = _T_332 ? 7'h37 : 7'h3f; // @[RVC.scala 95:20]
-  wire [14:0] _T_336 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_339 = {_T_336,io_in[6:2],12'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_343 = {_T_339[31:12],io_in[11:7],_T_333}; // @[Cat.scala 29:58]
-  wire  _T_351 = io_in[11:7] == 5'h0; // @[RVC.scala 97:14]
-  wire  _T_353 = io_in[11:7] == 5'h2; // @[RVC.scala 97:27]
-  wire  _T_354 = _T_351 | _T_353; // @[RVC.scala 97:21]
-  wire [6:0] _T_361 = _T_332 ? 7'h13 : 7'h1f; // @[RVC.scala 91:20]
-  wire [2:0] _T_364 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
-  wire [31:0] _T_379 = {_T_364,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_361}; // @[Cat.scala 29:58]
-  wire [31:0] _T_386_bits = _T_354 ? _T_379 : _T_343; // @[RVC.scala 97:10]
-  wire [4:0] _T_386_rd = _T_354 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 97:10]
-  wire [4:0] _T_386_rs2 = _T_354 ? _T_14 : _T_14; // @[RVC.scala 97:10]
-  wire [4:0] _T_386_rs3 = _T_354 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 97:10]
-  wire [25:0] _T_397 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
-  wire [30:0] _GEN_172 = {{5'd0}, _T_397}; // @[RVC.scala 104:23]
-  wire [30:0] _T_409 = _GEN_172 | 31'h40000000; // @[RVC.scala 104:23]
-  wire [31:0] _T_422 = {_T_211,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
-  wire [2:0] _T_426 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58]
-  wire  _T_428 = io_in[6:5] == 2'h0; // @[RVC.scala 108:30]
-  wire [30:0] _T_429 = _T_428 ? 31'h40000000 : 31'h0; // @[RVC.scala 108:22]
-  wire [6:0] _T_431 = io_in[12] ? 7'h3b : 7'h33; // @[RVC.scala 109:22]
-  wire [2:0] _GEN_1 = 3'h1 == _T_426 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
-  wire [2:0] _GEN_2 = 3'h2 == _T_426 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
-  wire [2:0] _GEN_3 = 3'h3 == _T_426 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
-  wire [2:0] _GEN_4 = 3'h4 == _T_426 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
-  wire [2:0] _GEN_5 = 3'h5 == _T_426 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
-  wire [2:0] _GEN_6 = 3'h6 == _T_426 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
-  wire [2:0] _GEN_7 = 3'h7 == _T_426 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
-  wire [24:0] _T_441 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_431}; // @[Cat.scala 29:58]
-  wire [30:0] _GEN_173 = {{6'd0}, _T_441}; // @[RVC.scala 110:43]
-  wire [30:0] _T_442 = _GEN_173 | _T_429; // @[RVC.scala 110:43]
-  wire [31:0] _T_443_0 = {{6'd0}, _T_397}; // @[RVC.scala 112:19 RVC.scala 112:19]
-  wire [31:0] _T_443_1 = {{1'd0}, _T_409}; // @[RVC.scala 112:19 RVC.scala 112:19]
-  wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_443_1 : _T_443_0; // @[RVC.scala 27:14]
-  wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_422 : _GEN_9; // @[RVC.scala 27:14]
-  wire [31:0] _T_443_3 = {{1'd0}, _T_442}; // @[RVC.scala 112:19 RVC.scala 112:19]
-  wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_443_3 : _GEN_10; // @[RVC.scala 27:14]
-  wire [31:0] _T_533 = {_T_243[20],_T_243[10:1],_T_243[11],_T_243[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
-  wire [4:0] _T_542 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
-  wire [12:0] _T_551 = {_T_542,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58]
-  wire [31:0] _T_600 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
-  wire [31:0] _T_667 = {_T_551[12],_T_551[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_551[4:1],_T_551[11],7'h63}; // @[Cat.scala 29:58]
-  wire  _T_673 = |io_in[11:7]; // @[RVC.scala 118:27]
-  wire [6:0] _T_674 = _T_673 ? 7'h3 : 7'h1f; // @[RVC.scala 118:23]
-  wire [25:0] _T_683 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
-  wire [28:0] _T_699 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
-  wire [27:0] _T_714 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_674}; // @[Cat.scala 29:58]
-  wire [27:0] _T_729 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
-  wire [24:0] _T_739 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
-  wire [24:0] _T_750 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
-  wire [24:0] _T_761 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
-  wire [24:0] _T_763 = {_T_761[24:7],7'h1f}; // @[Cat.scala 29:58]
-  wire [24:0] _T_766 = _T_673 ? _T_761 : _T_763; // @[RVC.scala 139:33]
-  wire  _T_772 = |io_in[6:2]; // @[RVC.scala 140:27]
-  wire [31:0] _T_743_bits = {{7'd0}, _T_739}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _T_770_bits = {{7'd0}, _T_766}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _T_773_bits = _T_772 ? _T_743_bits : _T_770_bits; // @[RVC.scala 140:22]
-  wire [4:0] _T_773_rd = _T_772 ? io_in[11:7] : 5'h0; // @[RVC.scala 140:22]
-  wire [4:0] _T_773_rs1 = _T_772 ? 5'h0 : io_in[11:7]; // @[RVC.scala 140:22]
-  wire [4:0] _T_773_rs2 = _T_772 ? io_in[6:2] : io_in[6:2]; // @[RVC.scala 140:22]
-  wire [4:0] _T_773_rs3 = _T_772 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 140:22]
-  wire [24:0] _T_779 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
-  wire [24:0] _T_781 = {_T_761[24:7],7'h73}; // @[Cat.scala 29:58]
-  wire [24:0] _T_782 = _T_781 | 25'h100000; // @[RVC.scala 142:46]
-  wire [24:0] _T_785 = _T_673 ? _T_779 : _T_782; // @[RVC.scala 143:33]
-  wire [31:0] _T_755_bits = {{7'd0}, _T_750}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _T_789_bits = {{7'd0}, _T_785}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _T_792_bits = _T_772 ? _T_755_bits : _T_789_bits; // @[RVC.scala 144:25]
-  wire [4:0] _T_792_rd = _T_772 ? io_in[11:7] : 5'h1; // @[RVC.scala 144:25]
-  wire [4:0] _T_792_rs1 = _T_772 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 144:25]
-  wire [31:0] _T_794_bits = io_in[12] ? _T_792_bits : _T_773_bits; // @[RVC.scala 145:10]
-  wire [4:0] _T_794_rd = io_in[12] ? _T_792_rd : _T_773_rd; // @[RVC.scala 145:10]
-  wire [4:0] _T_794_rs1 = io_in[12] ? _T_792_rs1 : _T_773_rs1; // @[RVC.scala 145:10]
-  wire [4:0] _T_794_rs2 = io_in[12] ? _T_773_rs2 : _T_773_rs2; // @[RVC.scala 145:10]
-  wire [4:0] _T_794_rs3 = io_in[12] ? _T_773_rs3 : _T_773_rs3; // @[RVC.scala 145:10]
-  wire [8:0] _T_798 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
-  wire [28:0] _T_810 = {_T_798[8:5],io_in[6:2],5'h2,3'h3,_T_798[4:0],7'h27}; // @[Cat.scala 29:58]
-  wire [7:0] _T_818 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58]
-  wire [27:0] _T_830 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h23}; // @[Cat.scala 29:58]
-  wire [27:0] _T_850 = {_T_818[7:5],io_in[6:2],5'h2,3'h2,_T_818[4:0],7'h27}; // @[Cat.scala 29:58]
-  wire [4:0] _T_898 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58]
-  wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_17 = 5'h1 == _T_898 ? _T_44_bits : _T_24_bits; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_18 = 5'h1 == _T_898 ? _T_14 : _T_14; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_19 = 5'h1 == _T_898 ? _T_30 : 5'h2; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_21 = 5'h1 == _T_898 ? io_in[31:27] : io_in[31:27]; // @[RVC.scala 203:12]
-  wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_22 = 5'h2 == _T_898 ? _T_66_bits : _GEN_17; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_23 = 5'h2 == _T_898 ? _T_14 : _GEN_18; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_24 = 5'h2 == _T_898 ? _T_30 : _GEN_19; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_26 = 5'h2 == _T_898 ? io_in[31:27] : _GEN_21; // @[RVC.scala 203:12]
-  wire [31:0] _T_88_bits = {{5'd0}, _T_80}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_27 = 5'h3 == _T_898 ? _T_88_bits : _GEN_22; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_28 = 5'h3 == _T_898 ? _T_14 : _GEN_23; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_29 = 5'h3 == _T_898 ? _T_30 : _GEN_24; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_31 = 5'h3 == _T_898 ? io_in[31:27] : _GEN_26; // @[RVC.scala 203:12]
-  wire [31:0] _T_119_bits = {{5'd0}, _T_111}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_32 = 5'h4 == _T_898 ? _T_119_bits : _GEN_27; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_33 = 5'h4 == _T_898 ? _T_14 : _GEN_28; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_34 = 5'h4 == _T_898 ? _T_30 : _GEN_29; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_36 = 5'h4 == _T_898 ? io_in[31:27] : _GEN_31; // @[RVC.scala 203:12]
-  wire [31:0] _T_146_bits = {{4'd0}, _T_138}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_37 = 5'h5 == _T_898 ? _T_146_bits : _GEN_32; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_38 = 5'h5 == _T_898 ? _T_14 : _GEN_33; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_39 = 5'h5 == _T_898 ? _T_30 : _GEN_34; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_41 = 5'h5 == _T_898 ? io_in[31:27] : _GEN_36; // @[RVC.scala 203:12]
-  wire [31:0] _T_177_bits = {{5'd0}, _T_169}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_42 = 5'h6 == _T_898 ? _T_177_bits : _GEN_37; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_43 = 5'h6 == _T_898 ? _T_14 : _GEN_38; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_44 = 5'h6 == _T_898 ? _T_30 : _GEN_39; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_46 = 5'h6 == _T_898 ? io_in[31:27] : _GEN_41; // @[RVC.scala 203:12]
-  wire [31:0] _T_208_bits = {{5'd0}, _T_200}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_47 = 5'h7 == _T_898 ? _T_208_bits : _GEN_42; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_48 = 5'h7 == _T_898 ? _T_14 : _GEN_43; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_49 = 5'h7 == _T_898 ? _T_30 : _GEN_44; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_51 = 5'h7 == _T_898 ? io_in[31:27] : _GEN_46; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_52 = 5'h8 == _T_898 ? _T_219 : _GEN_47; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_53 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_48; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_54 = 5'h8 == _T_898 ? io_in[11:7] : _GEN_49; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_55 = 5'h8 == _T_898 ? _T_14 : _GEN_48; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_56 = 5'h8 == _T_898 ? io_in[31:27] : _GEN_51; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_57 = 5'h9 == _T_898 ? _T_306 : _GEN_52; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_58 = 5'h9 == _T_898 ? 5'h1 : _GEN_53; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_59 = 5'h9 == _T_898 ? io_in[11:7] : _GEN_54; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_60 = 5'h9 == _T_898 ? _T_14 : _GEN_55; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_61 = 5'h9 == _T_898 ? io_in[31:27] : _GEN_56; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_62 = 5'ha == _T_898 ? _T_321 : _GEN_57; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_63 = 5'ha == _T_898 ? io_in[11:7] : _GEN_58; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_64 = 5'ha == _T_898 ? 5'h0 : _GEN_59; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_65 = 5'ha == _T_898 ? _T_14 : _GEN_60; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_66 = 5'ha == _T_898 ? io_in[31:27] : _GEN_61; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_67 = 5'hb == _T_898 ? _T_386_bits : _GEN_62; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_68 = 5'hb == _T_898 ? _T_386_rd : _GEN_63; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_69 = 5'hb == _T_898 ? _T_386_rd : _GEN_64; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_70 = 5'hb == _T_898 ? _T_386_rs2 : _GEN_65; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_71 = 5'hb == _T_898 ? _T_386_rs3 : _GEN_66; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_72 = 5'hc == _T_898 ? _GEN_11 : _GEN_67; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_73 = 5'hc == _T_898 ? _T_30 : _GEN_68; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_74 = 5'hc == _T_898 ? _T_30 : _GEN_69; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_75 = 5'hc == _T_898 ? _T_14 : _GEN_70; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_76 = 5'hc == _T_898 ? io_in[31:27] : _GEN_71; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_77 = 5'hd == _T_898 ? _T_533 : _GEN_72; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_78 = 5'hd == _T_898 ? 5'h0 : _GEN_73; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_79 = 5'hd == _T_898 ? _T_30 : _GEN_74; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_80 = 5'hd == _T_898 ? _T_14 : _GEN_75; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_81 = 5'hd == _T_898 ? io_in[31:27] : _GEN_76; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_82 = 5'he == _T_898 ? _T_600 : _GEN_77; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_83 = 5'he == _T_898 ? _T_30 : _GEN_78; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_84 = 5'he == _T_898 ? _T_30 : _GEN_79; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_85 = 5'he == _T_898 ? 5'h0 : _GEN_80; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_86 = 5'he == _T_898 ? io_in[31:27] : _GEN_81; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_87 = 5'hf == _T_898 ? _T_667 : _GEN_82; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_88 = 5'hf == _T_898 ? 5'h0 : _GEN_83; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_89 = 5'hf == _T_898 ? _T_30 : _GEN_84; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_90 = 5'hf == _T_898 ? 5'h0 : _GEN_85; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_91 = 5'hf == _T_898 ? io_in[31:27] : _GEN_86; // @[RVC.scala 203:12]
-  wire [31:0] _T_688_bits = {{6'd0}, _T_683}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_92 = 5'h10 == _T_898 ? _T_688_bits : _GEN_87; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_93 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_88; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_94 = 5'h10 == _T_898 ? io_in[11:7] : _GEN_89; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_95 = 5'h10 == _T_898 ? io_in[6:2] : _GEN_90; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_96 = 5'h10 == _T_898 ? io_in[31:27] : _GEN_91; // @[RVC.scala 203:12]
-  wire [31:0] _T_703_bits = {{3'd0}, _T_699}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_97 = 5'h11 == _T_898 ? _T_703_bits : _GEN_92; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_98 = 5'h11 == _T_898 ? io_in[11:7] : _GEN_93; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_99 = 5'h11 == _T_898 ? 5'h2 : _GEN_94; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_100 = 5'h11 == _T_898 ? io_in[6:2] : _GEN_95; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_101 = 5'h11 == _T_898 ? io_in[31:27] : _GEN_96; // @[RVC.scala 203:12]
-  wire [31:0] _T_718_bits = {{4'd0}, _T_714}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_102 = 5'h12 == _T_898 ? _T_718_bits : _GEN_97; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_103 = 5'h12 == _T_898 ? io_in[11:7] : _GEN_98; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_104 = 5'h12 == _T_898 ? 5'h2 : _GEN_99; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_105 = 5'h12 == _T_898 ? io_in[6:2] : _GEN_100; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_106 = 5'h12 == _T_898 ? io_in[31:27] : _GEN_101; // @[RVC.scala 203:12]
-  wire [31:0] _T_733_bits = {{4'd0}, _T_729}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_107 = 5'h13 == _T_898 ? _T_733_bits : _GEN_102; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_108 = 5'h13 == _T_898 ? io_in[11:7] : _GEN_103; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_109 = 5'h13 == _T_898 ? 5'h2 : _GEN_104; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_110 = 5'h13 == _T_898 ? io_in[6:2] : _GEN_105; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_111 = 5'h13 == _T_898 ? io_in[31:27] : _GEN_106; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_112 = 5'h14 == _T_898 ? _T_794_bits : _GEN_107; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_113 = 5'h14 == _T_898 ? _T_794_rd : _GEN_108; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_114 = 5'h14 == _T_898 ? _T_794_rs1 : _GEN_109; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_115 = 5'h14 == _T_898 ? _T_794_rs2 : _GEN_110; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_116 = 5'h14 == _T_898 ? _T_794_rs3 : _GEN_111; // @[RVC.scala 203:12]
-  wire [31:0] _T_814_bits = {{3'd0}, _T_810}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_117 = 5'h15 == _T_898 ? _T_814_bits : _GEN_112; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_118 = 5'h15 == _T_898 ? io_in[11:7] : _GEN_113; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_119 = 5'h15 == _T_898 ? 5'h2 : _GEN_114; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_120 = 5'h15 == _T_898 ? io_in[6:2] : _GEN_115; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_121 = 5'h15 == _T_898 ? io_in[31:27] : _GEN_116; // @[RVC.scala 203:12]
-  wire [31:0] _T_834_bits = {{4'd0}, _T_830}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_122 = 5'h16 == _T_898 ? _T_834_bits : _GEN_117; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_123 = 5'h16 == _T_898 ? io_in[11:7] : _GEN_118; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_124 = 5'h16 == _T_898 ? 5'h2 : _GEN_119; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_125 = 5'h16 == _T_898 ? io_in[6:2] : _GEN_120; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_126 = 5'h16 == _T_898 ? io_in[31:27] : _GEN_121; // @[RVC.scala 203:12]
-  wire [31:0] _T_854_bits = {{4'd0}, _T_850}; // @[RVC.scala 26:19 RVC.scala 27:14]
-  wire [31:0] _GEN_127 = 5'h17 == _T_898 ? _T_854_bits : _GEN_122; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_128 = 5'h17 == _T_898 ? io_in[11:7] : _GEN_123; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_129 = 5'h17 == _T_898 ? 5'h2 : _GEN_124; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_130 = 5'h17 == _T_898 ? io_in[6:2] : _GEN_125; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_131 = 5'h17 == _T_898 ? io_in[31:27] : _GEN_126; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_132 = 5'h18 == _T_898 ? io_in : _GEN_127; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_133 = 5'h18 == _T_898 ? io_in[11:7] : _GEN_128; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_134 = 5'h18 == _T_898 ? io_in[19:15] : _GEN_129; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_135 = 5'h18 == _T_898 ? io_in[24:20] : _GEN_130; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_136 = 5'h18 == _T_898 ? io_in[31:27] : _GEN_131; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_137 = 5'h19 == _T_898 ? io_in : _GEN_132; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_138 = 5'h19 == _T_898 ? io_in[11:7] : _GEN_133; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_139 = 5'h19 == _T_898 ? io_in[19:15] : _GEN_134; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_140 = 5'h19 == _T_898 ? io_in[24:20] : _GEN_135; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_141 = 5'h19 == _T_898 ? io_in[31:27] : _GEN_136; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_142 = 5'h1a == _T_898 ? io_in : _GEN_137; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_143 = 5'h1a == _T_898 ? io_in[11:7] : _GEN_138; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_144 = 5'h1a == _T_898 ? io_in[19:15] : _GEN_139; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_145 = 5'h1a == _T_898 ? io_in[24:20] : _GEN_140; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_146 = 5'h1a == _T_898 ? io_in[31:27] : _GEN_141; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_147 = 5'h1b == _T_898 ? io_in : _GEN_142; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_148 = 5'h1b == _T_898 ? io_in[11:7] : _GEN_143; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_149 = 5'h1b == _T_898 ? io_in[19:15] : _GEN_144; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_150 = 5'h1b == _T_898 ? io_in[24:20] : _GEN_145; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_151 = 5'h1b == _T_898 ? io_in[31:27] : _GEN_146; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_152 = 5'h1c == _T_898 ? io_in : _GEN_147; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_153 = 5'h1c == _T_898 ? io_in[11:7] : _GEN_148; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_154 = 5'h1c == _T_898 ? io_in[19:15] : _GEN_149; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_155 = 5'h1c == _T_898 ? io_in[24:20] : _GEN_150; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_156 = 5'h1c == _T_898 ? io_in[31:27] : _GEN_151; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_157 = 5'h1d == _T_898 ? io_in : _GEN_152; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_158 = 5'h1d == _T_898 ? io_in[11:7] : _GEN_153; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_159 = 5'h1d == _T_898 ? io_in[19:15] : _GEN_154; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_160 = 5'h1d == _T_898 ? io_in[24:20] : _GEN_155; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_161 = 5'h1d == _T_898 ? io_in[31:27] : _GEN_156; // @[RVC.scala 203:12]
-  wire [31:0] _GEN_162 = 5'h1e == _T_898 ? io_in : _GEN_157; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_163 = 5'h1e == _T_898 ? io_in[11:7] : _GEN_158; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_164 = 5'h1e == _T_898 ? io_in[19:15] : _GEN_159; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_165 = 5'h1e == _T_898 ? io_in[24:20] : _GEN_160; // @[RVC.scala 203:12]
-  wire [4:0] _GEN_166 = 5'h1e == _T_898 ? io_in[31:27] : _GEN_161; // @[RVC.scala 203:12]
-  wire  _T_900 = ~io_in[13]; // @[RVC.scala 204:18]
-  wire  _T_902 = ~io_in[12]; // @[RVC.scala 204:31]
-  wire  _T_903 = _T_900 & _T_902; // @[RVC.scala 204:29]
-  wire  _T_905 = _T_903 & io_in[11]; // @[RVC.scala 204:42]
-  wire  _T_907 = _T_905 & io_in[1]; // @[RVC.scala 204:54]
-  wire  _T_909 = ~io_in[0]; // @[RVC.scala 204:65]
-  wire  _T_910 = _T_907 & _T_909; // @[RVC.scala 204:63]
-  wire  _T_917 = _T_903 & io_in[6]; // @[RVC.scala 205:32]
-  wire  _T_919 = _T_917 & io_in[1]; // @[RVC.scala 205:43]
-  wire  _T_922 = _T_919 & _T_909; // @[RVC.scala 205:52]
-  wire  _T_923 = _T_910 | _T_922; // @[RVC.scala 204:76]
-  wire  _T_925 = ~io_in[15]; // @[RVC.scala 206:8]
-  wire  _T_928 = _T_925 & _T_900; // @[RVC.scala 206:19]
-  wire  _T_931 = ~io_in[1]; // @[RVC.scala 206:43]
-  wire  _T_932 = io_in[11] >> _T_931; // @[RVC.scala 206:42]
-  wire  _T_934 = _T_928 & _T_932; // @[RVC.scala 206:32]
-  wire  _T_935 = _T_923 | _T_934; // @[RVC.scala 205:65]
-  wire  _T_942 = _T_903 & io_in[5]; // @[RVC.scala 207:32]
-  wire  _T_944 = _T_942 & io_in[1]; // @[RVC.scala 207:41]
-  wire  _T_947 = _T_944 & _T_909; // @[RVC.scala 207:50]
-  wire  _T_948 = _T_935 | _T_947; // @[RVC.scala 206:54]
-  wire  _T_955 = _T_903 & io_in[10]; // @[RVC.scala 208:32]
-  wire  _T_958 = _T_955 & _T_931; // @[RVC.scala 208:42]
-  wire  _T_960 = _T_958 & io_in[0]; // @[RVC.scala 208:54]
-  wire  _T_961 = _T_948 | _T_960; // @[RVC.scala 207:63]
-  wire  _T_968 = _T_928 & io_in[6]; // @[RVC.scala 209:32]
-  wire  _T_971 = _T_968 & _T_931; // @[RVC.scala 209:41]
-  wire  _T_972 = _T_961 | _T_971; // @[RVC.scala 208:64]
-  wire  _T_976 = io_in[15] & _T_902; // @[RVC.scala 209:65]
-  wire  _T_979 = _T_976 & _T_931; // @[RVC.scala 209:78]
-  wire  _T_981 = _T_979 & io_in[0]; // @[RVC.scala 209:90]
-  wire  _T_982 = _T_972 | _T_981; // @[RVC.scala 209:54]
-  wire  _T_989 = _T_903 & io_in[9]; // @[RVC.scala 210:32]
-  wire  _T_991 = _T_989 & io_in[1]; // @[RVC.scala 210:41]
-  wire  _T_994 = _T_991 & _T_909; // @[RVC.scala 210:50]
-  wire  _T_995 = _T_982 | _T_994; // @[RVC.scala 209:100]
-  wire  _T_999 = _T_902 & io_in[6]; // @[RVC.scala 211:19]
-  wire  _T_1002 = _T_999 & _T_931; // @[RVC.scala 211:28]
-  wire  _T_1004 = _T_1002 & io_in[0]; // @[RVC.scala 211:40]
-  wire  _T_1005 = _T_995 | _T_1004; // @[RVC.scala 210:63]
-  wire  _T_1012 = _T_928 & io_in[5]; // @[RVC.scala 212:32]
-  wire  _T_1015 = _T_1012 & _T_931; // @[RVC.scala 212:41]
-  wire  _T_1016 = _T_1005 | _T_1015; // @[RVC.scala 211:50]
-  wire  _T_1023 = _T_903 & io_in[8]; // @[RVC.scala 213:32]
-  wire  _T_1025 = _T_1023 & io_in[1]; // @[RVC.scala 213:41]
-  wire  _T_1028 = _T_1025 & _T_909; // @[RVC.scala 213:50]
-  wire  _T_1029 = _T_1016 | _T_1028; // @[RVC.scala 212:54]
-  wire  _T_1033 = _T_902 & io_in[5]; // @[RVC.scala 214:19]
-  wire  _T_1036 = _T_1033 & _T_931; // @[RVC.scala 214:28]
-  wire  _T_1038 = _T_1036 & io_in[0]; // @[RVC.scala 214:40]
-  wire  _T_1039 = _T_1029 | _T_1038; // @[RVC.scala 213:63]
-  wire  _T_1046 = _T_928 & io_in[10]; // @[RVC.scala 215:32]
-  wire  _T_1049 = _T_1046 & _T_931; // @[RVC.scala 215:42]
-  wire  _T_1050 = _T_1039 | _T_1049; // @[RVC.scala 214:50]
-  wire  _T_1057 = _T_903 & io_in[7]; // @[RVC.scala 215:82]
-  wire  _T_1059 = _T_1057 & io_in[1]; // @[RVC.scala 215:91]
-  wire  _T_1062 = _T_1059 & _T_909; // @[RVC.scala 215:100]
-  wire  _T_1063 = _T_1050 | _T_1062; // @[RVC.scala 215:55]
-  wire  _T_1066 = io_in[12] & io_in[11]; // @[RVC.scala 216:16]
-  wire  _T_1068 = ~io_in[10]; // @[RVC.scala 216:28]
-  wire  _T_1069 = _T_1066 & _T_1068; // @[RVC.scala 216:26]
-  wire  _T_1072 = _T_1069 & _T_931; // @[RVC.scala 216:39]
-  wire  _T_1074 = _T_1072 & io_in[0]; // @[RVC.scala 216:51]
-  wire  _T_1075 = _T_1063 | _T_1074; // @[RVC.scala 215:113]
-  wire  _T_1082 = _T_928 & io_in[9]; // @[RVC.scala 216:88]
-  wire  _T_1085 = _T_1082 & _T_931; // @[RVC.scala 216:97]
-  wire  _T_1086 = _T_1075 | _T_1085; // @[RVC.scala 216:61]
-  wire  _T_1093 = _T_903 & io_in[4]; // @[RVC.scala 217:32]
-  wire  _T_1095 = _T_1093 & io_in[1]; // @[RVC.scala 217:41]
-  wire  _T_1098 = _T_1095 & _T_909; // @[RVC.scala 217:50]
-  wire  _T_1099 = _T_1086 | _T_1098; // @[RVC.scala 216:110]
-  wire  _T_1102 = io_in[13] & io_in[12]; // @[RVC.scala 217:74]
-  wire  _T_1105 = _T_1102 & _T_931; // @[RVC.scala 217:84]
-  wire  _T_1107 = _T_1105 & io_in[0]; // @[RVC.scala 217:96]
-  wire  _T_1108 = _T_1099 | _T_1107; // @[RVC.scala 217:63]
-  wire  _T_1115 = _T_928 & io_in[8]; // @[RVC.scala 218:32]
-  wire  _T_1118 = _T_1115 & _T_931; // @[RVC.scala 218:41]
-  wire  _T_1119 = _T_1108 | _T_1118; // @[RVC.scala 217:106]
-  wire  _T_1126 = _T_903 & io_in[3]; // @[RVC.scala 218:81]
-  wire  _T_1128 = _T_1126 & io_in[1]; // @[RVC.scala 218:90]
-  wire  _T_1131 = _T_1128 & _T_909; // @[RVC.scala 218:99]
-  wire  _T_1132 = _T_1119 | _T_1131; // @[RVC.scala 218:54]
-  wire  _T_1135 = io_in[13] & io_in[4]; // @[RVC.scala 219:16]
-  wire  _T_1138 = _T_1135 & _T_931; // @[RVC.scala 219:25]
-  wire  _T_1140 = _T_1138 & io_in[0]; // @[RVC.scala 219:37]
-  wire  _T_1141 = _T_1132 | _T_1140; // @[RVC.scala 218:112]
-  wire  _T_1148 = _T_903 & io_in[2]; // @[RVC.scala 219:74]
-  wire  _T_1150 = _T_1148 & io_in[1]; // @[RVC.scala 219:83]
-  wire  _T_1153 = _T_1150 & _T_909; // @[RVC.scala 219:92]
-  wire  _T_1154 = _T_1141 | _T_1153; // @[RVC.scala 219:47]
-  wire  _T_1161 = _T_928 & io_in[7]; // @[RVC.scala 220:32]
-  wire  _T_1164 = _T_1161 & _T_931; // @[RVC.scala 220:41]
-  wire  _T_1165 = _T_1154 | _T_1164; // @[RVC.scala 219:105]
-  wire  _T_1168 = io_in[13] & io_in[3]; // @[RVC.scala 220:65]
-  wire  _T_1171 = _T_1168 & _T_931; // @[RVC.scala 220:74]
-  wire  _T_1173 = _T_1171 & io_in[0]; // @[RVC.scala 220:86]
-  wire  _T_1174 = _T_1165 | _T_1173; // @[RVC.scala 220:54]
-  wire  _T_1177 = io_in[13] & io_in[2]; // @[RVC.scala 221:16]
-  wire  _T_1180 = _T_1177 & _T_931; // @[RVC.scala 221:25]
-  wire  _T_1182 = _T_1180 & io_in[0]; // @[RVC.scala 221:37]
-  wire  _T_1183 = _T_1174 | _T_1182; // @[RVC.scala 220:96]
-  wire  _T_1187 = io_in[14] & _T_900; // @[RVC.scala 221:58]
-  wire  _T_1190 = _T_1187 & _T_931; // @[RVC.scala 221:71]
-  wire  _T_1191 = _T_1183 | _T_1190; // @[RVC.scala 221:47]
-  wire  _T_1193 = ~io_in[14]; // @[RVC.scala 222:8]
-  wire  _T_1196 = _T_1193 & _T_902; // @[RVC.scala 222:19]
-  wire  _T_1199 = _T_1196 & _T_931; // @[RVC.scala 222:32]
-  wire  _T_1201 = _T_1199 & io_in[0]; // @[RVC.scala 222:44]
-  wire  _T_1202 = _T_1191 | _T_1201; // @[RVC.scala 221:84]
-  wire  _T_1206 = io_in[15] & _T_900; // @[RVC.scala 222:65]
-  wire  _T_1208 = _T_1206 & io_in[12]; // @[RVC.scala 222:78]
-  wire  _T_1210 = _T_1208 & io_in[1]; // @[RVC.scala 222:88]
-  wire  _T_1213 = _T_1210 & _T_909; // @[RVC.scala 222:97]
-  wire  _T_1214 = _T_1202 | _T_1213; // @[RVC.scala 222:54]
-  wire  _T_1222 = _T_928 & _T_902; // @[RVC.scala 223:32]
-  wire  _T_1224 = _T_1222 & io_in[1]; // @[RVC.scala 223:45]
-  wire  _T_1227 = _T_1224 & _T_909; // @[RVC.scala 223:54]
-  wire  _T_1228 = _T_1214 | _T_1227; // @[RVC.scala 222:110]
-  wire  _T_1235 = _T_928 & io_in[12]; // @[RVC.scala 223:94]
-  wire  _T_1238 = _T_1235 & _T_931; // @[RVC.scala 223:104]
-  wire  _T_1239 = _T_1228 | _T_1238; // @[RVC.scala 223:67]
-  wire  _T_1246 = _T_1187 & _T_909; // @[RVC.scala 224:29]
-  assign io_out_bits = 5'h1f == _T_898 ? io_in : _GEN_162; // @[RVC.scala 203:12]
-  assign io_out_rd = 5'h1f == _T_898 ? io_in[11:7] : _GEN_163; // @[RVC.scala 203:12]
-  assign io_out_rs1 = 5'h1f == _T_898 ? io_in[19:15] : _GEN_164; // @[RVC.scala 203:12]
-  assign io_out_rs2 = 5'h1f == _T_898 ? io_in[24:20] : _GEN_165; // @[RVC.scala 203:12]
-  assign io_out_rs3 = 5'h1f == _T_898 ? io_in[31:27] : _GEN_166; // @[RVC.scala 203:12]
-  assign io_rvc = io_in[1:0] != 2'h3; // @[RVC.scala 201:12]
-  assign io_legal = _T_1239 | _T_1246; // @[RVC.scala 204:14]
-endmodule
--- a/caller.anno.json
+++ b/caller.anno.json
@ -1,25 +0,0 @@
-[
-  {
-    "class":"firrtl.transforms.CombinationalPath",
-    "sink":"~caller|caller>io_out",
-    "sources":[
-      "~caller|caller>io_in"
-    ]
-  },
-  {
-    "class":"firrtl.EmitCircuitAnnotation",
-    "emitter":"firrtl.VerilogEmitter"
-  },
-  {
-    "class":"firrtl.options.TargetDirAnnotation",
-    "directory":"."
-  },
-  {
-    "class":"firrtl.options.OutputAnnotationFileAnnotation",
-    "file":"caller"
-  },
-  {
-    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
-    "targetDir":"."
-  }
-]
--- a/caller.fir
+++ b/caller.fir
@ -1,20 +0,0 @@
-;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
-circuit caller : 
-  module rvdff : 
-    input clock : Clock
-    input reset : Reset
-    output io : {flip in : UInt<32>, out : UInt}
-    
-    io.out <= io.in @[GCD.scala 12:10]
-    
-  module caller : 
-    input clock : Clock
-    input reset : UInt<1>
-    output io : {flip in : UInt<32>, out : UInt}
-    
-    inst u0 of rvdff @[GCD.scala 21:18]
-    u0.clock <= clock
-    u0.reset <= reset
-    io.out <= u0.io.out @[GCD.scala 22:6]
-    u0.io.in <= io.in @[GCD.scala 22:6]
-    
--- a/caller.v
+++ b/caller.v
@ -1,21 +0,0 @@
-module rvdff(
-  input  [31:0] io_in,
-  output [31:0] io_out
-);
-  assign io_out = io_in; // @[GCD.scala 12:10]
-endmodule
-module caller(
-  input         clock,
-  input         reset,
-  input  [31:0] io_in,
-  output [31:0] io_out
-);
-  wire [31:0] u0_io_in; // @[GCD.scala 21:18]
-  wire [31:0] u0_io_out; // @[GCD.scala 21:18]
-  rvdff u0 ( // @[GCD.scala 21:18]
-    .io_in(u0_io_in),
-    .io_out(u0_io_out)
-  );
-  assign io_out = u0_io_out; // @[GCD.scala 22:6]
-  assign u0_io_in = io_in; // @[GCD.scala 22:6]
-endmodule
--- a/configs/README.md
+++ b/configs/README.md
@ -0,0 +1,43 @@
+# Quasar RISC-V Core from Lampro Mellon
+## Configuration
+
+### Contents
+Name                     | Description
+----------------------   | ------------------------------
+quasar.config            | Configuration script for core 
+quasar_config_gen.py     | Python wrapper to run quasar.config
+
+
+This script will generate a consistent set of `defines/#defines/parameters` needed for the design and testbench.  
+A perl hash (*perl_configs.pl*) and a JSON format for SweRV-iss are also generated.
+
+This set of include files :  
+```
+    ./snapshots/<target>
+    ├── common_defines.vh                       # `defines for testbench
+    ├── defines.h                               # #defines for C/assembly headers
+    ├── param.vh                            	# Actual Design parameters
+    ├── pdef.vh                             	# Parameter structure definition
+    ├── pd_defines.vh                           # `defines for physical design
+    ├── perl_configs.pl                         # Perl %configs hash for scripting
+    ├── pic_map_auto.h                          # PIC memory map based on configure size
+    ├── whisper.json                            # JSON file for swerv-iss
+    └── link.ld                                 # Default linker file for tests
+```
+
+While the defines may be modified by hand, it is recommended that this script be used to generate a consistent set.
+
+### Targets
+There are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via the `-target=name` option to quasar.config.
+
+Target                  | Description
+----------------------  | ------------------------------
+default                 | Default configuration. AXI4 bus interface. 
+default_ahb             | Default configuration, AHB-Lite bus interface
+typical_pd              | No ICCM, AXI4 bus interface
+high_perf               | Large BTB/BHT, AXI4 interface
+
+
+`quasar.config` may be edited to add additional target configurations, or new configurations may be created via the command line `-set` or `-unset` options.
+
+**Run `$RV_ROOT/configs/quasar.config -h` for options and settable parameters.**
--- a/configs/quasar.config
+++ b/configs/quasar.config
--- a/configs/quasar_config_gen.py
+++ b/configs/quasar_config_gen.py
@ -0,0 +1,57 @@
+#!/usr/bin/env python
+from fusesoc.capi2.generator import Generator
+import os
+import shutil
+import subprocess
+import sys
+import tempfile
+if sys.version[0] == '2':
+    devnull = open(os.devnull, 'w')
+else:
+    from subprocess import DEVNULL as devnull
+
+class SwervConfigGenerator(Generator):
+    def run(self):
+        script_root = os.path.abspath(os.path.join(os.path.dirname(sys.argv[0]), '..'))
+        files = [
+            {"configs/snapshots/default/common_defines.vh" : {
+                "copyto"    : "config/common_defines.vh",
+                "file_type" : "systemVerilogSource"}},
+            {"configs/snapshots/default/pdef.vh" : {
+                "copyto" : "config/pdef.vh",
+                "file_type" : "systemVerilogSource"}},
+            {"configs/snapshots/default/param.vh" : {
+                "is_include_file" : True,
+                "file_type" : "systemVerilogSource"}},
+            {"configs/snapshots/default/pic_map_auto.h" : {
+                "is_include_file" : True,
+                "file_type" : "systemVerilogSource"}}]
+
+        tmp_dir = os.path.join(tempfile.mkdtemp(), 'core')
+        shutil.copytree(script_root, tmp_dir)
+
+        cwd = tmp_dir
+
+        env = os.environ.copy()
+        env['RV_ROOT'] = tmp_dir
+        args = ['configs/quasar.config'] + self.config.get('args', [])
+        rc = subprocess.call(args, cwd=cwd, env=env, stdout=devnull)
+        if rc:
+            exit(1)
+
+        filenames = []
+        for f in files:
+            for k in f:
+                filenames.append(k)
+
+        for f in filenames:
+            d = os.path.dirname(f)
+            if d and not os.path.exists(d):
+                os.makedirs(d)
+            shutil.copy2(os.path.join(cwd, f),f)
+
+        self.add_files(files)
+
+g = SwervConfigGenerator()
+g.run()
+g.write()
--- a/configs/swerv.config~
+++ b/configs/swerv.config~
--- a/design/.idea/.gitignore
+++ b/design/.idea/.gitignore
--- a/design/.idea/.name
+++ b/design/.idea/.name
--- a/design/.idea/codeStyles/Project.xml
+++ b/design/.idea/codeStyles/Project.xml
--- a/design/.idea/codeStyles/codeStyleConfig.xml
+++ b/design/.idea/codeStyles/codeStyleConfig.xml
--- a/design/.idea/compiler.xml
+++ b/design/.idea/compiler.xml
--- a/design/.idea/edaphic/defines.xml
+++ b/design/.idea/edaphic/defines.xml
@ -0,0 +1,358 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="SVCompilerDirectivesDefines">
+    <option name="defines">
+      <map>
+        <entry key="$PROJECT_DIR$/el2_dec.v">
+          <value>
+            <map>
+              <entry key="RANDOM">
+                <value>
+                  <list>
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+              <entry key="RANDOMIZE">
+                <value>
+                  <list>
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+            </map>
+          </value>
+        </entry>
+        <entry key="$PROJECT_DIR$/el2_dec_decode_ctl.v">
+          <value>
+            <map>
+              <entry key="RANDOM">
+                <value>
+                  <list>
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+              <entry key="RANDOMIZE">
+                <value>
+                  <list>
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+            </map>
+          </value>
+        </entry>
+        <entry key="$PROJECT_DIR$/el2_dec_gpr_ctl.v">
+          <value>
+            <map>
+              <entry key="RANDOM">
+                <value>
+                  <list>
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+              <entry key="RANDOMIZE">
+                <value>
+                  <list>
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+            </map>
+          </value>
+        </entry>
+        <entry key="$PROJECT_DIR$/el2_dec_tlu_ctl.v">
+          <value>
+            <map>
+              <entry key="RANDOM">
+                <value>
+                  <list>
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+              <entry key="RANDOMIZE">
+                <value>
+                  <list>
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+            </map>
+          </value>
+        </entry>
+        <entry key="$PROJECT_DIR$/el2_exu_alu_ctl.v">
+          <value>
+            <map>
+              <entry key="RANDOM">
+                <value>
+                  <list>
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+              <entry key="RANDOMIZE">
+                <value>
+                  <list>
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+            </map>
+          </value>
+        </entry>
+        <entry key="$PROJECT_DIR$/el2_pic_ctrl.v">
+          <value>
+            <map>
+              <entry key="RANDOM">
+                <value>
+                  <list>
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+              <entry key="RANDOMIZE">
+                <value>
+                  <list>
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+            </map>
+          </value>
+        </entry>
+        <entry key="$PROJECT_DIR$/top.v">
+          <value>
+            <map>
+              <entry key="RANDOM">
+                <value>
+                  <list>
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+              <entry key="RANDOMIZE">
+                <value>
+                  <list>
+                    <Body />
+                    <Body />
+                    <Body />
+                    <Body />
+                  </list>
+                </value>
+              </entry>
+            </map>
+          </value>
+        </entry>
+      </map>
+    </option>
+    <option name="dependencies">
+      <map>
+        <entry key="FIRRTL_AFTER_INITIAL">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="FIRRTL_BEFORE_INITIAL">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="INIT_RANDOM">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="RANDOM">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="RANDOMIZE">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="RANDOMIZE_DELAY">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="RANDOMIZE_GARBAGE_ASSIGN">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="RANDOMIZE_INVALID_ASSIGN">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="RANDOMIZE_MEM_INIT">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="RANDOMIZE_REG_INIT">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="SYNTHESIS">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+        <entry key="VERILATOR">
+          <value>
+            <set>
+              <option value="$PROJECT_DIR$/el2_dec.v" />
+              <option value="$PROJECT_DIR$/el2_dec_decode_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_gpr_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_dec_tlu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_exu_alu_ctl.v" />
+              <option value="$PROJECT_DIR$/el2_pic_ctrl.v" />
+              <option value="$PROJECT_DIR$/src/main/resources/vsrc/el2_ifu_iccm_mem.sv" />
+              <option value="$PROJECT_DIR$/src/main/resources/vsrc/el2_lsu_dccm_mem.sv" />
+              <option value="$PROJECT_DIR$/top.v" />
+            </set>
+          </value>
+        </entry>
+      </map>
+    </option>
+    <option name="status" value="NORMAL" />
+    <option name="version" value="640" />
+  </component>
+</project>
--- a/design/.idea/inspectionProfiles/Project_Default.xml
+++ b/design/.idea/inspectionProfiles/Project_Default.xml
@ -0,0 +1,6 @@
+<component name="InspectionProjectProfileManager">
+  <profile version="1.0">
+    <option name="myName" value="Project Default" />
+    <inspection_tool class="ScalaStyle" enabled="false" level="WARNING" enabled_by_default="false" />
+  </profile>
+</component>
--- a/design/.idea/libraries/sbt__com_github_nscala_time_nscala_time_2_12_2_22_0_jar.xml
+++ b/design/.idea/libraries/sbt__com_github_nscala_time_nscala_time_2_12_2_22_0_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: com.github.nscala-time:nscala-time_2.12:2.22.0:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__com_github_scopt_scopt_2_12_3_7_1_jar.xml
+++ b/design/.idea/libraries/sbt__com_github_scopt_scopt_2_12_3_7_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: com.github.scopt:scopt_2.12:3.7.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__com_google_protobuf_protobuf_java_3_9_0_jar.xml
+++ b/design/.idea/libraries/sbt__com_google_protobuf_protobuf_java_3_9_0_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: com.google.protobuf:protobuf-java:3.9.0:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__com_lihaoyi_utest_2_12_0_6_6_jar.xml
+++ b/design/.idea/libraries/sbt__com_lihaoyi_utest_2_12_0_6_6_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: com.lihaoyi:utest_2.12:0.6.6:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__com_thoughtworks_paranamer_paranamer_2_8_jar.xml
+++ b/design/.idea/libraries/sbt__com_thoughtworks_paranamer_paranamer_2_8_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: com.thoughtworks.paranamer:paranamer:2.8:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml
+++ b/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: edu.berkeley.cs:chisel3_2.12:3.3.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_core_2_12_3_3_1_jar.xml
+++ b/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_core_2_12_3_3_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: edu.berkeley.cs:chisel3-core_2.12:3.3.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_macros_2_12_3_3_1_jar.xml
+++ b/design/.idea/libraries/sbt__edu_berkeley_cs_chisel3_macros_2_12_3_3_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: edu.berkeley.cs:chisel3-macros_2.12:3.3.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__edu_berkeley_cs_chisel_iotesters_2_12_1_4_1_jar.xml
+++ b/design/.idea/libraries/sbt__edu_berkeley_cs_chisel_iotesters_2_12_1_4_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: edu.berkeley.cs:chisel-iotesters_2.12:1.4.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__edu_berkeley_cs_chiseltest_2_12_0_2_1_jar.xml
+++ b/design/.idea/libraries/sbt__edu_berkeley_cs_chiseltest_2_12_0_2_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: edu.berkeley.cs:chiseltest_2.12:0.2.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml
+++ b/design/.idea/libraries/sbt__edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: edu.berkeley.cs:firrtl_2.12:1.3.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__edu_berkeley_cs_firrtl_interpreter_2_12_1_3_1_jar.xml
+++ b/design/.idea/libraries/sbt__edu_berkeley_cs_firrtl_interpreter_2_12_1_3_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: edu.berkeley.cs:firrtl-interpreter_2.12:1.3.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__edu_berkeley_cs_treadle_2_12_1_2_1_jar.xml
+++ b/design/.idea/libraries/sbt__edu_berkeley_cs_treadle_2_12_1_2_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: edu.berkeley.cs:treadle_2.12:1.2.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__joda_time_joda_time_2_10_1_jar.xml
+++ b/design/.idea/libraries/sbt__joda_time_joda_time_2_10_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: joda-time:joda-time:2.10.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__junit_junit_4_13_jar.xml
+++ b/design/.idea/libraries/sbt__junit_junit_4_13_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: junit:junit:4.13:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__net_jcazevedo_moultingyaml_2_12_0_4_2_jar.xml
+++ b/design/.idea/libraries/sbt__net_jcazevedo_moultingyaml_2_12_0_4_2_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: net.jcazevedo:moultingyaml_2.12:0.4.2:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_antlr_antlr4_runtime_4_7_1_jar.xml
+++ b/design/.idea/libraries/sbt__org_antlr_antlr4_runtime_4_7_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.antlr:antlr4-runtime:4.7.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_apache_commons_commons_lang3_3_9_jar.xml
+++ b/design/.idea/libraries/sbt__org_apache_commons_commons_lang3_3_9_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.apache.commons:commons-lang3:3.9:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_apache_commons_commons_text_1_8_jar.xml
+++ b/design/.idea/libraries/sbt__org_apache_commons_commons_text_1_8_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.apache.commons:commons-text:1.8:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_fusesource_jansi_jansi_1_11_jar.xml
+++ b/design/.idea/libraries/sbt__org_fusesource_jansi_jansi_1_11_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.fusesource.jansi:jansi:1.11:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_hamcrest_hamcrest_core_1_3_jar.xml
+++ b/design/.idea/libraries/sbt__org_hamcrest_hamcrest_core_1_3_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.hamcrest:hamcrest-core:1.3:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_joda_joda_convert_2_2_0_jar.xml
+++ b/design/.idea/libraries/sbt__org_joda_joda_convert_2_2_0_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.joda:joda-convert:2.2.0:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_json4s_json4s_ast_2_12_3_6_8_jar.xml
+++ b/design/.idea/libraries/sbt__org_json4s_json4s_ast_2_12_3_6_8_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.json4s:json4s-ast_2.12:3.6.8:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_json4s_json4s_core_2_12_3_6_8_jar.xml
+++ b/design/.idea/libraries/sbt__org_json4s_json4s_core_2_12_3_6_8_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.json4s:json4s-core_2.12:3.6.8:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_json4s_json4s_native_2_12_3_6_8_jar.xml
+++ b/design/.idea/libraries/sbt__org_json4s_json4s_native_2_12_3_6_8_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.json4s:json4s-native_2.12:3.6.8:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml
+++ b/design/.idea/libraries/sbt__org_json4s_json4s_scalap_2_12_3_6_8_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.json4s:json4s-scalap_2.12:3.6.8:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml
+++ b/design/.idea/libraries/sbt__org_portable_scala_portable_scala_reflect_2_12_0_1_0_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.portable-scala:portable-scala-reflect_2.12:0.1.0:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_scala_lang_modules_scala_jline_2_12_1_jar.xml
+++ b/design/.idea/libraries/sbt__org_scala_lang_modules_scala_jline_2_12_1_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.scala-lang.modules:scala-jline:2.12.1:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_scala_lang_modules_scala_xml_2_12_1_2_0_jar.xml
+++ b/design/.idea/libraries/sbt__org_scala_lang_modules_scala_xml_2_12_1_2_0_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.scala-lang.modules:scala-xml_2.12:1.2.0:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_scala_lang_scala_library_2_12_10_jar.xml
+++ b/design/.idea/libraries/sbt__org_scala_lang_scala_library_2_12_10_jar.xml
@ -15,9 +15,11 @@
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-library/2.12.10/scala-library-2.12.10-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_scala_lang_scala_reflect_2_12_10_jar.xml
+++ b/design/.idea/libraries/sbt__org_scala_lang_scala_reflect_2_12_10_jar.xml
@ -5,9 +5,11 @@
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-lang/scala-reflect/2.12.10/scala-reflect-2.12.10-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_scala_sbt_test_interface_1_0_jar.xml
+++ b/design/.idea/libraries/sbt__org_scala_sbt_test_interface_1_0_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.scala-sbt:test-interface:1.0:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_scalacheck_scalacheck_2_12_1_14_3_jar.xml
+++ b/design/.idea/libraries/sbt__org_scalacheck_scalacheck_2_12_1_14_3_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.scalacheck:scalacheck_2.12:1.14.3:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_scalactic_scalactic_2_12_3_0_8_jar.xml
+++ b/design/.idea/libraries/sbt__org_scalactic_scalactic_2_12_3_0_8_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.scalactic:scalactic_2.12:3.0.8:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_scalatest_scalatest_2_12_3_0_8_jar.xml
+++ b/design/.idea/libraries/sbt__org_scalatest_scalatest_2_12_3_0_8_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.scalatest:scalatest_2.12:3.0.8:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml
+++ b/design/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml
@ -2,12 +2,15 @@
  <library name="sbt: org.yaml:snakeyaml:1.26:jar">
    <CLASSES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar!/" />
    </CLASSES>
    <JAVADOC>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-javadoc.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-javadoc.jar!/" />
    </JAVADOC>
    <SOURCES>
      <root url="jar://$USER_HOME$/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-sources.jar!/" />
+      <root url="jar://$USER_HOME$/AppData/Local/Coursier/cache/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26-sources.jar!/" />
    </SOURCES>
  </library>
 </component>
--- a/design/.idea/misc.xml
+++ b/design/.idea/misc.xml
@ -0,0 +1,894 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="ProjectRootManager" version="2" languageLevel="JDK_1_8" default="false" project-jdk-name="11" project-jdk-type="JavaSDK" />
+  <component name="SVCompilerDirectivesDefines">
+    <option name="define">
+      <map>
+        <entry key="RANDOM">
+          <value>
+            <Define>
+              <option name="definitions">
+                <list>
+                  <Body>
+                    <option name="offset" value="153357" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="248582" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="266739" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="418463" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="619760" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="17721" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_exu.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="152503" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_dec_decode_ctl.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="9366" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_dec_tlu_ctl.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="13807" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="axi4_to_ahb.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="159032" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_pic_ctrl.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="477" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="top.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="67095" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_dec_gpr_ctl.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="17145" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_exu_alu_ctl.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="10031" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_lsu.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="411371" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="el2_ifu_mem_ctl.v" />
+                  </Body>
+                  <Body>
+                    <option name="offset" value="149445" />
+                    <option name="replacementList" value="$random" />
+                    <option name="source" value="dec.v" />
+                  </Body>
+                </list>
+              </option>
+              <option name="dependencies">
+                <set>
+                  <option value="el2_exu.v" />
+                  <option value="el2_dec_decode_ctl.v" />
+                  <option value="el2_dec_tlu_ctl.v" />
+                  <option value="axi4_to_ahb.v" />
+                  <option value="el2_pic_ctrl.v" />
+                  <option value="top.v" />
+                  <option value="el2_dec_gpr_ctl.v" />
+                  <option value="el2_exu_alu_ctl.v" />
+                  <option value="el2_lsu.v" />
+                  <option value="el2_ifu_mem_ctl.v" />
+                  <option value="dec.v" />
+                </set>
+              </option>
+            </Define>
+          </value>
+        </entry>
+        <entry key="RANDOMIZE">
+          <value>
+            <Define>
+              <option name="definitions">
+                <list>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="153158" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="153215" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_REG_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="153266" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_MEM_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="153317" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_GARBAGE_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="248383" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_INVALID_ASSIGN" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="248440" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
+                      <list>
+                        <InclusionDependency>
+                          <option name="name" value="RANDOMIZE_REG_INIT" />
+                          <option name="rule" value="DEFINED" />
+                        </InclusionDependency>
+                      </list>
+                    </option>
+                    <option name="offset" value="248491" />
+                    <option name="source" value="el2_dec.v" />
+                  </Body>
+                  <Body>
+                    <option name="inclusionDependencies">
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+                    <option name="source" value="dec.v" />
+                  </Body>
+                </list>
+              </option>
+            </Define>
+          </value>
+        </entry>
+      </map>
+    </option>
+    <option name="version" value="195" />
+  </component>
+</project>
--- a/design/.idea/modules.xml
+++ b/design/.idea/modules.xml
--- a/design/.idea/modules/chisel-module-template-build.iml
+++ b/design/.idea/modules/chisel-module-template-build.iml
--- a/design/.idea/modules/chisel-module-template.iml
+++ b/design/.idea/modules/chisel-module-template.iml
@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<module external.linked.project.id="swerv-chislified-master [file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
+<module external.linked.project.id="design [file:/home/waleedbinehsan/Downloads/Quasar/design/]" external.linked.project.path="$MODULE_DIR$/../.." external.root.project.path="$MODULE_DIR$/../.." external.system.id="SBT" type="JAVA_MODULE" version="4">
  <component name="NewModuleRootManager" LANGUAGE_LEVEL="JDK_1_8">
    <output url="file://$MODULE_DIR$/../../target/scala-2.12/classes" />
    <output-test url="file://$MODULE_DIR$/../../target/scala-2.12/test-classes" />
@ -7,6 +7,7 @@
    <content url="file://$MODULE_DIR$/../..">
      <sourceFolder url="file://$MODULE_DIR$/../../src/main/scala" isTestSource="false" />
      <sourceFolder url="file://$MODULE_DIR$/../../src/test/scala" isTestSource="true" />
+      <sourceFolder url="file://$MODULE_DIR$/../../src/main/resources" type="java-resource" />
      <excludeFolder url="file://$MODULE_DIR$/../../target" />
    </content>
    <orderEntry type="inheritedJdk" />
--- a/design/.idea/sbt.xml
+++ b/design/.idea/sbt.xml
--- a/design/.idea/scala_compiler.xml
+++ b/design/.idea/scala_compiler.xml
--- a/design/.idea/vcs.xml
+++ b/design/.idea/vcs.xml
@ -1,6 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <project version="4">
  <component name="VcsDirectoryMappings">
+    <mapping directory="$PROJECT_DIR$/.." vcs="Git" />
    <mapping directory="$PROJECT_DIR$" vcs="Git" />
  </component>
 </project>
--- a/design/build.sbt
+++ b/design/build.sbt
@ -3,8 +3,6 @@
 def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
  Seq() ++ {
    // If we're building with Scala > 2.11, enable the compile option
-    //  switch to support our anonymous Bundle definitions:
-    //  https://github.com/scala/bug/issues/10047
    CrossVersion.partialVersion(scalaVersion) match {
      case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq()
      case _ => Seq("-Xsource:2.11")
@ -26,12 +24,15 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
  }
 }

-name := "chisel-module-template"
+name := "QUASAR"

 version := "3.3.0"

 scalaVersion := "2.12.10"

+// Making the main-class
+mainClass in (Compile, run) := Some("wrapper")
+
 crossScalaVersions := Seq("2.12.10", "2.11.12")

 resolvers ++= Seq(
--- a/design/project/build.properties
+++ b/design/project/build.properties
--- a/design/project/plugins.sbt
+++ b/design/project/plugins.sbt
--- a/design/project/project/target/config-classes/$8bee9d95f9787aaf4e5c$.class
+++ b/design/project/project/target/config-classes/$8bee9d95f9787aaf4e5c$.class
--- a/design/project/project/target/config-classes/$8bee9d95f9787aaf4e5c.cache
+++ b/design/project/project/target/config-classes/$8bee9d95f9787aaf4e5c.cache
--- a/design/project/project/target/config-classes/$8bee9d95f9787aaf4e5c.class
+++ b/design/project/project/target/config-classes/$8bee9d95f9787aaf4e5c.class
--- a/design/project/target/.sbt-compilation-infos/swerv-chislified-compile/.sbt-idea-lock
+++ b/design/project/target/.sbt-compilation-infos/swerv-chislified-compile/.sbt-idea-lock
--- a/design/project/target/config-classes/$14a629a1a30b1d6a5b92$.class
+++ b/design/project/target/config-classes/$14a629a1a30b1d6a5b92$.class
--- a/project/project/target/config-classes/$eafbdd71b574e8cd9359.cache
+++ b/project/project/target/config-classes/$eafbdd71b574e8cd9359.cache
--- a/design/project/target/config-classes/$14a629a1a30b1d6a5b92.class
+++ b/design/project/target/config-classes/$14a629a1a30b1d6a5b92.class
--- a/design/project/target/config-classes/$1b1fd4333cba49d51a95$.class
+++ b/design/project/target/config-classes/$1b1fd4333cba49d51a95$.class
--- a/design/project/target/config-classes/$1b1fd4333cba49d51a95.cache
+++ b/design/project/target/config-classes/$1b1fd4333cba49d51a95.cache
--- a/design/project/target/config-classes/$1b1fd4333cba49d51a95.class
+++ b/design/project/target/config-classes/$1b1fd4333cba49d51a95.class
--- a/design/project/target/config-classes/$23656f1bb53449bbc075$.class
+++ b/design/project/target/config-classes/$23656f1bb53449bbc075$.class
--- a/design/project/target/config-classes/$23656f1bb53449bbc075.cache
+++ b/design/project/target/config-classes/$23656f1bb53449bbc075.cache
--- a/design/project/target/config-classes/$23656f1bb53449bbc075.class
+++ b/design/project/target/config-classes/$23656f1bb53449bbc075.class
--- a/design/project/target/config-classes/$5062e2f82ee6ba32d823$.class
+++ b/design/project/target/config-classes/$5062e2f82ee6ba32d823$.class
--- a/design/project/target/config-classes/$5062e2f82ee6ba32d823.cache
+++ b/design/project/target/config-classes/$5062e2f82ee6ba32d823.cache
--- a/design/project/target/config-classes/$5062e2f82ee6ba32d823.class
+++ b/design/project/target/config-classes/$5062e2f82ee6ba32d823.class
--- a/design/project/target/config-classes/$64ccd5b1b46d1506a13c$.class
+++ b/design/project/target/config-classes/$64ccd5b1b46d1506a13c$.class
--- a/design/project/target/config-classes/$64ccd5b1b46d1506a13c.cache
+++ b/design/project/target/config-classes/$64ccd5b1b46d1506a13c.cache
--- a/design/project/target/config-classes/$64ccd5b1b46d1506a13c.class
+++ b/design/project/target/config-classes/$64ccd5b1b46d1506a13c.class
--- a/design/project/target/config-classes/$6f6796a05610000bdb36$.class
+++ b/design/project/target/config-classes/$6f6796a05610000bdb36$.class
--- a/design/project/target/config-classes/$6f6796a05610000bdb36.cache
+++ b/design/project/target/config-classes/$6f6796a05610000bdb36.cache
--- a/design/project/target/config-classes/$6f6796a05610000bdb36.class
+++ b/design/project/target/config-classes/$6f6796a05610000bdb36.class
--- a/design/project/target/config-classes/$7b28455cc36758b9e814$.class
+++ b/design/project/target/config-classes/$7b28455cc36758b9e814$.class
--- a/design/project/target/config-classes/$7b28455cc36758b9e814.cache
+++ b/design/project/target/config-classes/$7b28455cc36758b9e814.cache
--- a/Show More
+++ b/Show More