0199f48087
Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented
2022-05-24 16:44:03 +01:00
d62861159f
First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.
2022-05-24 16:17:54 +01:00
2df1179994
Wire privilege through from core to bus masters. Tied off inside core.
2022-05-24 14:05:26 +01:00
c0b5d73cbd
Typo in for loop, surprised Yosys accepted this
2022-05-23 18:15:36 +01:00
5466c8131e
Sketch in PMP implementation
2022-05-23 18:06:23 +01:00
06647b78c6
Fix IALIGN fault to trap on the control flow instruction instead of its target
2022-05-23 16:25:43 +01:00
da244f54c3
Remove unused FAKE_DUALPORT option from regfile
2022-05-23 16:22:01 +01:00
f849517202
Split CSR addresses into separate header file
2022-05-23 15:54:37 +01:00
5f4127948d
Add a parameter to control register file reset, instead of the weird ifdef tree
2022-05-23 13:29:44 +01:00
df0fd536eb
Fix IRQ priority to match the priv spec
2022-05-23 12:56:37 +01:00
96a9ee18e1
Add IALIGN exception to non-RVC implementations
2022-05-23 12:47:48 +01:00
c4e81922da
Don't store bit 1 of mepc on non-RVC implementations
2022-05-23 12:27:07 +01:00
210dbeae64
Correct the name and operation of the brev8 (formerly rev.b) instruction
2022-05-20 15:28:18 +01:00
a2582976fc
Fix opcodes for zip/unzip, which are wrong in the bitmanip copy of the Zbkb spec, but correct in the crypto copy of that spec
2022-05-20 15:15:37 +01:00
43e0b1d16a
Implement Zbkb (untested)
2022-05-06 17:36:25 +01:00
2c8f3974d0
Correctly implement fence.i as branch-to-next. Make Zifencei optional. Tighten up decode on fence and fence.i.
2022-04-09 13:49:16 +01:00
35651f52a7
Stronger property for correct predecode
2022-04-05 08:18:00 +01:00
20cf408632
Add fine (as well as coarse) register predecode, so that predecoded regnum can be used in bypass zeroing.
2022-04-04 20:16:19 +01:00
357efac66e
Don't decode unnecessary bits in register predecode logic
2022-04-04 18:22:09 +01:00
be80bd4c18
Radical opinion, we should have good performance by default, not bad
2022-04-02 17:53:22 +01:00
7dc5046505
Perf option for dedicated branch comparator
2022-04-02 11:40:47 +01:00
3c61fae9ef
Remove the halfword fetch thing, was only really useful on RISCBoy
2022-04-02 10:54:16 +01:00
7b8fe43c1c
Fix bad timing of predecoded regnum register update (thanks BMC)
2022-04-02 10:11:55 +01:00
b80b09afe5
Typo -- fully encode all 128 possible IRQs
2022-03-15 09:01:55 +00:00
b0b8703ea4
Support up to 128 IRQs
2022-03-13 09:27:43 +00:00
887c93dbf0
Reuse predecoded regnums for bypass mux (though can't be used for zeroing unfortunately)
2022-03-02 18:35:16 +00:00
96c69d0bb0
Cut in->out paths on debug halt/resume request
...
Should be harmless, because in practice these should always be driven from a register
in the DM, but still better to cut the path
2022-03-01 21:14:49 +00:00
8fbffbe133
Assign full width of fifo_valid in non-reset clause (cosmetic fix)
2022-02-24 12:00:27 +00:00
9ed99d8695
Use define to guard X-checks, instead of hot comments
2022-02-24 10:35:16 +00:00
bf15b6c49f
Fix forward reference to net
2022-01-18 23:02:39 +00:00
0a369efc06
Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
2021-12-18 15:41:05 +00:00
1b0e205f87
Fix bad AMO asserts. Fix hwdata instability during stalled AMO write dphase, which meant AMOs were fundamentally broken following yesterday's datapath origami
2021-12-18 14:51:46 +00:00
6b8d4913ee
Remove unnecessary mux of mw_result -> m_result
2021-12-18 01:34:25 +00:00
79fec3a2f5
Overload mw_result register for capturing AMO read data. Save some LCs.
2021-12-18 01:24:26 +00:00
28b53ef7b5
Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.
2021-12-18 00:35:13 +00:00
7485269ddf
Use the branch target adder for load/store addresses. Preparing for AMO ALU deletion
2021-12-17 22:36:40 +00:00
a35739baf1
Fix AMO failing to loop on global monitor write fail
2021-12-17 17:04:22 +00:00
b0d28447ab
New license headers: DWTFPL -> Apache 2.0
2021-12-13 23:23:40 +00:00
f1cda26bcc
Oops, try a little harder this time to ensure local monitor is cleared by sc.w errors _always_, even if lined up with trap entry stalls etc
2021-12-12 23:32:01 +00:00
25b44d04cf
Add more properties wrt AMO. Fix awful bugs in interaction between AMOs and prior lr/sc, prior load/store exception, or IRQ which is asserted then deasserted. Fix sc with HRESP=1 HEXOKAY=1 not clearing the local monitor (not a bug, but unfriendly).
2021-12-12 23:24:25 +00:00
88fea7acfa
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs.
2021-12-12 18:28:23 +00:00
8a003dbbed
Make mcycle/minstret inhibited by default
2021-12-12 13:55:33 +00:00
2bbc3637a2
Simplify CSR update logic. Showed promise in block synth but no difference to example soc. Still cleaner RTL.
2021-12-12 00:38:30 +00:00
9460b3cd04
Add load/store and lr/sc bus fault tests. Fix lr.w not clearing local monitor when HRESP=1 HEXOKAY=1.
2021-12-11 15:52:34 +00:00
3d2c912b4f
Add test script to make it easier to add software testcases
2021-12-09 22:25:18 +00:00
7d2fa6a049
Fix width warnings in A instruction decode, add don't-care to bus rdata picking logic
2021-12-09 06:26:31 +00:00
116e34df49
Fix commented out frontend properties which relied on non-constant past reset values
2021-12-07 20:24:29 +00:00
449348f459
Fix bug where an IRQ can fire during load/store dphase, followed by dphase bus exception.
...
Result was that the exception would sample the IRQ vector PC rather than the load/store instruction PC.
Fix by fencing off on in-flight dphases before asserting the IRQ. This adds a cycle of jitter
to IRQs, but is required for correct operation without adding a full exception-gathering pipeline.
2021-12-07 19:24:53 +00:00
6ef3503ef5
Add A bit to MISA, update docs
2021-12-07 05:10:20 +00:00
93be227d8a
Add (currently failing) trap entry property. Fails when an IRQ arrives during a load/store data phase which subsequently excepts.
2021-12-06 20:12:23 +00:00
ed22d502fd
Fix bus stall getting stuck high when a bus fault exception isn't immediately accepted by the frontend
2021-12-06 19:28:21 +00:00
50d3d5d3b3
Maintain AMO IRQ holdoff when transitioning from data phase to error phase, to prevent error possibly being flushed
2021-12-06 19:27:20 +00:00
29c5c8ca7f
Fix AMO stall falling through when write data phase should proceed to error phase
2021-12-06 18:28:56 +00:00
8bfc089660
Slightly more strict holdoff of IRQs on AMO
2021-12-06 18:13:43 +00:00
0b3629564c
Don't apply shifter assertions to rotates
2021-12-06 18:12:23 +00:00
4c532240f8
Hold off IRQ when AMO is past the point of no return
2021-12-06 07:45:13 +00:00
260491405a
Fix atomic instructions not asserting decode error when A extension is disabled
2021-12-06 07:28:50 +00:00
cc38f46848
Fix AMO wdata valid left high when entering trap at just the right time
2021-12-06 07:28:50 +00:00
12c79c0b41
Fix feature-flag for Zbs instructions in decoder
2021-12-05 02:05:35 +00:00
9b9120960d
Fix missing RAW stall on sc.w succes result. Closing laptop again.
2021-12-05 01:05:01 +00:00
df658d86ff
First plausibly working AMOs. Add AMOs to instruction timings list
2021-12-04 23:44:22 +00:00
5c098866f2
Sketch in AMO support
2021-12-04 20:46:39 +00:00
34e57f0b14
Sketch in an AMO ALU
2021-12-04 18:52:41 +00:00
a8933c332d
Fix illegal issue of pipelined exclusives on the bus, and document correct timings
2021-12-04 18:23:01 +00:00
5e17bb805e
Add basic support for lr/sc instructions from the A extension
2021-12-04 15:02:31 +00:00
607147f280
Rewrite byte pick/sign-extend logic, preparing to handle more memops
2021-12-04 12:08:54 +00:00
a988adfec8
Add RISC-V opcodes and memory operation codes for atomics
2021-12-04 11:16:24 +00:00
52ba930638
Remove useless midcr.eivect feature. Make mlei left-shift its value by 2.
2021-12-04 01:17:57 +00:00
dfb07822ee
Remove UART DTM
2021-12-02 02:08:16 +00:00
be6b2f3f76
Fix up DTMs to use byte addressing
2021-12-02 02:05:23 +00:00
1ebccb7cce
Switch DM to use byte addresses on APB, not word addresses
2021-12-02 01:47:30 +00:00
c5e85dea4c
Add mconfigptr CSR
2021-12-01 03:25:56 +00:00
c8afb4ac33
Add option for fast high-half multiplies
2021-11-29 18:48:02 +00:00
94a3d43f27
Add Hazard3's registered marchid value to hdl and docs
2021-11-28 19:53:49 +00:00
1aa9dbcddd
Fix comment typo in APB clock crossing
2021-11-28 17:40:57 +00:00
e7466ae4be
Move DM data0 CSR into the M-custom space, and document this
2021-11-28 15:52:52 +00:00
76172cdade
Start filling out CSR documentation. Change misa to report X=1 because of nonstandard IRQ CSRs.
2021-11-28 06:33:35 +00:00
800b21d2f5
Remove event feedback path (not logical path) in priority encoder
2021-11-28 02:19:01 +00:00
14a4f1a281
Add bitmanip reference vectors and test scripts. Fix bug in bclr implementation
2021-11-27 17:19:41 +00:00
5d093487b7
Update README
2021-11-26 23:33:46 +00:00
1bb7e33b69
Fix alignment of heap_ptr in init.S. Small ALU cleanup
2021-11-26 02:59:50 +00:00
8bcec11c80
Couple more silly mistakes
2021-11-26 01:30:13 +00:00
41eeb90c7d
Remove (safe) feedback path which Verilator linted on -- CXXRTL doesn't hate me any more
2021-11-26 01:29:47 +00:00
998f3fdeb7
Clean up silly mistakes
2021-11-26 00:55:57 +00:00
58c20a39d0
First pass at implementing bitmanip. Breaks CXXRTL. Ooop
2021-11-25 23:30:35 +00:00
ed6b6a3660
Cleanup order of declaration/use of a couple of wires
2021-11-25 15:16:59 +00:00
49462a8642
Add Zba/Zbb/Zbc/Zbs opcodes to rv_opcodes.vh
2021-11-23 22:11:50 +00:00
e05e9a4109
Add default_nettype none at top of every file, and default_nettype wire at bottom
2021-11-23 22:10:39 +00:00
0b9b706e81
Safer logic for load/store blocked by preceding WFI
2021-11-23 22:01:14 +00:00
cc6a6c09ba
Vaguely implement wfi
2021-11-05 18:48:42 +00:00
cfe16caf41
Remove some old todos
2021-09-05 22:20:40 +01:00
e9fccffca0
Fix break and single-step on a load/store access fault dropping the exception. Better fix for halt request on definitely-excepting stage M instruction giving unreachable next-instruction DPC.
2021-09-05 04:45:38 +01:00
65bfca5fdf
Fix latent bug with asynchronous debug entry during stalled load/store address phase
2021-09-04 07:49:29 +01:00
d03a82a826
Add instruction fetch faults
2021-09-04 02:57:39 +01:00
e16ae06cb5
Clean up timer
2021-08-21 17:03:32 +01:00
9dd091b7b5
Doh typo
2021-08-21 09:06:20 +01:00
b99e5b8a67
Convert timer to serial for smaller area. Rather untested
2021-08-20 22:27:15 +01:00
4aba165166
First pass at a 64-bit system timer
2021-08-20 21:49:05 +01:00
8263ee3a5d
Fix reporting DPC after an excepting instruction when halt request is simultaneous with exception
2021-07-24 15:31:33 +01:00
70a44d9681
Small code cleanup
2021-07-24 10:08:27 +01:00
155d3ba554
Tie off 1 or 2 LSBs of DPC depending on IALIGN
2021-07-23 23:09:03 +01:00
115cb2c50f
Tweaks to example soc configuration
2021-07-23 23:08:23 +01:00
279e4b4f29
Implement mstatush as hardwired-0, as required by priv-1.12
2021-07-23 21:52:01 +01:00
2ae30183aa
Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.
2021-07-23 18:32:47 +01:00
8ceae7e9e6
Start hacking on ECP5 JTAG DTM
2021-07-23 00:36:55 +01:00
41477ce479
Extract DTM bus/control logic from the JTAG-related parts
2021-07-22 19:26:25 +01:00
8cdde82248
Coding style tweaks for ALU to workaround upstream Yosys issue, see #1 and friends
2021-07-20 00:13:26 +01:00
7d24f42da9
Oops, properly fix platform IRQ mcause numbers
2021-07-19 09:32:59 +01:00
65fb62901e
Mask off trap entry assertion from IRQs when in debug mode. Because the IRQ is level-sensitive, this caused trap entry to be held asserted when an IRQ fired in debug mode. This was exposed by the last bug fix -- it is only seen now that MIE+MPIE shuffling is correctly disabled in debug mode.
2021-07-19 00:19:56 +01:00
70443fa557
Disable shifting of MIE/MPIE stack when in or entering debug mode
2021-07-18 21:14:11 +01:00
d30fc46f5b
Fix IRQ mcause not being set correctly when vectoring is disabled
2021-07-18 20:44:39 +01:00
e95b465e26
Typo in address of mcountinhibit!
2021-07-17 19:27:01 +01:00
d9300ee127
Fix bad handshake on bus error response (need to report both phases of response, to get clean exception entry
2021-07-17 19:26:45 +01:00
5deff12f95
DM: don't report as running/halted in dmstatus if unavailable.
2021-07-17 16:46:39 +01:00
ab0b4a04f0
Also support progbuf in abstractauto.
2021-07-17 15:08:00 +01:00
8e3dc62b97
Fiddly handshake changes for hardware single-stepping. Can now step correctly through illegal instructions
2021-07-16 20:43:24 +01:00
5aca6be572
Implement data0 inside of DM instead of core, so it gets correct reset. Add dummy tselect CSR.
2021-07-16 18:28:30 +01:00
ce5152a4f4
Implement HALTSUM0 and HALTSUM1 registers
2021-07-16 17:58:28 +01:00
011008efd1
Fix detection of exception-like vs IRQ-like halt/trap entries
2021-07-15 19:41:35 +01:00
71ec9fa283
Fix exception entry not counting as a step point for dcsr.step, and mask off IRQs in step mode (we tie dcsr.stepie = 0)
2021-07-14 20:39:51 +01:00
f4952ab66d
Add simple example SoC, hangs nextpnr for some reason!
2021-07-13 03:40:06 +01:00
307955c810
Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference
2021-07-13 01:10:55 +01:00
93c7039ea1
Sync doc updates
2021-07-12 22:13:31 +01:00
4b650ac437
DM: add missing w1c to abstract cmderr, add capture of last abstract command for use with abstractauto
2021-07-12 21:26:00 +01:00
42632e325a
Fix brokenness of JTAG-DTM and CDC, add openocd remote bitbang testbench for DTM + DM + core
2021-07-12 21:21:16 +01:00
27674be996
Start hacking in a JTAG-DTM
2021-07-12 01:49:32 +01:00
f7b3097ad6
Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works
2021-07-11 16:20:39 +01:00
0dce59daaf
Start hacking together a DM
2021-07-11 05:11:19 +01:00
5cc483898d
Add smoke test for core debug interface, and suppress bus fetch incrementing frontend level counter when in debug mode
2021-07-10 21:02:18 +01:00
63d661af63
Start hacking in debug support to the core -- seems to work as well as before adding debug!
2021-07-10 18:53:48 +01:00
83244c6651
Add Read ID command to UART DTM
2021-07-10 16:14:35 +01:00
3312ea7022
Add draft UART DTM
2021-07-08 17:57:46 +01:00
6a38fc33a6
Allow MHARTID to be configured at instantiation
2021-07-07 16:08:08 +01:00
278dc8b6a2
meie0 default to all-zeroes
2021-06-04 07:37:02 +01:00
af684c4e82
Some cleanup; correctly decode 16-bit EBREAK
2021-06-03 20:03:43 +01:00
5f8d217395
Implement new IRQ behaviour, and change mip.meip to be masked by individual enables in meip0
2021-05-31 17:54:12 +01:00
12851d3742
Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set
2021-05-30 19:52:46 +01:00
cec5dc4e3b
Remove old MCYCLE/MCYCLEH, implement MCOUNTINHIBIT fully, always decode tied-off HPM counters
2021-05-30 19:20:53 +01:00
565b76672a
Make MVENDORID/MARCHID/MIMPID configurable
2021-05-30 18:42:43 +01:00
2330b84b73
Use .f for riscv-formal tb dependencies, small reshuffling of directories
2021-05-30 09:44:57 +01:00
ad8f251ba2
RVFI wrapper: use proper bus assumptions. RVFI monitor: don't mark instruction which is aligned with IRQ as invalid, because the IRQ entry is notionally behind it
2021-05-29 23:24:02 +01:00
ea5db61582
Fix exception being passed to M when X is stalled but M is not (a load which had an unaligned address spuriously during a RAW stall on the result register)
2021-05-29 22:52:50 +01:00
4b9a3c2c78
Fix wrong reg readaddr when D starvation ends during a downstream load/store dphase stall (was using garbage from D instead of new fetch data predecoded in F)
2021-05-29 19:32:12 +01:00
f23ec3f941
Don't hold back instruction in M when an IRQ entry is stalled (but do for exception entry). Now pass add and lw checks in riscv-formal with depth 15, so getting somewhere
2021-05-29 18:57:43 +01:00
65075df0e5
More work on traps, delaying IRQs which arrive whilst a load/store address phase is stalled to avoid deassertion on the bus
2021-05-29 18:00:43 +01:00
1b252d4bda
Significant overhaul of trap handling. Exceptions now taken from stage 3 instead of stage 2
2021-05-23 11:59:46 +01:00
5e61c9f9ac
Use branch target adder for JALR target, and use ALU for JAL/JALR linkaddr instead of muxing in next_pc
2021-05-23 09:12:50 +01:00
90acfdcbe8
Organise test directory into formal and sim
2021-05-23 07:42:35 +01:00
7a3ce494e4
Fix a couple issues with trap exit, can now run add check with traps enabled (at low depth)
2021-05-23 06:40:44 +01:00
dec78a728d
Fix a few things that were obviously wrong, and the first signs of a plausible RVFI bridge circuit
2021-05-22 15:35:52 +01:00
08e986912c
Also fix RAW stall on JALR instructions, oops. Runs CoreMark and Dhrystone now
2021-05-22 11:18:56 +01:00
6692c1f26d
Fix premature taking of branches with RAW data dependencies on the previous instruction
2021-05-22 10:18:47 +01:00
cc6f590f2e
Fix some issues in predecode of register numbers for compressed ISA. RV32IC compliance now passes, hello world does not work still
2021-05-22 10:16:02 +01:00
692abbad8b
Merge stages D and X, and bring all branch resolution into X. Passes RV32I compliance
2021-05-22 07:55:13 +01:00
844fa8f97f
Rename hazard5 -> hazard3
2021-05-21 03:46:29 +01:00
5de4f01aae
Change how constants are plumbed through the hierarchy. Some small cleanups of variable declaration order etc
2021-05-21 03:23:44 +01:00
6dad4e20bb
Import from hazard5 9743a1b
2021-05-21 02:34:16 +01:00
Luke Wren
Luke Wren